Discrete device packaging structure

Abstract

The utility model provides a discrete device packaging structure, the packaging structure comprises a heat conduction substrate, a through hole, a chip, a lead, a pin and a packaging layer, the heat conduction substrate comprises a first metal layer, a second metal layer and an insulation heat conduction layer, the first metal layer comprises a first area and a plurality of second areas provided with lead areas, at least one second area is provided with a welding area communicated with the lead area in the second area; the at least one through hole penetrates through the heat conducting substrate at the corresponding position of the first area; the chip is welded in the welding area; the leads are electrically connected with the chip and the corresponding lead areas respectively; the plurality of pins are electrically connected with the corresponding lead areas respectively; the packaging layer covers the first metal layer, the chip, one end, close to the lead area, of the pin, the exposed surface of the lead and the inner wall of the through hole. According to the utility model, the heat conduction substrate is used as the substrate for welding the chip, so that the heat dissipation capability of the packaging structure is improved, the welding of the heat dissipation structure is facilitated, and meanwhile, through the arrangement of the through holes, the packaging structure is more convenient to install on a machine.

Description

Technical Field

[0001] The utility model belongs to the technical field of discrete device packaging, and relates to a discrete device packaging structure. Background Art

[0002] Power semiconductors are the core devices for power electronic energy conversion and circuit control. In recent years, power devices such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs for short) and Insulated Gate Bipolar Transistors (IGBTs for short) have developed rapidly towards high power density, and their current-carrying capacity and voltage-carrying capacity have also increased significantly. For discrete devices composed of power devices, the voltage and current required for a single transistor are getting higher and higher. At the same time, the application environment has higher and higher requirements for packaging.

[0003] At present, a heat sink needs to be added to the back of a discrete device single transistor to enhance heat dissipation. Usually, the heat sink is not insulated from the inside of the discrete device. However, the heat sink needs to be insulated from the inside of the discrete device. Therefore, an additional ceramic sheet is required to insulate the heat sink from the inside of the discrete device. At the same time as adding the ceramic sheet, a layer of thermal grease also needs to be added between the ceramic sheet and the back of the packaging structure and between the ceramic sheet and the heat sink. This leads to an increase in the thermal resistance of the system and the cost, and the heat dissipation capacity of this structure is also limited. As Figure 1 shown, it includes a package body 01, pins 02, a thermal grease layer 03, a ceramic sheet 04, a heat sink 05, a PCB board 06, and screws 07. When a customer uses it on a machine, since it is difficult to drill holes in the ceramic sheet, it is difficult to fix the heat sink with screws, which brings inconvenience to the customer's use. In addition, discrete devices usually need to be soldered on a lead frame with an uneven upper surface, resulting in multiple soldering operations for discrete devices containing multiple chips, reducing the assembly accuracy and affecting the reliability of the packaging structure. At the same time, since the chips in the discrete device and between the chips and the lead frame are usually interconnected by bonding wires, and the area of the bonding leads in the lead frame is limited, the number of bonding wires that can be bonded in the bonding lead area is limited, restricting the current-carrying capacity of the discrete device. At the same time, in order to ensure the electrical performance of the discrete device, green oil needs to be set between the leads and pins of the discrete device to prevent solder from overflowing onto the leads during the process of soldering the pins, increasing the packaging cost and introducing secondary pollution.

[0004] Therefore, there is an urgent need to find a discrete device packaging structure that can improve the chip soldering accuracy, enhance the heat dissipation capacity, and facilitate customer installation. Summary of the Utility Model

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present utility model is to provide a discrete device packaging structure, which is used to solve the problems of poor heat dissipation ability of discrete devices, low soldering accuracy of chips and inconvenient installation for customers in the prior art.

[0006] To achieve the above object and other related objects, the present utility model provides a discrete device packaging structure, including:

[0007] A heat-conducting substrate, including a second metal layer, an insulating and heat-conducting layer, and a first metal layer stacked in sequence. The first metal layer includes a first region and a plurality of second regions spaced from the first region and at least provided with lead regions. Adjacent two of the second regions are spaced apart by a preset distance, and at least one of the second regions is provided with a soldering region communicating with the lead region in the second region;

[0008] At least one through hole penetrates the heat-conducting substrate at a corresponding position of the first region;

[0009] At least one chip is soldered to a surface of the soldering region facing away from the insulating and heat-conducting layer;

[0010] A plurality of leads are respectively electrically connected to the chip and each of the lead regions corresponding to the chip;

[0011] A plurality of pins are respectively electrically connected to the corresponding lead regions;

[0012] A packaging layer covers the exposed surfaces of the first metal layer, the chip, the end of the pin close to the lead region, the lead, and the inner wall of the through hole.

[0013] Optionally, the chip includes a MOSFET chip, an IGBT chip, an FRD chip, a JBS chip, an SBD chip; the heat-conducting substrate includes a DBC substrate and an AMB substrate.

[0014] Optionally, in the same lead region, there is at least one groove between the region where the pin is soldered and the region where the lead is bonded, and the depth range of the groove is 20% - 50% of the thickness of the first metal layer in the lead region.

[0015] Optionally, the soldering region is provided in a plurality of the second regions, and the lead is also electrically connected to the chip to be electrically connected and the soldering region.

[0016] Optionally, in the same second region, there is at least one groove between the lead region where the lead is bonded and the soldering region.

[0017] Optionally, the widths of the parts of different pins protruding from the packaging layer are different.

[0018] Optionally, multiple ones of the pins are led out from the same sidewall of the encapsulation layer, and at least one notch is provided in the sidewall of the encapsulation layer from which the pins are led out. The notch is located between two adjacent ones of the pins and opens on the surface of the sidewall of the encapsulation layer from which the pins are led out.

[0019] Optionally, the distance between the portion of the pin protruding from the encapsulation layer and the surface of the heat-conducting substrate exposed by the encapsulation layer ranges from 2.4 mm to 3.5 mm.

[0020] Optionally, a heat dissipation structure fixedly connected to the heat-conducting substrate is further provided on the surface of the heat-conducting substrate exposed by the encapsulation layer.

[0021] Optionally, a circuit board electrically connected to one end of the pin away from the encapsulation layer is further provided in the discrete device encapsulation structure.

[0022] As described above, the discrete device encapsulation structure of the present utility model improves the structure of the encapsulation structure. A heat-conducting substrate is used as the substrate for soldering the chip in the discrete device. The first metal layer in the heat-conducting substrate includes a first region and a second region, and through holes are provided in the first region, facilitating the subsequent fixed installation of the encapsulation structure through the through holes, making the installation of the encapsulation structure on the machine more convenient. The upper surface of the second region is flush, facilitating the synchronous formation of solder and synchronous soldering during the soldering of the pins and the chip, improving the soldering efficiency and soldering accuracy. The lead region in the second region can be adjusted to a larger size region according to the requirements of the functional circuit, increasing the number of bonding leads and enhancing the current-carrying capacity of the encapsulation structure. By providing grooves between the region where the leads are bonded in the lead region and the soldering region and between the region where the leads are bonded in the lead region and the region where the pins are soldered, the solder overflowing during the soldering of the pins and the chip can be blocked from overflowing onto the leads, eliminating the need to use green oil to block the solder from overflowing onto the leads, avoiding secondary pollution caused by the green oil, and reducing the encapsulation cost. In addition, a heat-conducting substrate including a first metal layer, an insulating heat-conducting layer, and a second metal layer is used as the substrate for soldering the chip in the discrete device. When soldering the heat dissipation device, there is no need to introduce a ceramic sheet and thermal grease, reducing the thermal resistance of the system composed of the encapsulation structure and the heat dissipation structure, improving the heat dissipation capacity of the system, ensuring the reliability of the encapsulation structure, and further reducing the encapsulation cost, having high industrial utilization value. Description of the Drawings

[0023] Figure 1 Shown is a schematic structural diagram of a discrete device.

[0024] Figure 2 Shown is a top view of the encapsulation structure of the discrete device of the present utility model.

[0025] Figure 3 Shown is a bottom view of the encapsulation structure of the discrete device of the present utility model.

[0026] Figure 4 Shown is a schematic side view of the package structure of the discrete device of the present utility model.

[0027] Figures 5 to 20 Shown are schematic diagrams of the package structures of different discrete devices of the present utility model.

[0028] Explanation of reference numerals in the drawings

[0029] 01 Package body

[0030] 02 Pin

[0031] 03 Thermal grease layer

[0032] 04 Ceramic sheet

[0033] 05 Heat sink

[0034] 06 PCB board

[0035] 07 Screw

[0036] 1 Thermal conductive substrate

[0037] 11 First metal layer

[0038] 12 Insulating and thermally conductive layer

[0039] 13 Second metal layer

[0040] 14 First zone

[0041] 15 Second zone

[0042] 151 Lead zone

[0043] 152 Welding zone

[0044] 16 Groove

[0045] 2 Through hole

[0046] 3 Chip

[0047] 4 Lead

[0048] 5 Pin

[0049] 6 Package layer

[0050] 61 Notch

[0051] 7 Heat dissipation structure

[0052] 71 Fixing part

[0053] 8 Circuit board Detailed implementation manners

[0054] The following describes the embodiments of the present utility model through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present utility model from the content disclosed in this specification. The present utility model can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present utility model.

[0055] Please refer to Figures 2 to 20 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present utility model in a schematic manner. Therefore, only the components related to the present utility model are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0056] This embodiment provides a discrete device packaging structure, as Figure 2 , Figure 3 , Figure 4 and Figures 5 to 20 shown, which are the top view of the discrete device packaging structure, the bottom view of the discrete device packaging structure, the side structure schematic diagram of the discrete device packaging structure, and the structure schematic diagram of different discrete device packaging structures, including a heat-conducting substrate 1, through holes 2, chips 3, leads 4, pins 5, and a packaging layer 6. Among them, the heat-conducting substrate 1 includes a second metal layer 13, an insulating and heat-conducting layer 12, and a first metal layer 11 stacked in sequence. The first metal layer 11 includes a first area 14 and a plurality of second areas 15 spaced from the first area 14 and at least provided with lead areas 151. Adjacent two second areas 15 are spaced a preset distance apart. At least one second area 15 is provided with a welding area 152 communicating with the lead area 151 in this second area 15; at least one through hole 2 penetrates the heat-conducting substrate 1 at a position corresponding to the first area 14; at least one chip 3 is welded to the surface of the welding area 152 facing away from the insulating and heat-conducting layer 12; a plurality of leads 4 are respectively electrically connected to the chip 3 and the respective lead areas 151 corresponding to the chip 3; a plurality of pins 5 are respectively electrically connected to the respective lead areas 151; the packaging layer 6 covers the exposed surfaces of the first metal layer 11, the chip 3, the ends of the pins 5 close to the lead areas 151, the leads 4, and the inner walls of the through holes 2.

[0057] Specifically, the heat-conducting substrate 1 is a substrate for welding the chip 3, the leads 4, and the pins 5. At the same time, the heat-conducting substrate 1 is also used to quickly export the heat generated by the chip 3 in the packaging structure.

[0058] As an example, the heat-conducting substrate 1 includes a DBC substrate, an AMB substrate, or other suitable high heat-conductivity substrates. Here, the DBC substrate is a direct copper clad ceramic substrate, and the AMB substrate is an active metal brazed ceramic substrate.

[0059] Specifically, under the condition of ensuring the performance of the encapsulation structure, the size, thickness and shape of the heat-conducting substrate 1 are selected according to the actual situation; the thickness of the first metal layer 11 can be selected according to the actual situation; the size, thickness and shape of the insulating heat-conducting layer 12 can be selected according to the actual situation; the size, thickness and shape of the second metal layer 13 can be selected according to the actual situation. In this embodiment, the shape of the heat-conducting substrate 1 is a regular quadrilateral.

[0060] Specifically, the material of the first metal layer 11 includes copper, gold, silver or other suitable conductive materials. Preferably, a copper layer with high thermal conductivity and low resistivity is used as the first metal layer 11.

[0061] Specifically, the material of the insulating heat-conducting layer 12 includes alumina, aluminum nitride, silicon nitride or other suitable high thermal conductivity insulating materials.

[0062] Specifically, the material of the second metal layer 13 includes copper, gold, silver, aluminum or other suitable high thermal conductivity materials. Under the condition of ensuring the heat-conducting performance of the heat-conducting substrate 1, the material of the second metal layer 13 can be the same as or different from that of the first metal layer 11. Preferably, a copper layer with high thermal conductivity and low resistance is used as the second metal layer 13.

[0063] Specifically, the first area 14 and the second area 15 are arranged at intervals and insulated from each other. Under the condition of ensuring the performance of the encapsulation structure, the distance between the first area 14 and the second area 15 can be selected according to the actual situation; the shape and size of the first area 14 can be selected according to the actual situation; the shape, size and number of the second areas 15 can be selected according to the actual situation; the distance between two adjacent second areas 15 can be selected according to the actual situation. In this embodiment, the first area 14 and each second area 15 are located in two relatively arranged areas on the first surface.

[0064] Specifically, the second area 15 is an area for welding the chips 3 that need to be individually encapsulated or each chip 3 and the terminals in the power module to be encapsulated. At the same time, the lead area 151 in the second area 15 is used for welding the leads 4 for interconnection between the chips 3 or between the chips 3 and the terminals.

[0065] Specifically, the number, size and distribution of the second areas 15 are related to the interconnection of the chips 3 in the functional circuit of the encapsulation structure; the number, size and position of the lead areas 151 in the second areas 15 are related to the interconnection of the chips 3 in the functional circuit of the encapsulation structure and the application scenario requirements of the encapsulation structure; the number, size and position of the welding areas 151 in the second areas 15 are related to the interconnection of the chips 3 in the functional circuit of the encapsulation structure.

[0066] Specifically, the through-hole 2 is used as a reserved drilling area for fixing the encapsulation structure after the encapsulation layer 7 is formed, so that when it is used on the machine subsequently, it is convenient for screw fixation, and at the same time, when screw fixation is adopted, there will be no problem when screwing the screw to fix the encapsulation structure.

[0067] Specifically, under the condition of ensuring the performance of the encapsulation structure, the size, shape and position of the through-hole 2 in the first region 14 can be selected according to the actual situation. In this embodiment, the through-hole 2 is circular and located in the middle region of the first region 14, and the edge of the through-hole 2 is tangent to the edge of the first region 14 close to the second region 15.

[0068] As an example, the chip 3 includes a MOSFET chip, an IGBT chip, an FRD chip, a JBS chip, an SBD chip or other suitable power device chips. Here, the MOSFET chip is a metal oxide semiconductor field effect transistor chip, the IGBT chip is an insulated gate bipolar transistor chip, the FRD chip is a fast recovery diode chip, the JBS chip is a junction barrier schottky diode chip, and the SBD chip is a schottky barrier diode chip.

[0069] Specifically, the upper surface of the first metal layer 11 is flush, that is, the upper surfaces of the second regions 15 and the upper surface of the first region 14 in the first metal layer 11 are flush. Glue or solder paste can be directly applied at one time, and after applying glue or solder paste, the reflow soldering process is used to synchronously weld each chip 3 and the pin 5 in the functional circuit of the encapsulation structure. When welding multiple chips, there is no need to weld different chips 3 separately, which improves the assembly accuracy and welding efficiency.

[0070] Specifically, the lead 4 is used for the interconnection between the chips 3. It can be based on the functional circuit to electrically connect the electrodes of the chip 3 and the corresponding lead region 151, or electrically connect two corresponding lead regions 151, or electrically connect the electrodes of different chips 3.

[0071] Specifically, the material of the lead 4 includes gold, silver, copper, aluminum or other suitable conductive leads.

[0072] Specifically, the wire diameter and quantity of the lead 4 are related to the requirements of the functional circuit in the encapsulation structure. The length of the lead 4 is related to the distance between the two lead regions 151 to be interconnected, the distance between the electrode of the chip 3 to be interconnected and the lead region 151, and the distance between the electrodes of the two chips 3 to be interconnected, which will not be elaborated here.

[0073] Specifically, there is a preset distance between the bonding area of the lead 4 in the lead region 151 and the welding area of the pin 6 in the lead region 151, so as to facilitate the welding of the lead 4 and the welding of the pin 6.

[0074] Specifically, since the first region 14 and the second region 15 are divided by the first metal layer 11 covering the upper surface of the insulating heat-conducting layer 12, the sizes and shapes of the respective lead regions 151 can be selected according to the requirements of the functional circuit. When a large current is required in the functional circuit, when manufacturing the second region 15, the size of the lead region 151 in the second region 15 can be increased, so that the number of leads 4 bonded in the lead region 151 is increased, thereby improving the current-carrying capacity of the package structure and avoiding the problem that the current-carrying capacity of the package structure cannot be improved due to the fixed size of the bonding region corresponding to the leads in the traditional lead frame.

[0075] As an example, in the same lead region 151, at least one groove 16 is provided between the region where the pin 5 is soldered and the region where the lead 4 is bonded. The depth range of the groove 16 is 20% to 50% of the thickness of the first metal layer 11, as Figures 5 to 19 shown.

[0076] Specifically, since the pin 5 and the lead region 151 are usually soldered by solder, during the soldering process, the solder is likely to overflow. By providing the groove 16 between the region where the pin 5 is soldered and the region where the lead 4 is bonded in the lead region 151, when soldering the pin 5 on the upper surface of the lead region 151 corresponding to the pin 5, the solder can be blocked from overflowing onto the lead 4, eliminating the need to use green solder mask to block the solder from overflowing onto the lead 4, reducing costs and avoiding secondary pollution introduced by the green solder mask. At the same time, since the groove 16 does not penetrate the lead region 151 part in the first metal layer 11, the setting of the groove 16 has no impact on the current-carrying capacity of the package structure.

[0077] Specifically, under the condition of ensuring the performance of the package structure, the opening size, opening shape and number of the groove 16 can be selected according to the actual situation. In this embodiment, one groove 16 is provided between the region where the pin 5 is soldered and the region where the lead 4 is bonded in the lead region 151.

[0078] Specifically, the method of forming the groove 16 in the lead region 151 includes dry etching, wet etching, laser etching or other suitable methods.

[0079] As an example, a welding region 152 is provided in multiple second regions 15, and the lead 4 is also electrically connected to the chip 3 to be electrically connected and the welding region 152.

[0080] Specifically, a welding region 152 is provided in multiple second regions 15. Based on the connection situation of the respective chips 3 in the functional circuit of the package structure, the lead 4 can be electrically connected to the chips 3 soldered in different welding regions 152, or can be electrically connected to the lead region 151 and the chip 3 soldered on the welding region 152 not communicating with this lead region 151, or can be electrically connected to the lead regions 151 communicating with different welding regions 152.

[0081] As an example, in the same second region 15, at least one groove 16 is further provided between the lead region 151 and the welding region 152 to which the lead 4 is bonded.

[0082] Specifically, in the same second region 15, a welding region 152 communicating with the lead region 151 is provided. By providing a groove 16 between the welding region 152 and the lead region 151, when welding the chip 3, the solder can be blocked from overflowing onto the lead 4 bonded in the lead region 151. There is no need to use green oil to block the overflow of solder onto the lead 4, avoiding secondary pollution introduced by the green oil, reducing the cost at the same time, and since the groove 16 does not penetrate the lead region 151 part in the first metal layer 11, the setting of the groove 16 has no influence on the current-carrying capacity of the package structure.

[0083] Specifically, the pins 5 are combined with the leads 4 and the lead region 151, and each electrode of the circuit formed by the chips 3 with specific functions can be led out. Under the condition of ensuring the performance of the package structure, the length, size and shape of each pin 5 can be selected according to the actual situation; the number of pins 5 in the package structure can be selected according to the actual situation. For example, according to the electrode situation led out by the functional circuit in the package structure, the pins 5 of the package structure can be set to 2 pins, 3 pins, 4 pins, 5 pins or more pins.

[0084] Specifically, the pins 5 are fixedly electrically connected to the lead region 151 through a solder layer, and the solder layer is formed by a common welding material through a welding process. For example, the welding material can be a solder sheet, solder paste, etc.

[0085] As an example, the widths of the parts of different pins 5 protruding from the package layer 6 are different, as Figures 7 to 12 and Figures 16 to 19 shown.

[0086] Specifically, under the condition of ensuring the performance of the package structure, the widths of the parts of each pin 5 protruding from the package layer 6 can also be the same.

[0087] Specifically, a plurality of pins 5 are provided in the package structure, and the distances between adjacent two pins 5 can be the same or different.

[0088] Specifically, the welding positions of each pin 5 in the package structure remain unchanged. By changing the width of the part of the pin 5 protruding from the package layer 6 to make the part of the pin 5 protruding from the package layer 6 thinner, the defective rate of welding of the pins 5 in the package structure can be reduced, and the creepage distance of the package structure can be improved.

[0089] Specifically, the material of the pins 5 includes copper, aluminum, nickel, gold, silver, titanium or other suitable conductive materials.

[0090] As an example, the distance between the portion of the pin 5 protruding from the encapsulation layer 6 and the surface of the heat-conducting substrate 1 exposed by the encapsulation layer 6 ranges from 2.4 mm to 3.5 mm.

[0091] Specifically, by controlling the distance between the portion of the pin 5 protruding from the encapsulation layer 6 and the surface of the heat-conducting substrate 1 exposed by the encapsulation layer 6 to be between 2.4 mm and 3.5 mm, when the heat dissipation structure is soldered on the side of the second metal layer 13 away from the insulating heat-conducting layer 12, the creepage distance between the pin 5 and the heat dissipation structure meets the requirements of the high-voltage scenario.

[0092] Specifically, the material of the encapsulation layer 6 includes epoxy resin, polyimide, poly(maleimide triazine) resin, polyphenylene ether, polytetrafluoroethylene, or other suitable dielectric materials. Preferably, an epoxy resin layer is used as the encapsulation layer 6.

[0093] Specifically, the side wall of the encapsulation layer 6 is spaced from the side wall of the heat-conducting substrate 1 by a preset distance to protect the heat-conducting substrate 1, each chip 3 and each lead 4 in the encapsulation structure. When ensuring the performance of the encapsulation structure, the distance between the side wall of the encapsulation layer 6 and the side wall of the heat-conducting substrate 1 can be selected according to the actual situation; the thickness of the encapsulation layer 6 can also be selected according to the actual situation.

[0094] As an example, a plurality of pins 5 are led out from the same side wall of the encapsulation layer 6, and at least one notch 61 is provided in the side wall of the encapsulation layer 6 from which the plurality of pins 5 are led out. The notch 61 is located between two adjacent pins 5 and opens on the surface of the side wall of the encapsulation layer 6 from which the pins 5 are led out, as Figures 10 to 12 and Figures 16 to 18 shown.

[0095] Specifically, the notch 61 penetrates the encapsulation layer 6 in the stacking direction of the chip 3 and the heat-conducting substrate 1, and the bottom surface of the notch 61 is spaced from the side wall of the heat-conducting substrate 1 by a preset distance. When ensuring the performance of the encapsulation structure, the opening size and shape of the notch 61 can be selected according to the actual situation; the distance between the bottom surface of the notch 61 and the side wall of the heat-conducting substrate 1 can also be selected according to the actual situation. Here, the opening size and shape of the notch 61 refer to the opening on the side wall of the encapsulation layer 6, and the bottom surface of the notch 61 refers to the surface parallel to the side wall of the encapsulation layer 6 from which the plurality of pins 5 are led out.

[0096] Specifically, when a plurality of pins 4 are led out from the same side wall of the encapsulation layer 5, by providing the notch 61 in the side wall of the encapsulation layer 6 from which the pins 5 are led out, the creepage distance of the encapsulation structure can be enhanced.

[0097] As an example, a heat dissipation structure 7 fixedly connected to the heat-conducting substrate 1 is further provided on the surface of the heat-conducting substrate 1 exposed by the encapsulation layer 6.

[0098] Specifically, the heat dissipation structure 7 is usually used to accelerate the heat dissipation from the encapsulation structure and improve the heat dissipation capacity of the encapsulation structure. Under the condition of ensuring the performance of the encapsulation structure, the structure, shape and size of the heat dissipation structure 7 can be selected according to the actual situation. Preferably, a fin-type radiator is used as the heat dissipation structure 7.

[0099] Specifically, the heat dissipation structure 7 is fixed on the side of the encapsulation layer 6 where the heat-conducting substrate 1 is exposed through clamping or the fixing portion 71 passing through the through hole 2. And a thermal grease layer or a soldering layer with a relatively high thermal conductivity is provided between the second metal layer 13 exposed on the encapsulation layer 6 and the heat dissipation structure 7 to improve the heat transfer effect between the second metal layer 13 and the heat dissipation structure 7. Preferably, the fixing portion 71 passing through the through hole 2 is used to fix the heat dissipation structure 7. In this embodiment, a screw passing through the through hole 2 is used to fix the heat dissipation structure 7. The screw is tightly attached to the encapsulation layer 6 covering the inner wall of the through hole 2. At the same time, a soldering layer is also provided between the heat dissipation structure 7 and the heat-conducting substrate 1 to improve the heat transfer effect between the heat dissipation structure 7 and the heat-conducting substrate 1.

[0100] Specifically, a soldering layer for improving the heat transfer effect between the heat dissipation structure 7 and the second metal layer 13 is provided between the heat dissipation structure 7 and the second metal layer 13. This soldering layer usually also has the function of fixing the heat dissipation structure 7. The soldering layer is formed by a common soldering material through a soldering process, which will not be elaborated here; under the condition of ensuring the performance of the encapsulation structure, the heat dissipation structure can also be fixed on the side of the encapsulation layer 6 where the heat-conducting substrate 1 is exposed only by the soldering layer.

[0101] As an example, a circuit board 8 electrically connected to the end of the pin 5 far from the encapsulation layer 6 is also provided in the discrete device encapsulation structure, as Figure 20 shown.

[0102] Specifically, the encapsulation structure realizes the electrical connection between the encapsulation structure and the circuit board 8 by being soldered to the circuit board 8. By soldering the encapsulation structure to the circuit board 8, it is convenient to apply the encapsulation structure and other circuits to a complex functional circuit. The size and shape of the circuit board 8 and the circuit distribution in the circuit board 8 can be selected according to the actual situation.

[0103] Specifically, the chip 3 and the pin 5 are respectively soldered on the surfaces of the welding area 152 and the lead area 151 in the first metal layer 11 of the heat-conducting substrate 1, and the distance between the part of the pin 5 protruding from the encapsulation layer 6 and the second metal layer 13 is adjusted according to the working environment requirements of the encapsulation structure, so that when the side of the second metal layer 13 facing away from the insulating heat-conducting layer 12 is soldered to the heat dissipation structure, the creepage distance of the encapsulation structure can also be satisfied.

[0104] Specifically, by providing a through-hole 2 in the first region 14 and covering the inner wall of the through-hole 2 with the encapsulation layer 6, it is convenient to fix the screws of the encapsulation structure during on-machine use, and then it is convenient to install the encapsulation structure on the machine.

[0105] Specifically, since the upper surfaces of the welding region 152 and the lead region 151 in the second region 15 are flush, it is convenient to simultaneously form the solder of the welding pins 5 and the chip 3, and at the same time, it is convenient to simultaneously weld the pins 5 and the chip 3, improving the welding accuracy and welding efficiency.

[0106] Specifically, by providing a groove 16 that does not penetrate the second region 15 between the region where the lead 4 is bonded in the lead region 151 and the welding region 152 and between the region where the lead 4 is bonded and the region where the pin 5 is welded, the solder overflowing during the welding of the welding pin 5 and the chip 3 can be blocked from overflowing onto the lead 4, eliminating the need to provide a green oil to block the solder overflow, avoiding secondary pollution caused by the introduction of the green oil, reducing the encapsulation cost, and ensuring the electrical performance and reliability of the encapsulation structure.

[0107] Specifically, the heat dissipation structure 7 is directly welded to the side of the second metal layer 13 facing away from the insulating and heat-conducting layer 12 through a highly heat-conductive solder, and then through the combination of the first metal layer 11, the insulating and heat-conducting layer 12, and the second metal layer 13 in the heat-conducting substrate 1, there is no need to add a ceramic sheet for internal insulation and a thermal grease for enhancing the heat transfer ability between the ceramic sheet and the heat dissipation structure, further reducing the encapsulation cost, and at the same time significantly reducing the thermal resistance of the system composed of the encapsulation structure and the heat dissipation structure 7, improving the heat dissipation ability of the system.

[0108] In summary, the discrete device packaging structure of the present utility model improves the structure of the packaging structure. A heat-conducting substrate including a first metal layer, an insulating heat-conducting layer, and a second metal layer is used as the substrate for soldering the chip. The first metal layer includes a first region and a second region. Through holes are provided in the first region to facilitate the installation of the packaging structure on the machine through the through-hole region. The upper surface of the second region is flush, facilitating the synchronous soldering of the pins and the chip, improving the soldering efficiency and soldering accuracy. The lead region in the second region can be divided into regions with larger sizes according to the requirements of the functional circuit, facilitating an increase in the number of bonding leads and enhancing the current-carrying capacity of the packaging structure. By providing grooves between the region where the leads are bonded in the lead region and the soldering region, and between the region where the leads are bonded and the region where the pins are soldered, the solder overflowing during the soldering of the pins and the chip is blocked from reaching the leads, eliminating the need to use green solder resist to block the solder from reaching the leads, avoiding secondary pollution caused by the green solder resist, and reducing the packaging cost. In addition, by using a heat-conducting substrate as the substrate for soldering the chip, when soldering the heat dissipation device, there is no need to introduce a ceramic sheet and thermal grease, reducing the thermal resistance of the system composed of the packaging structure and the heat dissipation structure, improving the heat dissipation capacity of the system, ensuring the reliability of the packaging structure, and further reducing the packaging cost. Therefore, the present utility model effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0109] The above embodiments are merely illustrative of the principles and effects of the present utility model, and are not intended to limit the present utility model. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present utility model. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present utility model should still be covered by the claims of the present utility model.

Claims

1. A discrete device packaging structure, characterized in that, Comprising: A heat-conducting substrate, including a second metal layer, an insulating and heat-conducting layer, and a first metal layer laminated in sequence. The first metal layer includes a first region and a plurality of second regions spaced from the first region and having at least a lead region. Adjacent two of the second regions are spaced a preset distance apart. At least one of the second regions is provided with a welding region communicating with the lead region in the second region; At least one through hole, penetrating the heat-conducting substrate at a corresponding position of the first region; At least one chip, welded to a surface of the welding region facing away from the insulating and heat-conducting layer; A plurality of leads, respectively electrically connecting the chip and each of the corresponding lead regions; A plurality of pins, respectively electrically connected to the corresponding lead regions; A packaging layer, covering the first metal layer, the chip, one end of the pin close to the lead region, the exposed surfaces of the leads, and the inner wall of the through hole.

2. The discrete device package structure according to claim 1, wherein: The chip includes a MOSFET chip, an IGBT chip, an FRD chip, a JBS chip, an SBD chip; the heat-conducting substrate includes a DBC substrate, an AMB substrate.

3. The discrete device package structure according to claim 1, wherein: In the same lead region, there is at least one groove between the region where the pin is welded and the region where the lead is bonded. The depth range of the groove is 20% - 50% of the thickness of the first metal layer in the lead region.

4. The discrete device package structure according to claim 1, wherein: The welding region is provided in a plurality of the second regions, and the lead also electrically connects the chip to be electrically connected and the welding region.

5. The discrete device package structure according to claim 4, wherein: In the same second region, there is also at least one groove between the lead region where the lead is bonded and the welding region.

6. The discrete device package structure according to claim 1, wherein: The widths of the portions of different pins protruding from the packaging layer are different.

7. The discrete device package structure according to claim 1, wherein: A plurality of the pins are led out from the same side wall of the packaging layer, and at least one notch is provided in the side wall of the packaging layer from which the pins are led out. The notch is located between adjacent two of the pins and opens on the surface of the side wall of the packaging layer from which the pins are led out.

8. The discrete device package structure according to claim 1, wherein: The distance between the portion of the pin protruding from the packaging layer and the surface of the heat-conducting substrate exposed by the packaging layer ranges from 2.4 mm to 3.5 mm.

9. The discrete device package structure according to claim 1, wherein: The surface of the heat-conducting substrate exposed by the packaging layer is also provided with a heat dissipation structure fixedly connected to the heat-conducting substrate.

10. The discrete device package structure according to claim 1, wherein: A circuit board electrically connected to the end of the pin away from the packaging layer is also provided in the discrete device packaging structure.

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