Power-on and power-off automatic reset circuit
Through the automatic power-down reset circuit built by discrete devices, the identification timing problem of USB products when switching between Host and Device is solved, low-cost circuit design is realized, and market competitiveness is enhanced.
Patent Information
- Application Number
- CN202422309901.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2034-09-20
AI Technical Summary
When switching between Host and Device, existing USB products require a high-cost reset chip or microcontroller to achieve recognition timing control, resulting in a high overall cost.
The up-down automatic reset circuit built with discrete devices, including comparator and MOS tube, is designed through voltage divider circuit and capacitor, and voltage adjustment and signal control are realized to ensure normal identification timing after switching.
It realizes that the recognition timing of USB products after switching between Host and Device is normal, the circuit is simple and the cost is low, and the market competitiveness is enhanced.
Smart Images
Figure CN223093760U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of hardware circuits, in particular to an up-and-down power automatic reset circuit. Background Art
[0002] At present, for some USB products, such as POS bases and USB docking stations, there is indeed an urgent need for the USB products to be able to flexibly switch between Host (host) and Device (device) through power-on and power-off.
[0003] Generally speaking, in order to ensure the normal recognition timing after the Host and Device are switched, the common practice in the industry is to use a reset chip with a high degree of integration or a powerful single-chip microcomputer to trigger the control logic circuit.
[0004] However, although this technical solution shows high reliability and flexibility in function implementation, it inevitably involves certain cost considerations. Specifically, using a reset chip or a single-chip microcomputer as the control core often results in a relatively high overall cost due to factors such as the high technical content of the components themselves and the complex production process. This is undoubtedly a factor that manufacturers who pursue cost control and cost performance need to carefully weigh.
[0005] Therefore, when designing and developing such products, it is necessary to comprehensively consider various factors such as functional requirements, cost-effectiveness, and technical feasibility, and explore more economical and efficient solutions, so as to effectively control costs and enhance market competitiveness while meeting the functional requirements of the products.
[0006] The above information is given as background information only to assist in understanding the present disclosure, and does not determine or admit whether any of the above content can be used as the prior art relative to the present disclosure. Summary of the Utility Model
[0007] The utility model provides an up-and-down power automatic reset circuit to solve the problem of high cost in the prior art.
[0008] To achieve the above object, the utility model provides the following technical solutions:
[0009] An up-and-down power automatic reset circuit includes a power-down automatic reset circuit and a power-up automatic reset circuit; wherein,
[0010] The power-down automatic reset circuit includes a comparator U1 and a first MOS transistor D3;
[0011] The IN+ pin of the comparator U1 is connected to the TYPE-B interface, and the OUT pin of the comparator U1 is connected to the gate of the first MOS transistor D3; the source of the first MOS transistor D3 is grounded, and the drain of the first MOS transistor D3 serves as the output terminal of the reset enable signal;
[0012] When powering down, the TYPE-B interface changes from a high level to 0V, and the comparator U1 will output a high level to the gate of the first MOS transistor D3, and the drain of the first MOS transistor D3 is pulled to a low level, thereby triggering an automatic reset;
[0013] The power-on automatic reset circuit includes an eighth capacitor C8 and a second MOS transistor D4;
[0014] The eighth capacitor C8 is connected between the TYPE-B interface and the gate of the second MOS transistor D4; the source of the second MOS transistor D4 is grounded, and the drain of the second MOS transistor D4 is connected to the output terminal;
[0015] When powering on, the TYPE-B interface changes from 0V to a high level. Due to the voltage across the eighth capacitor C8 not being able to change suddenly, the gate of the second MOS transistor D4 is at a high level, and the drain of the second MOS transistor D4 is pulled to a low level, thereby triggering an automatic reset.
[0016] Further, in the power-on and power-off automatic reset circuit, the power-off automatic reset circuit further includes a first voltage dividing circuit;
[0017] The IN+ pin of the comparator U1 is connected to the TYPE-B interface through the first voltage dividing circuit.
[0018] Further, in the power-on and power-off automatic reset circuit, the first voltage dividing circuit includes a first resistor R1 and a fourth resistor R4;
[0019] The IN+ pin of the comparator U1 is connected to the TYPE-B interface through the fourth resistor R4;
[0020] One end of the first resistor R1 is connected to the IN+ pin of the comparator U1, and the other end of the first resistor R1 is grounded.
[0021] Further, in the power-on and power-off automatic reset circuit, the power-off automatic reset circuit further includes a third capacitor C3;
[0022] One end of the third capacitor C3 is connected to the IN+ pin of the comparator U1, and the other end of the third capacitor C3 is grounded.
[0023] Further, in the power-on and power-off automatic reset circuit, the power-off automatic reset circuit further includes a second resistor R2, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a fourth capacitor C4, a fifth capacitor C5, a seventh capacitor C7, a first diode D1, and a second diode D2;
[0024] The OUT pin of the comparator U1 is connected to the gate of the first MOS transistor D3 through the sixth resistor R6;
[0025] One end of the seventh capacitor C7 is connected to the OUT pin of the comparator U1, and the other end of the seventh capacitor C7 is grounded;
[0026] One end of the fifth capacitor C5 is connected to the gate of the first MOS transistor D3, and the other end of the fifth capacitor C5 is grounded;
[0027] The +Vs pin of the comparator U1 is connected to the power supply HUB0_VDD;
[0028] One end of the first capacitor C1 and the second capacitor C2 are connected in parallel and then grounded, and the other end is connected to the +Vs pin of the comparator U1;
[0029] One end of the fourth capacitor C4 and the second resistor R2 are connected in parallel and then grounded, and the other end is connected to the IN- pin of the comparator U1;
[0030] The positive electrode of the first diode D1 is connected to the TYPE-B interface, and the negative electrode of the first diode D1 is connected to the IN- pin of the comparator U1;
[0031] The positive electrode of the second diode D2 is connected to the initial level VCC_1V8, and the negative electrode of the second diode D2 is connected to the IN- pin of the comparator U1.
[0032] Further, in the power-on and power-off automatic reset circuit, the power-on automatic reset circuit further includes a second voltage dividing circuit;
[0033] The second voltage dividing circuit is connected between the eighth capacitor C8 and the TYPE-B interface.
[0034] Further, in the power-on and power-off automatic reset circuit, the second voltage dividing circuit includes a fifth resistor R5 and an eighth resistor R8;
[0035] The fifth resistor R5 is connected between the eighth capacitor C8 and the TYPE-B interface;
[0036] One end of the eighth resistor R8 is connected to the eighth capacitor C8, and the other end of the eighth resistor R8 is grounded.
[0037] Further, in the power-on and power-off automatic reset circuit, the power-on automatic reset circuit further includes a fifth diode D5;
[0038] The anode of the fifth diode D5 is grounded, and the cathode of the fifth diode D5 is connected between the eighth capacitor C8 and the gate of the second MOS transistor D4.
[0039] Further, in the power-on and power-off automatic reset circuit, the power-on automatic reset circuit further includes a seventh resistor R7 and a second capacitor C6;
[0040] One end of the seventh resistor R7 and the second capacitor C6 in parallel is grounded, and the other end is connected between the eighth capacitor C8 and the gate of the second MOS transistor D4.
[0041] Further, in the power-on and power-off automatic reset circuit, the power-on automatic reset circuit further includes a third resistor R3 and a ninth capacitor C9;
[0042] The third resistor R3 is connected in series to the output terminal;
[0043] One end of the ninth capacitor C9 is grounded, and the other end is connected to the output terminal.
[0044] Compared with the prior art, the present utility model has the following beneficial effects:
[0045] A power-on and power-off automatic reset circuit provided by the present utility model is built with discrete components, which can not only ensure the normal recognition timing of the USB product after the Host and Device switching, but also has a simple circuit and low cost, which is conducive to cost control and improves market competitiveness.
[0046] The present utility model has other characteristics and advantages, which will be obvious from the accompanying drawings incorporated herein and the subsequent specific embodiments, or will be described in detail in the accompanying drawings incorporated herein and the subsequent specific embodiments, and these drawings and specific embodiments are used together to explain the specific principles of the present utility model. Description of the Drawings
[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0048] Figure 1 It is a simple circuit diagram of a power-on and power-off automatic reset circuit provided by an embodiment of the present utility model;
[0049] Figure 2 It is a partial circuit principle schematic diagram of a power-on and power-off automatic reset circuit provided by an embodiment of the present utility model;
[0050] Figure 3 It is another partial circuit principle schematic diagram of a power-on and power-off automatic reset circuit provided by an embodiment of the present utility model. Specific implementation manners
[0051] To describe in detail the possible application scenarios, technical principles, specific implementable solutions, achievable purposes and effects of the present application, the following will be described in detail with reference to the listed specific embodiments and in conjunction with the accompanying drawings. The embodiments described herein are only used to more clearly illustrate the technical solutions of the present application, so they are only used as examples and cannot be used to limit the protection scope of the present application.
[0052] Referring to "embodiments" in this article means that specific features, structures or characteristics described in connection with the embodiments may be included in at least one embodiment of the present application. The term "embodiment" appearing in various positions in the specification does not necessarily refer to the same embodiment, nor does it particularly limit its independence or relevance to other embodiments. In principle, in the present application, as long as there is no technical contradiction or conflict, the technical features mentioned in each embodiment can be combined in any way to form corresponding implementable technical solutions.
[0053] Unless otherwise defined, the meanings of the technical terms used in this article are the same as those commonly understood by those skilled in the technical field to which the present application belongs; the use of the relevant terms in this article is only for describing specific embodiments and is not intended to limit the present application.
[0054] In the description of the present application, the term "and / or" is an expression used to describe the logical relationship between objects, indicating that there can be three relationships, for example, A and / or B, which means: there is A, there is B, and there is both A and B at the same time. In addition, the character " / " in this article generally represents an "or" logical relationship between the associated objects before and after.
[0055] In the present application, terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual quantity, primary or secondary, or order relationship between these entities or operations.
[0056] Without further limitations, in this application, the terms "comprising", "including", "having" or other similar expressions used in a statement are intended to cover non-exclusive inclusion. These expressions do not exclude the possibility that there may be additional elements in a process, method or product that includes the said elements. Thus, in a process, method or product that includes a series of elements, it can include not only those defined elements, but also other elements not explicitly listed, or elements inherent to such a process, method or product.
[0057] In this application, expressions such as "greater than", "less than", "exceeding" are understood not to include the base number; expressions such as "above", "below", "within" are understood to include the base number. In addition, in the description of the embodiments of this application, the meaning of "multiple" is two or more (including two). Similar expressions related to "many", such as "multiple groups", "multiple times", etc., are understood in this way, unless otherwise specifically defined.
[0058] In the description of the embodiments of this application, the spatially related expressions used, such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "perpendicular", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the specific embodiment or the drawing. It is only for the convenience of describing the specific embodiments of this application or facilitating the reader's understanding, rather than indicating or implying that the device or component referred to must have a specific position, a specific orientation, or be constructed or operated in a specific orientation. Therefore, it should not be construed as a limitation to the embodiments of this application.
[0059] Unless otherwise clearly specified or limited, in the description of the embodiments of this application, the terms "installed", "connected", "joined", "fixed", "set", etc. should be understood in a broad sense. For example, the said "connection" can be a fixed connection, a detachable connection, or an integral setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be directly connected, or indirectly connected through an intermediate medium; it can be the communication inside two elements or the interaction relationship between two elements. For those skilled in the technical field to which this application belongs, the specific meanings of the above terms in the embodiments of this application can be understood according to specific circumstances.
[0060] Please refer to Figures 1 - 3 , the embodiment of the present utility model provides an up and down power automatic reset circuit, including a power-down automatic reset circuit and a power-up automatic reset circuit; wherein,
[0061] The power-down automatic reset circuit includes a comparator U1 and a first MOS transistor D3;
[0062] The IN+ pin of the comparator U1 is connected to the TYPE-B interface, and the OUT pin of the comparator U1 is connected to the gate of the first MOS transistor D3; the source of the first MOS transistor D3 is grounded, and the drain of the first MOS transistor D3 serves as the output terminal of the reset enable signal;
[0063] The power-on automatic reset circuit includes an eighth capacitor C8 and a second MOS transistor D4;
[0064] The eighth capacitor C8 is connected between the TYPE-B interface and the gate of the second MOS transistor D4; the source of the second MOS transistor D4 is grounded, and the drain of the second MOS transistor D4 is connected to the output terminal;
[0065] It should be noted that the specific circuit principle of the power-off automatic reset function that the power-off automatic reset circuit can achieve is as follows:
[0066] Condition status: The power supply HUB0_VDD and the initial level VCC_1V8 of the comparator U1 are powered normally;
[0067] When powering off, the power supply provided by the TYPE-B interface (shown as TYPE_B_5V in the figure) changes from a high level (such as 5V) to 0V, and the comparator U1 will output a high level to the gate of the first MOS transistor D3, and the drain of the first MOS transistor D3 is pulled to a low level, thereby triggering an automatic reset;
[0068] When TYPE_B_5V is in a constant state of 5V or 0V, a low level is given to the gate of the first MOS transistor D3 through the comparator U1, and no automatic reset will be triggered at this time; when TYPE_B_5V changes from 0V to a high level, the gate of the first MOS transistor D3 is a low level, and no automatic reset will be triggered at this time.
[0069] The specific circuit principle of the power-on automatic reset function that the power-on automatic reset circuit can achieve is as follows:
[0070] When powering on, the TYPE-B interface changes from 0V to a high level. Since the voltage across the eighth capacitor C8 cannot change suddenly, the gate of the second MOS transistor D4 is at a high level, and the drain of the second MOS transistor D4 is pulled to a low level, thereby triggering an automatic reset.
[0071] When TYPE_B_5V is in a constant state of 5V or 0V, a low level is given to the gate of the second MOS transistor D4 through the eighth capacitor C8, and no automatic reset will be triggered at this time; when TYPE_B_5V changes from a high level to 0V, the gate of the second MOS transistor D4 is a low level, and no automatic reset will be triggered at this time.
[0072] It is understandable that since the power-on and power-off automatic reset circuit designed in this embodiment uses carefully selected discrete components for construction, this not only ensures that the USB product can accurately follow the established recognition timing logic to operate after the Host and Device are switched, guaranteeing the stability and compatibility of the system, but also reflects the ingenuity and efficiency in design. At the same time, this circuit solution strives for simplicity in structure, avoiding unnecessary complexity, thus achieving a significant reduction in manufacturing costs. This optimized cost control strategy not only helps enterprises reduce the overall cost of product production and improve economic efficiency, but also enables them to win wider market recognition and favor with a more consumer-friendly price strategy and excellent performance in the fierce market competition, further consolidating and enhancing the market competitiveness of the brand.
[0073] Please refer to again Figure 2 , in one implementation manner of this embodiment, a first voltage division circuit is particularly introduced as a key component, and the ingenious design of this circuit plays a crucial role in the overall performance and stability of the circuit.
[0074] Specifically, the power-off automatic reset circuit innovatively integrates the first voltage division circuit, and this design enables the IN+ pin of the comparator U1 to be connected to the TYPE-B interface through a carefully configured voltage distribution path. The uniqueness of this connection method lies in that it does not directly transmit the high-level signal of the TYPE-B interface to the comparator U1, but appropriately adjusts the voltage through the first voltage division circuit to ensure signal compatibility and security.
[0075] It is particularly noteworthy that when TYPE_B_5V is in the in-position state, that is, when there is a stable 5V voltage supply in the interface, the first voltage division circuit will accurately divide this voltage to an appropriate level between 5V and 1.8V and deliver it to the IN+ pin of the comparator U1. This voltage division process not only protects the comparator from the impact of excessive voltage, but also ensures that the comparator can accurately perform signal comparison and judgment within this range, thereby triggering the corresponding reset operation.
[0076] Furthermore, regarding the specific implementation of the first voltage division circuit, a feasible alternative is provided. This solution adopts the combination form of the first resistor R1 and the fourth resistor R4, and realizes the voltage adjustment through the series voltage division effect of these two resistors. Specifically, the IN+ pin of the comparator U1 is first connected to the TYPE-B interface through the fourth resistor R4 to form a preliminary voltage input path; subsequently, one end of the first resistor R1 is connected to a certain point on this path (i.e., the IN+ pin of the comparator U1), and the other end is grounded to form a current loop. By adjusting the resistance ratio of these two resistors, the voltage value after voltage division can be accurately controlled to meet the requirements of the circuit design.
[0077] In summary, the power-down automatic reset circuit in this embodiment realizes the precise adjustment and control of the voltage of the TYPE-B interface by introducing the first voltage division circuit and skillfully using the principle of resistor voltage division. It not only improves the compatibility and stability of the circuit, but also provides a reliable signal basis for subsequent comparison and reset operations.
[0078] Please refer to again Figure 2 , in one implementation manner of this embodiment, the power-down automatic reset circuit further includes a third capacitor C3;
[0079] One end of the third capacitor C3 is connected to the IN+ pin of the comparator U1, and the other end of the third capacitor C3 is grounded.
[0080] It should be noted that the third capacitor C3 plays multiple roles in this circuit. First of all, as a smoothing element, it effectively smooths the level change on the IN+ pin of the comparator U1. During the operation of the circuit, due to the influence of various factors, the level on the IN+ pin may fluctuate or mutate, which may interfere with the normal operation of the comparator. The existence of the third capacitor C3 is like a "buffer pad", which can absorb and slow down these fluctuations, make the level change on the IN+ pin more stable, and thus ensure that the comparator can accurately perform signal comparison and judgment.
[0081] Secondly, the third capacitor C3 also has the functions of energy storage and slowing down the power-on and power-off processes. During the power-on process of the circuit, the capacitor starts to charge, and this process will absorb a part of the current, thus slowing down the instantaneous current impact in the circuit and protecting other components in the circuit from damage. Similarly, when the circuit needs to discharge, the capacitor will gradually release the electrical energy it stores, and this process also helps to slow down the discharge speed and avoid excessive impact on the circuit.
[0082] Please refer to again Figure 2, in one implementation of this embodiment, the power-down automatic reset circuit further includes a second resistor R2, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a fourth capacitor C4, a fifth capacitor C5, a seventh capacitor C7, a first diode D1, and a second diode D2;
[0083] The OUT pin of the comparator U1 is connected to the gate of the first MOS transistor D3 through the sixth resistor R6; this design enables the output signal of the comparator to directly control the switching state of the MOS transistor, thereby realizing effective control of the circuit reset operation.
[0084] One end of the seventh capacitor C7 is connected to the OUT pin of the comparator U1, and the other end of the seventh capacitor C7 is grounded; the function of the seventh capacitor C7 is to further smooth the level change on the OUT pin and reduce misoperations that may be caused by signal fluctuations.
[0085] One end of the fifth capacitor C5 is connected to the gate of the first MOS transistor D3, and the other end of the fifth capacitor C5 is grounded; the fifth capacitor C5 provides necessary decoupling and filtering functions for the gate, which helps to improve the switching performance of the MOS transistor.
[0086] The +Vs pin of the comparator U1 is connected to the power supply HUB0_VDD;
[0087] After the first capacitor C1 and the second capacitor C2 are connected in parallel, one end is grounded and the other end is connected to the +Vs pin of the comparator U1; these two capacitors together constitute a decoupling network for the power supply, effectively filtering out high-frequency noise and interference in the power supply and providing a stable working voltage for the comparator.
[0088] After the fourth capacitor C4 and the second resistor R2 are connected in parallel, one end is grounded and the other end is connected to the IN- pin of the comparator U1; this combination not only provides necessary filtering function for the IN- pin, but also limits the maximum input voltage of the IN- pin through resistor voltage division, protecting the input end of the comparator from damage.
[0089] The positive electrode of the first diode D1 is connected to the TYPE-B interface, and the negative electrode of the first diode D1 is connected to the IN- pin of the comparator U1; the function of the first diode D1 is to limit the voltage within the forward conduction voltage of the diode when there is voltage at the TYPE-B interface, preventing excessive voltage from damaging the comparator.
[0090] The positive electrode of the second diode D2 is connected to the initial level VCC_1V8, and the negative electrode of the second diode D2 is connected to the IN- pin of the comparator U1. The second diode D2 provides a stable reference voltage VCC_1V8 to the IN- pin. When there is no voltage at the TYPE-B interface, the IN- pin will remain at this reference voltage level.
[0091] Please refer to again Figure 3 , in an implementation manner of this embodiment, the power-on automatic reset circuit further includes a second voltage dividing circuit;
[0092] The second voltage dividing circuit is connected between the eighth capacitor C8 and the TYPE-B interface.
[0093] It should be noted that the introduction of this voltage dividing circuit aims to solve the problem of excessive voltage of the second MOS transistor D4 that may occur during the power-on process, thereby protecting the MOS transistor from damage and ensuring the stable operation of the circuit.
[0094] Specifically, the second voltage dividing circuit is ingeniously designed and connected between the eighth capacitor C8 and the TYPE-B interface. This layout enables, when the TYPE-B interface is connected to the power supply, through the action of the second voltage dividing circuit, the input voltage to be divided and then transmitted to the eighth capacitor C8 and subsequent circuits. This voltage dividing mechanism effectively limits the voltage value transmitted to the second MOS transistor D4, preventing it from being damaged due to excessive voltage.
[0095] Furthermore, regarding the specific implementation manner of the second voltage dividing circuit, a feasible alternative solution is provided. This solution adopts a combination form of the fifth resistor R5 and the eighth resistor R8. Among them, the fifth resistor R5 is directly connected between the eighth capacitor C8 and the TYPE-B interface and serves as the main voltage dividing element of the voltage dividing circuit; while the eighth resistor R8 has one end connected to the eighth capacitor C8 and the other end grounded, forming the current loop of the voltage dividing circuit. By adjusting the resistance ratio of these two resistors, the voltage value after voltage division can be precisely controlled to meet the requirements of the circuit design.
[0096] Please refer to again Figure 3 , in an implementation manner of this embodiment, the power-on automatic reset circuit further includes a fifth diode D5;
[0097] The positive electrode of the fifth diode D5 is grounded, and the negative electrode of the fifth diode D5 is connected between the eighth capacitor C8 and the gate of the second MOS transistor D4.
[0098] Specifically, the fifth diode D5 plays two key roles in this circuit. First, as a fast charge path, it can quickly supply the required charge to the eighth capacitor C8 when the voltage changes suddenly (especially at the moment of power-on). This function is crucial for ensuring that the eighth capacitor C8 can quickly reach a stable operating state, thus helping to improve the response speed and stability of the entire circuit.
[0099] Second, the fifth diode D5 also serves to prevent the charge from flowing back along the original path. During the operation of the circuit, if the charge on the eighth capacitor C8 could easily flow back to the power supply or other components along the original path, it would not only cause energy waste but also have an adverse impact on the circuit stability. The presence of the fifth diode D5 acts like a "one-way valve", allowing the charge to flow only from the negative electrode to the positive electrode (i.e., to ground), thus effectively preventing the charge from flowing back along the original path.
[0100] Please refer to again Figure 3 , in one implementation of this embodiment, the power-on automatic reset circuit further includes a seventh resistor R7 and a second capacitor C6;
[0101] One end of the parallel connection of the seventh resistor R7 and the second capacitor C6 is grounded, and the other end is connected between the eighth capacitor C8 and the gate of the second MOS transistor D4.
[0102] Specifically, the main function of the seventh resistor R7 is to discharge the gate of the second MOS transistor D4. When the circuit needs to be powered off or reset, through the discharging effect of the seventh resistor R7, the voltage on the gate can be gradually reduced, thus safely and controllably turning off the MOS transistor. It should be noted that the resistance value of the seventh resistor R7 is specifically selected as 3 MΩ to slow down the discharging process and avoid sudden large currents from impacting the circuit. By slowing down the discharging speed, a smooth transition during the power-off or reset process of the circuit can be ensured, protecting other components in the circuit from damage.
[0103] The second capacitor C6, on the other hand, plays a role in smoothing the level change of the gate of the second MOS transistor D4. During the operation of the circuit, due to various factors, the level on the gate may fluctuate or change suddenly. The presence of the second capacitor C6 acts like a "buffer pad", which can absorb and slow down these fluctuations, making the level change on the gate more stable. This not only helps to protect the MOS transistor from the impact of instantaneous high or low voltages but also improves the anti-interference ability of the circuit. At the same time, the second capacitor C6 also has a certain energy storage function and can release energy when the circuit needs it, slowing down the discharging process and further improving the stability and reliability of the circuit.
[0104] Please refer to again Figure 3, in one implementation of this embodiment, the power-on automatic reset circuit further includes a third resistor R3 and a ninth capacitor C9; the introduction of these two components further enhances the functionality and stability of the circuit.
[0105] The third resistor R3 is connected in series to the output terminal;
[0106] One end of the ninth capacitor C9 is grounded, and the other end is connected to the output terminal.
[0107] It should be noted that the design of the third resistor R3 is used to limit the magnitude of the output current, preventing damage to subsequent circuits or loads due to excessive current during circuit startup or operation. At the same time, the resistor also has a certain voltage-dividing effect, which can adjust the amplitude of the output voltage to meet the requirements of specific application scenarios.
[0108] The ninth capacitor C9 mainly functions to debounce. In digital circuits, especially when it comes to mechanical contact input components such as buttons and switches, due to the instability of mechanical contacts, multiple rapid on-off signals are often generated at the moment of contact, and this phenomenon is called "jitter". If the jitter signal is directly transmitted to subsequent circuits, it may cause the circuit to make misjudgments or incorrect operations. The introduction of the ninth capacitor C9 is precisely to eliminate this jitter phenomenon. When the output terminal changes rapidly, the capacitor will absorb and store a part of the charge, thereby slowing down the signal change speed, enabling subsequent circuits to have sufficient time to stably identify and process the signal, and avoiding incorrect operations caused by jitter.
[0109] Although terms such as power-down automatic reset circuit, power-on automatic reset circuit comparator, etc. are used more frequently in this application, the possibility of using other terms is not excluded. The use of these terms is only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional limitation is contrary to the spirit of the present invention.
[0110] A power-on and power-off automatic reset circuit provided by the present invention is built with discrete components. It can not only ensure the normal recognition timing of USB products after switching between Host and Device, but also has a simple circuit and low cost, which is conducive to cost control and enhances market competitiveness.
[0111] Finally, it should be noted that although the above embodiments have been described in the text and drawings of the specification of this application, it does not limit the patent protection scope of this application. Any technical solutions obtained by equivalent structure or equivalent process substitution or modification based on the essential concept of this application, using the content recorded in the text and drawings of the specification of this application, and any technical solutions directly or indirectly implementing the above embodiments in other related technical fields, etc., are all included in the patent protection scope of this application.
Claims
1. An up / down power automatic reset circuit, characterized in that, It includes a power-down automatic reset circuit and a power-up automatic reset circuit; among them, the power-down automatic reset circuit includes a comparator U1 and a first MOS transistor D3; the IN+ pin of the comparator U1 is connected to the TYPE-B interface, and the OUT pin of the comparator U1 is connected to the gate of the first MOS transistor D3; the source of the first MOS transistor D3 is grounded, and the drain of the first MOS transistor D3 serves as the output terminal of the reset enable signal; when powering down, the TYPE-B interface changes from high level to 0V, the comparator U1 will output a high level to the gate of the first MOS transistor D3, and the drain of the first MOS transistor D3 is pulled to a low level, thereby triggering an automatic reset; the power-up automatic reset circuit includes an eighth capacitor C8 and a second MOS transistor D4; the eighth capacitor C8 is connected between the TYPE-B interface and the gate of the second MOS transistor D4; the source of the second MOS transistor D4 is grounded, and the drain of the second MOS transistor D4 is connected to the output terminal; when powering up, the TYPE-B interface changes from 0V to high level. Since the voltage across the eighth capacitor C8 cannot change suddenly, the gate of the second MOS transistor D4 is at a high level, and the drain of the second MOS transistor D4 is pulled to a low level, thereby triggering an automatic reset.
2. The power-on and power-off automatic reset circuit according to claim 1, wherein The power-down automatic reset circuit further includes a first voltage dividing circuit; the IN+ pin of the comparator U1 is connected to the TYPE-B interface through the first voltage dividing circuit.
3. The power-on and power-off automatic reset circuit according to claim 2, wherein The first voltage dividing circuit includes a first resistor R1 and a fourth resistor R4; the IN+ pin of the comparator U1 is connected to the TYPE-B interface through the fourth resistor R4; one end of the first resistor R1 is connected to the IN+ pin of the comparator U1, and the other end of the first resistor R1 is grounded.
4. The power-on and power-off automatic reset circuit according to claim 1, characterized in that, The power-down automatic reset circuit further includes a third capacitor C3; one end of the third capacitor C3 is connected to the IN+ pin of the comparator U1, and the other end of the third capacitor C3 is grounded.
5. The power-on and power-off automatic reset circuit according to claim 1, characterized in that The power-down automatic reset circuit further includes a second resistor R2, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a fourth capacitor C4, a fifth capacitor C5, a seventh capacitor C7, a first diode D1, and a second diode D2; the OUT pin of the comparator U1 is connected to the gate of the first MOS transistor D3 through the sixth resistor R6; one end of the seventh capacitor C7 is connected to the OUT pin of the comparator U1, and the other end of the seventh capacitor C7 is grounded; one end of the fifth capacitor C5 is connected to the gate of the first MOS transistor D3, and the other end of the fifth capacitor C5 is grounded; the +Vs pin of the comparator U1 is connected to the power supply HUB0_VDD; the first capacitor C1 and the second capacitor C2 are connected in parallel, one end is grounded, and the other end is connected to the +Vs pin of the comparator U1; the fourth capacitor C4 and the second resistor R2 are connected in parallel, one end is grounded, and the other end is connected to the IN- pin of the comparator U1; The positive electrode of the first diode D1 is connected to the TYPE-B interface, and the negative electrode of the first diode D1 is connected to the IN- pin of the comparator U1; The positive electrode of the second diode D2 is connected to the initial level VCC_1V8, and the negative electrode of the second diode D2 is connected to the IN- pin of the comparator U1.
6. The power-on and power-off automatic reset circuit according to claim 1, wherein The power-on automatic reset circuit further includes a second voltage dividing circuit; The second voltage dividing circuit is connected between the eighth capacitor C8 and the TYPE-B interface.
7. The power-on and power-off automatic reset circuit according to claim 6, wherein The second voltage dividing circuit includes a fifth resistor R5 and an eighth resistor R8; The fifth resistor R5 is connected between the eighth capacitor C8 and the TYPE-B interface; One end of the eighth resistor R8 is connected to the eighth capacitor C8, and the other end of the eighth resistor R8 is grounded.
8. The power-on and power-off automatic reset circuit according to claim 1, wherein, The power-on automatic reset circuit further includes a fifth diode D5; The positive electrode of the fifth diode D5 is grounded, and the negative electrode of the fifth diode D5 is connected between the eighth capacitor C8 and the gate of the second MOS transistor D4.
9. The power-on and power-off automatic reset circuit according to claim 1, characterized in that The power-on automatic reset circuit further includes a seventh resistor R7 and a second capacitor C6; One end of the seventh resistor R7 and the second capacitor C6 are connected in parallel and grounded, and the other end is connected between the eighth capacitor C8 and the gate of the second MOS transistor D4.
10. The power-on and power-off automatic reset circuit according to claim 1, characterized in that, The power-on automatic reset circuit further includes a third resistor R3 and a ninth capacitor C9; The third resistor R3 is connected in series to the output terminal; One end of the ninth capacitor C9 is grounded, and the other end is connected to the output terminal.