Driving circuit of radio frequency switch

Abstract

The utility model relates to the technical field of radio frequency switches, in particular to a driving circuit of a radio frequency switch, which comprises a main control chip, a level conversion circuit, a channel selection circuit, a detection circuit and a selection circuit. The main control chip is respectively connected with the level conversion circuit and the channel selection circuit; the input end of the detection circuit is connected with the output end of the channel selection circuit, the output end of the detection circuit is connected with the input end of the judgment circuit, and the output end of the judgment circuit is connected with the channel selection circuit. The detection circuit detects the voltage of the channel, and if the voltage value exceeds a parameter voltage value in the detection circuit, the selection circuit closes the channel selection circuit, so that the technical problem that the radio frequency switch receives an error level signal due to the fact that a traditional drive circuit cannot be closed immediately when an internal fault occurs is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of radio frequency switches, and more specifically, to a driving circuit for a radio frequency switch. Background Art

[0002] The driving circuit of a radio frequency switch is an important component in a radio frequency switch system. It converts a control signal into a signal for driving radio frequency components (such as MOS transistors and PIN diodes) to achieve the switching and regulation of radio frequency signals. Although traditional driving circuits can effectively control simple radio frequency switches, they cannot guarantee their stability when dealing with complex radio frequency switches. Given the crucial role of complex radio frequency switches in high-performance communication, radar, satellites, and other fields, it is particularly urgent and important to develop a driving circuit that meets their requirements and can achieve precise control.

[0003] The Chinese utility model patent with the patent name "Radio Frequency Driving Circuit, Radio Frequency Switch and Radio Frequency Chip" and the publication number CN216390968U, which has been publicly disclosed, includes a digital circuit, a driving signal generation circuit, and a latch circuit. This utility model patent not only makes the control signal output by the driving circuit stable but also improves the conduction and cutoff speeds of the radio frequency switch. However, this utility model does not have a protection mechanism. If a fault occurs inside the circuit or it is in an abnormal state, it may lead to the incorrect output of the control signal, thereby causing the opening state of the radio frequency switch to be chaotic and disorderly, resulting in unnecessary losses or risks. Summary of the Utility Model

[0004] The purpose of this application is to provide a driving circuit for a radio frequency switch, which solves the technical problem that the traditional driving circuit cannot be immediately turned off during an internal fault, resulting in the radio frequency switch receiving an incorrect level signal.

[0005] To solve the above technical problems, the solution adopted in this application is as follows:

[0006] The utility model provides a driving circuit for a radio frequency switch, including a main control chip, a level conversion circuit, and a channel selection circuit. The output end of the level conversion circuit is connected to the input end of the channel selection circuit, and the main control chip is respectively connected to the level conversion circuit and the channel selection circuit. It is characterized in that: it further includes a detection circuit and a selection circuit. The input end of the detection circuit is connected to the output end of the channel selection circuit, and the output end of the detection circuit is connected to the input end of the judgment circuit. The output end of the judgment circuit is respectively connected to the channel selection circuit and the level conversion circuit, and the main control chip controls the channel selection circuit through the judgment circuit;

[0007] The detection circuit includes a first operational amplifier, a second operational amplifier, and a third operational amplifier. The input terminal of the first operational amplifier serves as the input terminal of the detection circuit. The output terminal of the first operational amplifier, the positive input terminal of the second operational amplifier, and the negative input terminal of the third operational amplifier are connected; the output terminal of the second operational amplifier is connected to the output terminal of the third operational amplifier, and an output terminal is set here as the output terminal of the detection circuit;

[0008] The judgment circuit includes an exclusive - OR gate, a NOT gate, a first AND gate, and a selector. The input terminals of the exclusive - OR gate, the input terminal of the NOT gate, and the input terminals of the selector respectively serve as the input terminals of the judgment circuit. The output terminal of the exclusive - OR gate is connected to one input terminal of the first AND gate, the output terminal of the NOT gate is connected to the other input terminal of the first AND gate, the output terminal of the AND gate is connected to the input terminal of the selector, and the output terminal of the selector serves as the output terminal of the judgment circuit.

[0009] In some embodiments, the selector includes a second AND gate and a third AND gate. One input terminal of the second AND gate and one input terminal of the third AND gate are respectively set as the input terminals of the selector. The other input terminal of the second AND gate and the other input terminal of the third AND gate are connected, and an input terminal is set here, and this input terminal is connected to the output terminal of the first AND gate.

[0010] In some embodiments, the selector includes a decoder. The enable terminal of the decoder is connected to the output terminal of the first AND gate. The data input terminal of the decoder is connected to the main control chip, and the output terminal of the decoder serves as the output terminal of the selector.

[0011] In some embodiments, the channel selection circuit includes a first field - effect transistor, a second field - effect transistor, a detection resistor, and a second - stage non - inverting amplifier. The gate electrodes of the first field - effect transistor and the second field - effect transistor respectively serve as the control input terminals of the channel selection circuit. The drain electrodes of the first field - effect transistor and the second field - effect transistor respectively serve as the signal input terminals of the channel selection circuit. The source electrode of the first field - effect transistor is connected to one end of the resistor under test. The source electrode of the second field - effect transistor, the other end of the resistor under test, and the positive input terminal of the second - stage non - inverting amplifier are connected. The output terminal of the second - stage non - inverting amplifier is set as the output terminal of the channel selection circuit.

[0012] In some embodiments, the channel selection circuit further includes a protection circuit. The source electrode of the first field - effect transistor is connected to the positive electrode of the second - stage non - inverting amplifier through the protection circuit.

[0013] In some embodiments, the protection circuit includes an inductor, a diode, and a capacitor. The inductor is connected in series with the first field effect transistor. The positive electrode of the diode and one end of the capacitor are connected to the inductor. The negative electrode of the diode and the other end of the capacitor are both grounded.

[0014] In some embodiments, the level conversion circuit includes a triode, a first-stage non-inverting amplifier, and a first-stage inverting amplifier. The base of the triode serves as the input end of the level conversion circuit. The emitter of the triode, the negative input end of the first-stage non-inverting amplifier, and the positive input end of the first-stage inverting amplifier are connected. The judgment circuit controls the non-inverting amplification signal of the first-stage non-inverting amplifier and the inverting amplification signal of the first-stage inverting amplifier through the triode. The output end of the first-stage non-inverting amplifier and the output end of the first-stage inverting amplifier are respectively set as the output ends of the level conversion circuit.

[0015] In some embodiments, the level conversion circuit further includes a delay circuit. The output end of the first-stage non-inverting amplifier and the output end of the first-stage inverting amplifier are connected to the input end of the channel selection circuit through the delay circuit.

[0016] In some embodiments, the delay circuit is an LC delay circuit.

[0017] The technical solution of this application has at least the following advantages and beneficial effects:

[0018] In this utility model, a detection circuit and a selection circuit are provided. The detection circuit is used to detect the voltage condition in the channel switching circuit. The selection circuit is used to control the on-off state of the channel selection circuit. When the detection circuit detects that the voltage value at the output end of the channel switching circuit is greater than the threshold voltage, the detection circuit sends a signal to the selection circuit. The selection circuit controls all the circuit channels in the channel selection circuit to be disconnected according to this signal, solving the technical problem that the traditional drive circuit cannot be immediately turned off during internal faults, resulting in the RF switch receiving incorrect level signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is the detection circuit diagram of this utility model;

[0020] Figure 2 It is a judgment circuit diagram of this utility model;

[0021] Figure 3 It is the channel selection circuit diagram of this utility model;

[0022] Figure 4 It is the level conversion circuit diagram of this utility model;

[0023] Figure 5 It is another judgment circuit diagram of this utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part rather than all of the embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without making creative efforts shall fall within the protection scope of the present utility model.

[0025] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. If terms such as "center", "upper", "lower", "inner", "outer", etc. indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the product of this application is usually placed. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to this application. It should also be noted that unless otherwise clearly specified and limited, if terms such as "set", "installed", "connected" are understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0026] Embodiment 1

[0027] Please refer to Figures 1 - 5 , the present utility model provides a driving circuit for a radio frequency switch. The same as the prior art, it includes a main control chip, a level conversion circuit, and a channel selection circuit. The output end of the level conversion circuit is connected to the input end of the channel selection circuit, and the main control chip is respectively connected to the level conversion circuit and the channel selection circuit;

[0028] It should be noted that the model of the main control chip is STM32G070CBT6.

[0029] Different from the prior art, it further includes a detection circuit and a selection circuit. The input end of the detection circuit is connected to the output end of the channel selection circuit, and the output end of the detection circuit is connected to the input end of the judgment circuit; the output end of the judgment circuit is respectively connected to the channel selection circuit and the level conversion circuit, and the main control chip controls the channel selection circuit through the judgment circuit.

[0030] When the drive circuit is working, the main control chip sends a signal to the judgment circuit, and the judgment circuit preliminarily judges whether the control signal of the main control chip is abnormal; if there is no abnormal phenomenon, the judgment circuit outputs signals to the level conversion circuit and the channel selection circuit respectively. After receiving the signal, the level conversion circuit starts to output a positive voltage or a negative voltage signal. After receiving the signal, the channel selection circuit turns on the positive voltage channel or the negative voltage channel, so that the RF switch connected to the output end of the channel selection circuit obtains a positive voltage control signal or a negative voltage control signal, and then the RF switch turns on;

[0031] The detection circuit real-time detects the voltage condition of the output end of the channel selection circuit. If the detection circuit detects that the voltage value at the output end of the channel switching circuit is greater than the threshold voltage, the detection circuit sends a signal to the selection circuit, and the selection circuit cuts off all circuit channels in the channel selection circuit according to this signal to prevent the wrong level signal from being transmitted to the RF switch.

[0032] The detection circuit includes a first operational amplifier, a second operational amplifier and a third operational amplifier. The input end of the first operational amplifier serves as the input end of the detection circuit, and the output end of the first operational amplifier, the positive input end of the second operational amplifier and the negative input end of the third operational amplifier are connected; the output end of the second operational amplifier is connected to the output end of the third operational amplifier, and an output end is set here as the output end of the detection circuit.

[0033] Further, as Figure 1 shown, the detection circuit includes a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, resistors R1, R2, R3, R4, R5, R6, R7, and diodes D1, D2;

[0034] Specifically, one end of resistor R1 is set as the t_in1 input terminal, and one end of resistor R2 is set as the t_in2 input terminal. The t_in1 input terminal and the t_in2 input terminal are respectively connected to the level conversion circuit; the other end of resistor R1 is connected to the positive input terminal of the first operational amplifier U1, and the other end of resistor R2, the negative input terminal of the first operational amplifier U1, and one end of resistor R3 are connected, and one end of resistor R3 is connected; the pin 2 of the first operational amplifier U1 is connected to the positive power supply, and the pin 5 is grounded. The output terminal of the first operational amplifier U1, the other end of resistor R3, the positive input terminal of the second operational amplifier U2, and the negative input terminal of the third operational amplifier U3 are connected. The negative input terminal of the second operational amplifier U2, one end of resistor R4, and one end of resistor R5 are connected. The other end of resistor R4 is connected to the positive power supply, and the other end of resistor R5 is grounded; the positive input terminal of the third operational amplifier U3, one end of resistor R6, and one end of resistor R7 are connected. The other end of resistor R6 is connected to the positive power supply, and the other end of resistor R7 is grounded; the pin 5 of the second operational amplifier U2 is connected to the positive power supply, and the pin 4 is connected to the negative power supply; the pin 5 of the third operational amplifier U3 is connected to the positive power supply, and the pin 4 is connected to the negative power supply; the output terminal of the second operational amplifier U2 is connected to the positive electrode of diode D1, and the output terminal of the third operational amplifier U3 is connected to the positive electrode of diode D2. The negative electrodes of diode D1 and diode D2 are connected, and the t_out output terminal is set here.

[0035] The judgment circuit includes an exclusive - OR gate, a NOT gate, a first AND gate, and a selector. The input terminals of the exclusive - OR gate, the input terminal of the NOT gate, and the input terminals of the selector are respectively used as the input terminals of the judgment circuit. The output terminal of the exclusive - OR gate is connected to one input terminal of the first AND gate, the output terminal of the NOT gate is connected to the other input terminal of the first AND gate, the output terminal of the AND gate is connected to the input terminal of the selector, and the output terminal of the selector is used as the output terminal of the judgment circuit;

[0036] The selector includes a second AND gate and a third AND gate. One input terminal of the second AND gate and one input terminal of the third AND gate are respectively set as the input terminals of the selector. The other input terminal of the second AND gate and the other input terminal of the third AND gate are connected, and the input terminal is set here, and this input terminal is connected to the output terminal of the first AND gate.

[0037] Further, as Figure 2 shown, a judgment circuit includes an exclusive - OR gate U4, a NOT gate U5, AND gates U6, U7, U8;

[0038] Specifically, the A input terminal of the exclusive-OR gate U4 is set as the d_in1 input terminal, the B input terminal is set as the d_in2 input terminal, the Y output terminal is connected to the B input terminal of the AND gate U6, and the d_out1 output terminal is set here; the input terminal of the NOT gate U5 is set as the d_in3 input terminal, the output terminal of the NOT gate U5 is connected to the A input terminal of the AND gate U6, the Y output terminal of the AND gate U6 is connected to the B input terminal of the AND gate U7 and the A input terminal of the AND gate U8, the A input terminal of the AND gate U7 is connected to the pin PA4 of the main control chip, and the B input terminal of the AND gate U8 is connected to the pin PA5 of the main control chip; the Y output terminal of the AND gate U7 is set as the d_out2 output terminal, and the Y output terminal of the AND gate U8 is set as the d_out3 output terminal.

[0039] In some embodiments, the selector includes a decoder. The enable terminal of the decoder is connected to the output terminal of the first AND gate. The data input terminals of the decoder are connected to the pins of the main control chip, and the output terminal of the decoder serves as the output terminal of the selector.

[0040] Further, as Figure 5 shown, another judgment circuit includes an exclusive-OR gate U9, a NOT gate U10, an AND gate U11, and a decoder U12.

[0041] It should be noted that the model of the decoder U12 in this embodiment is 74HC138D.

[0042] Specifically, the A input terminal of the exclusive-OR gate U9 is set as the d_in1 input terminal, the B input terminal is set as the d_in2 input terminal, the Y output terminal is connected to the B input terminal of the AND gate U11, and the d_out1 output terminal is set here; the input terminal of the NOT gate U10 is set as the d_in3 input terminal, the output terminal of the NOT gate U10 is connected to the A input terminal of the AND gate U11, the Y output terminal of the AND gate U11 is connected to the pin 6 of the decoder U12, and the pins 4, 5, and 8 of the decoder are connected and grounded; the pin 16 of the decoder U12 is connected to the power supply, and the pins 1, 2, and 3 of the decoder U12 are respectively connected to the pins PA4, PA5, and PA6 of the main control chip; the pins 15, 14, 13, 12, 11, 10, 9, and 7 of the decoder U12 are respectively set as the d_out2 output terminal, the d_out3 output terminal, the d_out4 output terminal, the d_out5 output terminal, the d_out6 output terminal, the d_out7 output terminal, the d_out8 output terminal, and the d_out9 output terminal.

[0043] It should be noted that the advantage of the another judgment circuit is that it can control the on-off states of a large number of channels by connecting a small number of pins of the main control chip, enhancing the control ability of complex RF switches.

[0044] It should be noted that the d_in1 input terminal and the d_in2 input terminal of the judgment circuit are both connected to the pins of the main control chip, and the d_in3 input terminal of the judgment circuit is connected to the t_out output terminal of the detection circuit.

[0045] The channel selection circuit includes a first field-effect transistor, a second field-effect transistor, a detection resistor, and a second-stage non-inverting amplifier. The gates of the first field-effect transistor and the second field-effect transistor are respectively used as the control input terminals of the channel selection circuit. The drains of the first field-effect transistor and the second field-effect transistor are respectively used as the signal input terminals of the channel selection circuit. The source of the first field-effect transistor is connected to one end of the resistor under test. The source of the second field-effect transistor, the other end of the resistor under test, and the positive input terminal of the second-stage non-inverting amplifier are connected. The output terminal of the second-stage non-inverting amplifier is set as the output terminal of the channel selection circuit;

[0046] The channel switching circuit further includes a protection circuit. The source of the first field-effect transistor is connected to the positive terminal of the second-stage non-inverting amplifier through the protection circuit. The protection circuit includes an inductor, a diode, and a capacitor. The inductor is connected in series with the first field-effect transistor. The positive terminal of the diode and one end of the capacitor are connected to the inductor. The negative terminal of the diode and the other end of the capacitor are both grounded.

[0047] It should be noted that the function of the protection circuit is to provide overvoltage protection.

[0048] It should be noted that the channel selection circuit can select a positive voltage or a negative voltage to control radio frequency switches with different biases.

[0049] Furthermore, as Figure 3 shown, the channel switching circuit includes a first field-effect transistor Q2, a second field-effect transistor Q3, a detection resistor R16, an operational amplifier U14, an inductor L3, diodes D3, D4, a capacitor C3, and resistors R17, R18, R19;

[0050] Among them, the second-stage non-inverting amplifier includes an operational amplifier U14 and resistors R17, R18, R19; the protection circuit includes an inductor L3, a diode D4, and a capacitor C3;

[0051] Specifically, the gate of the first field-effect transistor Q2 is set as the ch_in3 input terminal, and the drain of the first field-effect transistor Q2 is set as the ch_in1 input terminal; the gate of the second field-effect transistor Q3 is set as the ch_in4 input terminal, and the drain of the second field-effect transistor Q3 is set as the ch_in2 input terminal; the source of the first field-effect transistor Q2, the positive electrode of the diode D3, and one end of the inductor L3 are connected, and the other end of the diode D3 is grounded; the other end of the inductor L3 is connected to one end of the resistor R16 to be measured, and the ch_out1 output terminal is set here; the other end of the resistor R16 to be measured, one end of the capacitor C3, one end of the diode D4, the source of the second field-effect transistor Q3, and one end of the resistor R17 are connected, and the ch_out2 output terminal is set here; the other end of the resistor R17 is connected to the positive input terminal of the operational amplifier U14. The negative input terminal of the operational amplifier U14, one end of the resistor R18, and one end of the resistor R19 are connected. The other end of the resistor R18 is grounded, and the other end of the resistor R19 is connected to the output terminal of the operational amplifier U14, and the ch_out3 output terminal is set here; the pin 2 of the operational amplifier U14 is connected to the power supply, and the pin 5 is grounded.

[0052] It should be noted that the ch_in3 input terminal and the ch_in4 input terminal in the channel switching circuit are respectively connected to the d_out2 output terminal and the d_out3 output terminal in the judgment circuit; the ch_out1 output terminal and the ch_out2 output terminal in the channel switching circuit are respectively connected to the L_in1 input terminal and the L_in2 input terminal of the detection circuit; the ch_out3 output terminal in the channel switching circuit is connected to the control terminal of the radio frequency switch.

[0053] The level conversion circuit includes a triode, a first-stage non-inverting amplifier, and a first-stage inverting amplifier. The base of the triode is used as the input terminal of the level conversion circuit. The emitter of the triode, the negative input terminal of the first-stage non-inverting amplifier, and the positive input terminal of the first-stage inverting amplifier are connected. The judgment circuit controls the first-stage non-inverting amplifier to amplify the signal in the same direction and the first-stage inverting amplifier to amplify the signal in the opposite direction through the triode; the output terminals of the first-stage non-inverting amplifier and the first-stage inverting amplifier are respectively set as the output terminals of the level conversion circuit;

[0054] The level conversion circuit further includes a delay circuit. The output terminals of the first-stage non-inverting amplifier and the first-stage inverting amplifier are connected to the input terminal of the channel selection circuit through the delay circuit.

[0055] It should be explained that the delay circuit is an LC delay circuit.

[0056] Furthermore, as Figure 4As shown in the figure, the level conversion circuit includes a triode Q1, capacitors C1 and C2, inductors L1 and L2, operational amplifiers U9 and U10, resistors R8, R9, R10, R11, R12, R13, R14, R15, and a diode D5;

[0057] Among them, the first-stage non-inverting amplifier includes an operational amplifier U9, resistors R10, R11, and R15; the first-stage inverting amplifier includes an operational amplifier U10, resistors R12, R13, and R14; a group of LC delay circuits includes an inductor L1 and a capacitor C1; the second group of LC delay circuits includes an inductor L2 and a capacitor C2;

[0058] Specifically, one end of the resistor R8 is set as the L_in input terminal, the other end of the resistor R8, the positive electrode of the diode D5, and the base of the triode Q1 are connected. The collector of the triode Q1 is connected to the power supply. The emitter of the triode Q1, one end of the resistor R9, one end of the resistor R10, and one end of the resistor R13 are connected. The negative electrode of the diode D5 is connected to the other end of the resistor R9 and grounded here; the other end of the resistor R10 is connected to the positive input terminal of the operational amplifier U9. The negative input terminal of the operational amplifier U9, one end of the resistor R11, and one end of the resistor R15 are connected. The other end of the resistor R11 is connected to one end of the resistor R12 and grounded; the other end of the resistor R12 is connected to the operational amplifier U10. The other end of the resistor R13, the negative input terminal of the operational amplifier U10, and one end of the resistor R14 are connected; the pin 2 of the operational amplifier U9 is connected to the positive power supply, and the pin 5 is grounded; the pin 2 of the operational amplifier U10 is connected to the positive power supply, and the pin 5 is grounded; the output terminal of the operational amplifier U9, the other end of the resistor R15, one end of the capacitor C1, and one end of the inductor L1 are connected. The other end of the capacitor C1 is grounded, and the other end of the inductor L1 is set as the L_out1 output terminal; the output terminal of the operational amplifier U10, the other end of the resistor R14, one end of the capacitor C2, and one end of the inductor L2 are connected. The other end of the capacitor C2 is grounded, and the other end of the inductor L2 is set as the L_out2 output terminal.

[0059] It should be noted that the L_in input terminal in the level conversion circuit is connected to the d_out1 output terminal in the judgment circuit. The L_out1 output terminal and the L_out2 output terminal in the level conversion circuit are used as the output terminals of the level conversion circuit and are respectively connected to the ch_in1 input terminal and the ch_in2 input terminal in the channel selection circuit.

[0060] To facilitate the understanding of the detection circuit and the judgment circuit, the working process of this drive circuit is described as follows:

[0061] Under normal working conditions, the judgment circuit controls the channel detection circuit and the level conversion circuit to work according to the signal of the main control chip; the detection circuit continuously detects the voltage across the resistor to be measured in the channel selection circuit;

[0062] The detection circuit differentially amplifies the collected voltage. The amplified voltage is simultaneously compared with a set voltage threshold through a second operational amplifier and a third operational amplifier, and a control signal is output to the judgment circuit according to the comparison result;

[0063] If the detection circuit detects that the voltage across the resistor under test exceeds the threshold voltage, the detection circuit sends a high level to the judgment circuit, and the judgment circuit closes all switches in the channel selection circuit and controls the level conversion circuit to stop working.

[0064] So far, the embodiments of the present invention have been described in detail. To avoid obscuring the concept of the present invention, some details well known in the art are not described. Those skilled in the art can clearly understand how to implement the technical solutions of the present invention according to the above description. The scope of the present invention is defined by the appended claims.

Claims

1. A driving circuit for a radio frequency switch, comprising a main control chip, a level conversion circuit, and a channel selection circuit. The output end of the level conversion circuit is connected to the input end of the channel selection circuit, and the main control chip is respectively connected to the level conversion circuit and the channel selection circuit; characterized in that: It further includes a detection circuit and a selection circuit. The input end of the detection circuit is connected to the output end of the channel selection circuit, and the output end of the detection circuit is connected to the input end of the judgment circuit. The output end of the judgment circuit is respectively connected to the channel selection circuit and the level conversion circuit, and the main control chip controls the channel selection circuit through the judgment circuit. The detection circuit includes a first operational amplifier, a second operational amplifier, and a third operational amplifier. The input end of the first operational amplifier serves as the input end of the detection circuit, and the output end of the first operational amplifier, the positive input end of the second operational amplifier, and the negative input end of the third operational amplifier are connected. The output end of the second operational amplifier is connected to the output end of the third operational amplifier, and an output end is set here as the output end of the detection circuit. The judgment circuit includes an exclusive OR gate, a NOT gate, a first AND gate, and a selector. The input ends of the exclusive OR gate, the NOT gate, and the selector respectively serve as the input ends of the judgment circuit. The output end of the exclusive OR gate is connected to one input end of the first AND gate, the output end of the NOT gate is connected to the other input end of the first AND gate, the output end of the AND gate is connected to the input end of the selector, and the output end of the selector serves as the output end of the judgment circuit.

2. The driving circuit of a radio frequency switch according to claim 1, wherein The selector includes a second AND gate and a third AND gate. One input end of the second AND gate and one input end of the third AND gate are respectively set as the input ends of the selector. The other input end of the second AND gate is connected to the other input end of the third AND gate, and an input end is set here. And this input end is connected to the output end of the first AND gate.

3. The drive circuit of a radio frequency switch according to claim 1, characterized in that, The selector includes a decoder. The enable end of the decoder is connected to the output end of the first AND gate. The data input end of the decoder is connected to the main control chip, and the output end of the decoder serves as the output end of the selector.

4. The driving circuit of a radio frequency switch according to claim 1, wherein The channel selection circuit includes a first field effect transistor, a second field effect transistor, a detection resistor, and a second-order non-inverting amplifier. The gates of the first field effect transistor and the second field effect transistor respectively serve as the control input ends of the channel selection circuit. The drains of the first field effect transistor and the second field effect transistor respectively serve as the signal input ends of the channel selection circuit. The source of the first field effect transistor is connected to one end of the resistor to be measured. The source of the second field effect transistor, the other end of the resistor to be measured, and the positive input end of the second-order non-inverting amplifier are connected. The output end of the second-order non-inverting amplifier is set as the output end of the channel selection circuit.

5. The driving circuit of a radio frequency switch according to claim 4, wherein, The channel selection circuit further includes a protection circuit. The source of the first field effect transistor is connected to the positive electrode of the second-order non-inverting amplifier through the protection circuit.

6. The drive circuit of a radio frequency switch according to claim 5, wherein The protection circuit includes an inductor, a diode, and a capacitor. The inductor is in series with the first field effect transistor. The positive electrode of the diode and one end of the capacitor are connected to the inductor, and the negative electrode of the diode and the other end of the capacitor are both grounded.

7. The drive circuit of a radio frequency switch according to claim 1, characterized in that The level conversion circuit includes a triode, a first-stage non-inverting amplifier, and a first-stage inverting amplifier. The base of the triode serves as the input end of the level conversion circuit. The emitter of the triode, the negative input end of the first-stage non-inverting amplifier, and the positive input end of the first-stage inverting amplifier are connected. The judgment circuit controls the non-inverting amplification signal of the first-stage non-inverting amplifier and the inverting amplification signal of the first-stage inverting amplifier through the triode. The output ends of the first-stage non-inverting amplifier and the first-stage inverting amplifier are respectively set as the output ends of the level conversion circuit.

8. The driving circuit of a radio frequency switch according to claim 7, characterized in that, The level conversion circuit further includes a delay circuit. The output ends of the first-stage non-inverting amplifier and the first-stage inverting amplifier are connected to the input end of the channel selection circuit through the delay circuit.

9. The driving circuit of a radio frequency switch according to claim 8, characterized in that, The delay circuit is an LC delay circuit.

Images