Speed sensor emulator for hardware in loop

Abstract

A speed sensor emulator for hardware in a loop is presented. In one example, a sensor simulation system includes a first storage device configured to receive a signal at an input of the first storage device and provide a first voltage output to a first voltage-controlled current source; and a second memory device configured to receive a reverse signal of the signal at the second memory device input and to provide a second voltage output to a second voltage-controlled current source.

Description

Technical Field

[0001] The present disclosure relates to a method and system for simulating a speed sensor with a current output. The speed sensor can provide speed feedback for an internal combustion engine, an electric motor, a wheel, a sprocket, or other rotating devices. Background Art

[0002] A hardware-in-the-loop (HIL) system can be connected to a controller (e.g., a vehicle system controller, an engine controller, an electromechanical controller, a brake system controller, etc.). When the controller is deployed in the system, the HIL system can simulate sensors, actuators, and other devices connected to the controller. The HIL system can receive inputs from the controller and provide outputs to the controller as part of the process of evaluating the controller. One type of output that the HIL system can provide to the controller operating as a device under test is an analog speed signal, which generates an output voltage from the HIL system. Although a sensor of the output voltage may be effective for some systems, in other systems, such as those that generate higher electrical noise, its effect may be poor. A sensor of the output voltage level may give way to other sensors that are less susceptible to electrical noise. Therefore, it is desirable for the HIL system to simulate other types of speed sensors that are less affected by electrical noise. Summary of the Utility Model

[0003] The inventors herein have recognized the above problems and developed a sensor simulation system that includes: a first trigger configured to receive a signal at a clock input terminal of the first trigger and provide a first voltage output to a first voltage-controlled current source; a second trigger configured to receive a reverse signal at a clock input terminal of the second trigger and provide a second voltage output to a second voltage-controlled current source.

[0004] By generating a signal through the HIL system and inputting the signal into two triggers that drive voltage-controlled current sources, a technical result of simulating the current output of a speed sensor can be provided. Specifically, the HIL system can generate a pulse-width modulation signal through a digital output and input the signal and its reverse signal into two triggers. The triggers can generate a first signal and a second signal, where the second signal has a different phase from the first signal. The first and second signals can provide inputs to two voltage-controlled current sources, and the two voltage-controlled current sources can be electrically coupled to the device under test.

[0005] This description has several advantages. In particular, the method can reliably simulate a speed sensor with a current output. In addition, the method can also enable the HIL system to simulate a speed sensor with a current output at a lower financial cost. In addition, the method can also be applied to a single-wire sensor that encodes the rotation direction of a device into the duty cycle of an output signal.

[0006] It is understood that the above summary is intended to introduce concepts further described in the detailed description in a simplified form. This is not meant to identify the key or essential features of the claimed subject matter, the scope of which is uniquely determined by the claims that follow the detailed description. Furthermore, the claimed subject matter is not limited to embodiments that solve any disadvantages noted in the foregoing or any part of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein by reference in their entirety as part of this specification, illustrate embodiments of the disclosed subject matter and together with the description, serve to explain the principles and teachings of the selected embodiments of the disclosed subject matter. However, the drawings do not illustrate all possible implementations of the disclosed subject matter and are not intended to limit the scope of the disclosure in any way.

[0008] Figure 1 is a schematic diagram of a vehicle with a controller and wheel speed sensors;

[0009] Figure 2 shows an example block diagram of a HIL system connected to Figure 1 the controller;

[0010] Figure 3 shows an example circuit for simulating a speed sensor with a current output;

[0011] Figure 4 shows the truth table of a D flip - flop;

[0012] Figure 5 shows an example of a speed sensor and rotation direction;

[0013] Figure 6 shows Figure 3 the signal output of a circuit;

[0014] Figure 7 shows an example of simulating a change in the direction of a monitored wheel or axle;

[0015] Figure 8 and Figure 9 shows an example state machine for simulating a speed sensor with a current output; and

[0016] Figures 10 - 12 shows an example sequence for simulating speed sensor degradation. DETAILED DESCRIPTION

[0017] The following description relates to systems and methods for simulating a speed sensor with a current output via a HIL system. In one example, the HIL outputs a pulse - width - modulated signal with a digital voltage and converts the digital voltage output into two current outputs to reduce effects that may be associated with electrical noise sources such as switching transistors of an inverter, etc. The HIL system and speed sensor simulation can be used to evaluateFigure 1 Components and systems of a vehicle of the type shown. The configuration of the HIL system is as Figure 2 shown. The HIL system may include Figure 3 the speed sensor current output simulation circuit shown, or it may be modified to interface with the speed sensor. The trigger of the simulation circuit may operate as Figure 4 shown in the truth table of Figure 5 shown. The simulation circuit may simulate the operation of the speed sensor, as Figure 6 and Figure 7 shown. The functions of the simulation circuit and the HIL system may be as Figure 8 and Figure 9 shown. The simulation circuit and the HIL system may operate according to the state machines of Figures 10 - 12 shown. The simulation circuit and the HIL system may also simulate the attenuation of the speed sensor, as

[0018] It should be understood that, unless there are express contrary provisions, the present disclosure may adopt various different orientations and step sequences. It should also be understood that the specific devices and processes illustrated in the drawings and described in the specification are merely exemplary embodiments of the utility model concepts disclosed herein. Accordingly, specific dimensions, orientations, or other physical characteristics related to the various disclosed embodiments should not be considered restrictive unless expressly stated otherwise.

[0019] Within the scope of the present disclosure, by way of non-limiting example, the methods and systems of the HIL system may be applied to automobiles, off-road vehicles, all-terrain vehicles, construction and structural applications. By way of non-limiting example, the methods and systems for constructing and operating the HIL system disclosed herein may also be used to evaluate control systems of passenger vehicles, electric vehicles, hybrid vehicles, commercial vehicles, and autonomous vehicles.

[0020] Figure 1 An example of a vehicle powertrain 199 in vehicle 100 is shown. Figure 1 Mechanical connections are shown by solid lines and electrical connections are shown by dashed lines in

[0021] Vehicle 100 includes a front side 110 and a rear side 111. Vehicle 100 includes front wheels 102 and rear wheels 103. In this example, vehicle 100 is configured as a two-wheel drive vehicle; however, in other examples, vehicle 100 may be configured as a four-wheel drive vehicle. Vehicle 100 includes a propulsion source 120 that selectively provides propulsion force to rear axle 190 and front axle 101. Propulsion source 120 may be an internal combustion engine (e.g., spark ignition or diesel), or, propulsion source 120 may be an electric motor (e.g., a motor / generator), or a combination of both. Propulsion source 120 shown in the figure is mechanically connected to transmission 140, and transmission 140 is mechanically connected to rear axle 190. Propulsion source 120 provides mechanical power to transmission 140. Rear axle 190 may receive mechanical power from transmission 140, thereby transmitting the mechanical power to rear wheels 103.

[0022] Rear axle 190 consists of two half shafts, including a first or right half shaft 190a and a second or left half shaft 190b. Rear axle 190 may be an integrated axle that includes a differential gear set 191. When vehicle 100 is traveling and turning on the road, differential gear set 191 can open so that the rotational speed of the right rear wheel can be different from the rotational speed of the left rear wheel. Differential gear set 191 enables vehicle 100 not to drag the right rear wheel or the left rear wheel when turning.

[0023] Vehicle 100 includes a controller 144, which includes a read-only memory (ROM or non-temporary memory) 114, a random access memory (RAM) 116, a digital processor or central processing unit (CPU) 160, and input and output terminals (I / O) 118 (e.g., digital input terminals, digital output terminals, analog input terminals, and analog output terminals including counters, timers, and discrete input terminals). Controller 144 can receive signals from sensors 154 (including transmission output shaft speed sensor 186, propulsion source temperature sensor, wheel speed sensor 185, propulsion source speed sensor 187, etc.), and provide control signal outputs to actuators 156 (including propulsion source torque actuators, axle locking actuators, etc.). Controller 144 can communicate with instrument panel 130, propulsion source 120, external controllers, external servers, and other controllers (if any).

[0024] Vehicle 100 may further include a dashboard 130 with which a human operator of the vehicle may interact. The dashboard 130 may include an interactive navigation system 134 that may generate and display a travel route based on user input. The dashboard 130 may further include a display system 132 configured to display information to the vehicle operator. As a non-limiting example, the display system 132 may include a touchscreen or a human-machine interface (HMI) display that enables the vehicle operator to view graphical information and input commands. In some examples, the display system 132 may be wirelessly connected to the Internet (not shown) via a controller 144. Thus, in some examples, the vehicle operator may communicate with an Internet website or a software application (App) and the controller 144 via the display system 132. The dashboard 130 and the devices therein may be powered by a battery 139. The battery 139 may also power the controller 144 and a starting motor (not shown) for the propulsion source 120.

[0025] The dashboard 130 may further include an operator interface 136 through which the vehicle operator may adjust the operating state of the vehicle. Specifically, the operator interface 136 may be configured to initiate and / or terminate the operation of the vehicle's driveline (e.g., the propulsion source 120) based on operator input. Various examples of the operator interface 136 may include an interface that utilizes a physical device (such as an active key) that may be inserted into the operator interface 136 to start the propulsion source 120 and turn on the vehicle 100, or may be removed to turn off the propulsion source 120 and turn off the vehicle. The spatial orientation of the vehicle 100 and the vehicle axis are indicated by axis 176.

[0026] Now referring Figure 2 , to FIG. 200 which shows a block diagram 200 including a HIL system 202 for evaluating real-time control. In this example, the controller 144 is electrically coupled to the HIL system 202 for evaluating whether the controller 144 meets real-time control criteria and objectives.

[0027] The HIL system 202 includes a first simulation model 204 that consists of a first computer core (such as a computer processor) 206 including a random access memory 206a and a read-only memory 206b. The first simulation model 204 and the first computer core 206 may be associated with one or more modules (such as 208, 210, 222, and 224). The modules (such as 208, 210, 222, and 224) may consist of software (such as executable code) and / or hardware.

[0028] The modules of the first simulation model 204 include a control model 208, a scheduler 210, a nominal bus communication channel 222, and a BSP layer module 224. The HIL system 202 includes a real-time operating system for the scheduling control model 208 (such as the first model) and the physical system model 244 (such as the second model). The HIL system 202 can be used to verify whether the device under test (such as the controller 144) complies with its operating specifications. The task of the control model 208 of the HIL system 202 is to verify whether the device under test complies with its operating specifications, but the execution of the physical model algorithm 244 may not interfere with the real-time operation of the control model 208, thus achieving an effective verification of the device under test.

[0029] The first simulation model 204 can communicate with the device under test through the board support package (BSP) layer 224, which may include software device drivers. The BSP layer 224 may include a controller area network (CAN) bus and analog signals. The BSP layer 224 interfaces only with the control model 208. The BSP layer 224 enables external access from the control model 208 to the device under test (such as the controller 144). The control model 208 executes according to the trigger signal provided by the scheduler 210. The control model 208 can perform various functions or operations, including but not limited to simulating controllers (such as transmission or engine controllers), organizing input and output data, and exchanging data with the physical system model 244. The control model 208 can facilitate the exchange of digital and analog signals between the HIL system 202 and the controller 144.

[0030] The HIL system 202 also includes a second simulation model 240, which consists of a second computer core 242, including a random access memory 242a and a read-only memory 242b. The second simulation model 240 and the second computer core 242 can be associated with one or more modules (such as 244 - 246). The modules (such as 204 - 224) can consist of software (such as executable code) and / or hardware.

[0031] The modules of the second simulation model 240 include a physical system module 244 and a scheduler 246. The physical system module 244 can be an algorithm for simulating a physical system. The algorithm can be a simple look-up table, taking one or more inputs (such as driver demand) as a reference and outputting the operating state of the physical system (such as engine torque). Alternatively, the algorithm can include many inputs, which are processed through a linear or non-linear model, and the model generates outputs to simulate the physical system.

[0032] The controller 144 comes with a BSP layer 232 and a system monitoring section 234. The system monitoring module 234 can be included in the second computer core of the controller 144. The controller 144 also includes a nominal control module 236, which is included in the first computer core of the controller 144.

[0033] In this example, the speed sensor simulation circuit 250 is located outside the HIL system 200, but in other examples, the simulation circuit 250 can be integrated into the HIL system 200. The configuration of the speed sensor simulation circuit 250 is as Figure 3 shown. The speed sensor simulation circuit 250 can receive a digital voltage signal (e.g., a signal carrying data or information that is a function of the voltage level or signal value) from the HIL system 200 and output a current signal (e.g., a signal carrying data or information that is a function of the current level or signal value) to the controller 114.

[0034] Now refer to Figure 3 , which shows an example of a speed sensor simulation circuit 250 for a HIL system. The speed sensor simulation circuit 250 is configured to simulate the operation of a speed sensor that can monitor and indicate the speed of a wheel, sprocket, shaft, or other rotating device. The simulated speed sensor can be configured with a current output. A current output may be desirable in systems where electrical noise and electromagnetic noise may affect the output voltage of the sensor. A speed sensor with a current output can control the current in a current loop (e.g., a wire extending from the speed sensor to the sensing circuit and back to the speed sensor) to provide a higher signal-to-noise ratio. Since the circuit is a single-loop circuit, the current on the sensor is substantially equal to the current on the receiver (such as the controller 114), thereby providing a better signal-to-noise ratio.

[0035] In this example, the speed sensor simulation circuit 250 includes two output channels CH A and CH B, as Figure 6 and Figure 7 shown, and each output channel outputs a pulse-width modulated current output. The outputs of these two channels can be used as a basis for determining whether the monitored device (such as a wheel, shaft, sprocket, etc.) is rotating clockwise or counterclockwise. The sensor simulation circuit 250 consists of a first D flip-flop 304, a second D flip-flop, a first voltage-controlled current source 308, a second voltage-controlled current source 310, and an inverter 302.

[0036] The speed sensor simulation circuit 250 also includes several input terminals SA (the set input terminal of the first D flip-flop), SB (the set input terminal of the second D flip-flop), RA (the reset input terminal of the first D flip-flop), RB (the reset input terminal of the second D flip-flop), and CLKAB (the clock input terminal). The first flip-flop 304 includes a set input terminal (S), a reset input terminal (R), a clock input terminal (CLK), a data (D) input terminal, a first output terminal (Q) output terminal, and a second output terminal. The output terminal It is the reciprocal of the output Q of the output terminal. Similarly, the second flip-flop 306 includes a set input terminal (S), a reset input terminal (R), a clock input terminal (CLK), a data (D) input terminal, a first output terminal (Q) output terminal, and a second () output terminal. ) output terminal. The output terminal of each D flip-flop The output terminal of each D flip-flop is directly electrically coupled to its D input terminal. The circuit input terminal SA is directly electrically coupled to the S input terminal of the first flip-flop 304. The circuit input terminal SB is directly electrically coupled to the S input terminal of the second flip-flop 306. The circuit input terminal RA is directly electrically coupled to the R input terminal of the first flip-flop 304. The circuit input terminal RB is directly electrically coupled to the R input terminal of the second flip-flop 306. The circuit output terminal Q of the first flip-flop 304 is directly electrically coupled to the input terminal 308a of the voltage-controlled current source 308. The output terminal 308b of the voltage-controlled current source 308 is directly electrically coupled to the output terminal CH A. The circuit output terminal Q of the second flip-flop 306 is directly electrically coupled to the input terminal 310a of the voltage-controlled current source 310. The output terminal 310b of the voltage-controlled current source 310 is directly electrically coupled to the output terminal CH B. The clock input terminal CLK AB is directly electrically coupled to the clock input terminal CLK of the first flip-flop 304 and the input terminal 302a of the inverter 302. The output terminal 302b of the inverter 302 is input to the clock input terminal CLK of the second flip-flop 306. The first flip-flop 304 and the second flip-flop 306 can operate according to Figure 4 the truth table of Figure 6 and Figure 7 the sequence of

[0037] Figures 1 - 3 The system of output terminal. In a second example that may include one or both of the first and second examples, the sensor simulation system includes a first storage device and a second storage device that are D storage devices. In a second example that may include the first example, the sensor simulation system includes a first storage device that includes a first D input terminal and a first output terminal. output terminal. In a third example that may include one or both of the first and second examples, the sensor simulation system includes a second storage device that includes a second D input terminal and a second output terminal. The output terminal is electrically coupled to the first D input terminal. In a fifth example that may include one or more of the first through fourth examples, the sensor simulation system includes a second output terminal therein that is electrically coupled to a second input terminal. The second output terminal is electrically coupled to the second D input terminal. In a sixth example that may include one or more of the first through fifth examples, the sensor simulation system further includes a first S input terminal and a first R input terminal on a first storage device, and a second S input terminal and a second R input terminal on a second storage device. In a seventh example that may include one or more of the first through sixth examples, the sensor simulation system includes a hardware-in-the-loop system that generates signals and includes an output terminal coupled to the first S input terminal, the first R input terminal, the second S input terminal, and the second R input terminal. Figures 1 - 3 The system also provides a hardware-in-the-loop (HIL) system having sensor simulation capabilities, including: an HIL system coupled to a device under test; a first storage device configured to receive a signal from the HIL system at a clock input terminal of the first storage device and provide a first voltage output to a first voltage-controlled current source; and a second storage device configured to receive an inversion of the signal at a clock input terminal of the second storage device and provide a second voltage output to a second voltage-controlled current source. In a first example, the HIL system further includes a device under test coupled to the system. In a second example that may include the first example, the HIL system further includes a first digital output terminal at which the HIL system generates a signal, and additional digital output terminals at which the HIL system generates outputs to the S input terminal of the first storage device, the R input terminal of the first storage device, the S input terminal of the second storage device, and the R input terminal of the second storage device. In a third example that may include one or both of the first and second examples, the HIL system includes a first voltage-controlled current source coupled to the device under test. In a fourth example that may include one or both of the first through third examples, the HIL system includes a second voltage-controlled current source coupled to the device under test.

[0038] Next, look at Figure 4 , Figure 4 shows Figure 3 an example truth table 402 of a D flip-flop in. The truth table 402 is divided into rows 406 and columns 404. These columns include input terminals (CLK, D, R, S) and output terminals (Q and ). The row includes the space from the input end to the input and output ends of various flip - flops. The input item "rising level" refers to the situation where the signal provided to the clock input terminal CLK of the flip - flop transitions from a lower voltage (such as 0 volts) to a higher voltage (such as 5 volts). "Falling level" refers to the situation where the signal provided to the clock input terminal CLK of the flip - flop transitions from a higher voltage to a lower voltage. The higher voltage can also be referred to as logic 1 or true value, and the lower voltage can be referred to as logic 0 or false value. The input item "X" means "don't care", so the input can be logic 0, logic 1, or other values that have no effect on the output of the flip - flop.

[0039] The truth table 402 is read as follows: The first row 410 indicates that when a logic - zero - level voltage is input to the D, R, and S input terminals of the flip - flop, the output Q will be logic 0 (false), and the output will be logic 1 (true) when the signal at the input clock terminal (CLK) transitions from a low level (such as 0) to a high level (such as 1), and a logic - zero - level voltage is input to the D, R, and S input terminals of the flip - flop. Similarly, the second row 412 indicates that the output Q will be logic 1 (true), and the output will be logic 0 (false) when a logic - zero - level voltage is input to the R and S input terminals of the flip - flop, and a logic 1 voltage is applied to the D input terminal of the flip - flop when the signal input to the clock terminal (CLK) transitions from a low level (such as 0) to a high level (such as 1). The remaining rows can be read in a similar manner.

[0040] The input terminal of the first flip - flop 304 is the CLK signal. Therefore, it can switch at the rising edge of the input signal and hold the output logic value. The input terminal of the second flip - flop 306 is the inverse of the clock signal CLK, for synchronization purposes, because both input signals are generated by the same clock. This means that the second flip - flop switches and holds the output logic value at the falling edge of the clock signal or the rising edge of the inverse clock signal. When a rising edge (voltage transitions from a low voltage to a high voltage) is received at the clock input terminal CLK, the current state of the data input will be stored in the circuit, and the output Q of the flip - flop will reflect the current state of the data input terminal D. The output will be the inverse state of the Q output state. The input D is connected to the complementary outputs of the two flip - flops The complementary outputs of two flip - flops, thus generating the desired square - wave signal. There is a phase shift between the square - wave outputs of the two flip - flops, and the phase shift is proportional to the duty cycle (DC) of the input frequency signal. This is because the first flip - flop 304 and the second flip - flop 306 are triggered by the opposite edges of the pulse - width - modulated signal input at the input terminal CLK. Since the period of the pulse - width modulation is T, the rising edge and the falling edge are separated by T*DC. The periods of the two output square - waves are also 2*T (because the flip - flop divides the input frequency by two), and they are separated by 2T*DC. Finally, the set input terminal S of the flip - flop is used to set the output to the high - level state, regardless of the inputs at the D input terminal and the CLK input terminal. The reset input terminal R of the flip - flop is used to reset the output Q to the low - level state, regardless of the inputs at the D input terminal and the CLK input terminal. The set and reset states are tied to appropriate logic voltage levels (such as low - level 0 or high - level 1). The HIL system provides digital output terminals connected to the D, S, and R input terminals. However, the D, R, and S ports can be used to set defined starting conditions and generate sensor anomalies. For example, if the performance of one of the sensors degrades, its output may exhibit a constant logic level. A constant voltage level can be applied at the CLK input terminal to observe the response of the device under test.

[0041] Now look at Figure 5 , the figure shows a plan view of a speed sensor 506, whose current - output speed is used to sense the wheel speed. The wheel 502 shown in the figure has a plurality of teeth 504. The wheel 502 can rotate in the clockwise direction, as shown by CW. The wheel 502 can also rotate in the counter - clockwise direction, as shown by CCW. The movement of the teeth 504 sensed by the speed sensor 506 can cause a change in the output state of the speed sensor 506.

[0042] Now look at Figure 6 , sequence 600 shows the behavior of the speed - sensor simulation circuit 250 when the simulated speed sensor indicates a clockwise rotation. Figure 6 The sequence shown can be generated by Figure 3 the circuit shown in Figure 8 cooperating with

[0043] Figure 6 The top - most figure is a diagram of the clock signal output by the HIL system. The clock signal is a signal whose voltage level changes with the speed of the simulated rotating device. In Figure 6 another example (not shown), if the simulated rotating device is an engine speed sensor with 60 teeth rotating at a speed of 1000 revolutions per minute, the HIL system can generate a pulse - width signal that cycles between logic 0 and logic 1, with a DC voltage of 50% and a frequency of 1000 hertz. Returning to Figure 6, the logic 1 and logic 0 voltage levels are represented along the vertical axis. The horizontal axis represents time, which increases from the left side to the right side of the figure.

[0044] Figure 6 The second figure at the top shows the CH A current output of the speed sensor simulation circuit 250. The operating state of the output Q of the first flip-flop (e.g., flip-flop A) is equivalent to the output state of CH A, but the output state of the output Q of the first flip-flop is a voltage, while the output state of CH A of the speed sensor simulation circuit 250 is a current. The vertical axis represents the relationship between the current of CH A of the speed sensor simulation circuit 250 based on the logic level or state and time. The logic 1 and 0 current levels are represented along the vertical axis. The horizontal axis represents time, which increases from the left side to the right side of the figure. In this sequence, the set S and reset R inputs of the first flip-flop and the second flip-flop remain at the logic 0 level (not shown).

[0045] Figure 6 The third figure at the top shows the CH B current output of the speed sensor simulation circuit 250. The operating state of the output Q of the second flip-flop (e.g., flip-flop B) is equivalent to the output state of CH B, but the output state of the output Q of the second flip-flop is a voltage, while the output state of CH B of the speed sensor simulation circuit 250 is a current. The vertical axis represents the relationship between the current of CH B of the speed sensor simulation circuit 250 based on the logic level or state and time. The logic 1 and 0 current levels are represented along the vertical axis. The horizontal axis represents time, which increases from the left side to the right side of the figure.

[0046] At t0, the clock signal CLK is at the logic 0 level. CH A and CH B are also at the logic 0 level. At time t1, the rising edge 602 of CLK (as shown by the upward arrow) shows the transition from the low voltage level (logic 0) to the high voltage level (logic 1). This causes the flip-flop A of the speed sensor simulation circuit 250 to move from the low level state (logic 0) to the high level state (logic 1), thereby causing the CH A output of the speed sensor simulation circuit 250 to change the current level from the low level (logic 0) to the high level (logic 1). The CH B output remains unchanged because it can change its state according to the falling edge of the CLK signal.

[0047] At time t2, the falling edge 604 of CLK (as shown by the arrow below) shows a transition from a higher voltage level (logic 1) to a lower voltage level (logic 0). This causes the second flip-flop of the speed sensor simulation circuit 250 to move from a low level state (logic 0) to a high level state (logic 1), resulting in the CH B output current level of the speed sensor simulation circuit 250 changing from a low level (logic 0) to a high level (logic 1). The CH A output remains unchanged because it can change state according to the rising edge of the CLK signal. Since the CH A and CH B outputs may change due to different clock edges, a phase delay occurs, as shown at 605. The CH A output leads the CH B output in time (time increases from the left side to the right side of the figure), so this may indicate that the device is rotating in the clockwise direction.

[0048] The duty cycle of the CLK signal can be used to adjust the phase shift between CH A and CH B (as shown at 605). In addition, the CLK signal can also simulate the harsh operating conditions of the speed sensor by generating a larger phase shift between CH A and CH B. For example, the sensitive element of the speed sensor (such as the metal strip in a Hall effect sensor) undergoes a 90° mechanical displacement during installation to ensure optimal performance. However, due to mechanical limitations, this installation method may not always be possible, so a non-optimal angle of the metal strip may be used. The non-optimal angle reduces the ability of the sensor to detect the direction at higher speeds, thus reducing the performance of the speed sensor. The present utility model can simulate the non-optimal mechanical angle of the speed sensor by adjusting the phase shift between CH A and CH B, thereby simulating the challenging operating conditions of the speed sensor coupled to the controller by setting the phase shift within the boundary range of the allowable installation angle.

[0049] At time t3, another rising edge of CLK occurs, causing the first flip-flop of the speed sensor simulation circuit 250 to move from a high level state (logic 1) to a low level state (logic 0), resulting in the CH A output of the speed sensor simulation circuit 250 changing the current level from a high level (logic 1) to a low level (logic 0). The CH B output remains unchanged because it can change state according to the falling edge of the CLK signal.

[0050] At time t4, a falling edge of CLK occurs, causing the second flip-flop of the speed sensor simulation circuit 250 to move from a high level state (logic 1) to a low level state (logic 0), resulting in the CH B output of the speed sensor simulation circuit 250 changing the current level from a high level (logic 1) to a low level (logic 0).

[0051] Therefore, the outputs provided by the first and second flip - flops are half the frequency of the CLK input signal and provide two signals with different phases, so as to simulate the rotation direction from a single signal (CLK). In addition, since the CH A and CH B signals are generated from one signal (CLK), the errors generated when generating two signals with different phases through the HIL system can be avoided.

[0052] Now look at Figure 7 , sequence 700 shows the behavior of the speed sensor simulation circuit 250 when the simulated speed sensor indicates a change in the rotation direction. Figure 7 The sequence shown can be generated by Figure 3 the circuit shown in Figure 8 in conjunction with the method of

[0053] Figure 7 The top - most first figure is a diagram of the clock signal output by the HIL system. The clock signal is a signal whose voltage level changes with the speed of the simulated rotating device. In this example, the pulse - width signal generated by the HIL system cycles between logic 0 and logic 1, with a DC voltage of 50%. The logic 1 and logic 0 voltage levels are shown along the vertical axis. The horizontal axis represents time, which increases from left to right.

[0054] Figure 7 The second figure from the top shows the CH A current output of the speed sensor simulation circuit 250. The vertical axis represents the relationship between the current of CH A of the speed sensor simulation circuit 250 based on the logic level or state and time. The logic 1 and 0 current levels are represented along the vertical axis. The horizontal axis represents time, which increases from the left of the figure to the right of the figure.

[0055] Figure 7 The third figure from the top shows the CH B current output of the speed sensor simulation circuit 250. The vertical axis represents the relationship between the current of CH B of the speed sensor simulation circuit 250 based on the logic level or state and time. The logic 1 and 0 current levels are represented along the vertical axis. The horizontal axis represents time, which increases from the left of the figure to the right of the figure.

[0056] Figure 7 The fourth figure from the top shows the set input (SA) of flip - flop A of the speed sensor simulation circuit 250. The vertical axis represents the logic 1 and 0 voltage levels of the set input of flip - flop A.

[0057] Figure 7 The fifth figure from the top shows the reset input (RA) of flip - flop A of the speed sensor simulation circuit 250. The vertical axis represents the logic 1 and 0 voltage levels of the reset input of flip - flop A.

[0058] Figure 7The sixth figure at the top shows the set input (SB) of flip-flop B of the speed sensor simulation circuit 250. The vertical axis represents the logic 1 and 0 voltage levels of the set input of flip-flop B.

[0059] Figure 7 The seventh figure at the top shows the reset input (RB) of flip-flop B of the speed sensor simulation circuit 250. The vertical axis represents the logic 1 and 0 voltage levels of the reset input of flip-flop B.

[0060] The speed sensor simulation circuit 250 includes two flip-flops sensitive to the relative edges of the CLK signal. For a CLK signal with a period of T seconds, the phase shift between CH A and CH B is 2·T·DC, where DC is the duty cycle. The output of the speed sensor depends on the orientation of the speed sensor. When the speed sensor is oriented in the first way, the controller 144 detects the rotation direction of the rotating device according to the logic level of CH B at the moment of the rising edge of CH A (for example, the moment when CH A transitions from low level to high level). Therefore, there are two possibilities: if CH B is high level, it rotates clockwise; if CH B is low level, it rotates counterclockwise. If the orientation of the speed sensor is different, the situation may be reversed. However, it is important to correctly simulate the reversal of the rotation direction from the known internal state of the flip-flop and the initial conditions of the output Q and to correctly simulate the reversal of the rotation direction. Therefore, the set and reset input ports of the two flip-flops can be controlled.

[0061] At time t10, the clock signal CLK, the set input of the first flip-flop (such as flip-flop A), the reset input of the first flip-flop (such as flip-flop A), the set input of the second flip-flop (such as flip-flop BA), and the reset input of the second flip-flop (such as flip-flop B) receive logic 0 levels. CH A and CH B are also at logic 0 levels.

[0062] At time t11, the rising edge 702 of CLK (as shown by the upward arrow) shows the transition from a low voltage level (logic 0) to a high voltage level (logic 1). This causes the first flip-flop of the speed sensor simulation circuit 250 to move from a low level state (logic 0) to a high level state (logic 1), resulting in the CH A output current level of the speed sensor simulation circuit 250 changing from a low level (logic 0) to a high level (logic 1). The CH B output remains unchanged because it can change state according to the falling edge of the CLK signal. The set input of the first flip-flop, the reset input of the first flip-flop, the set input of the second flip-flop, and the reset input of the second flip-flop remain at logic 0 levels.

[0063] At time t12, the falling edge 704 of CLK (as indicated by the arrow below) shows a transition from a higher voltage level (logic 1) to a lower voltage level (logic 0). This causes the second flip - flop of the speed sensor simulation circuit 250 to move from a low state (logic 0) to a high state (logic 1), resulting in the CH B output current level of the speed sensor simulation circuit 250 changing from low (logic 0) to high (logic 1). The CH A output remains unchanged because it can change state according to the rising edge of the CLK signal. The output CH A leads the output CH B in time (time increases from the left - hand side to the right - hand side of the graph), so this may indicate that the device being tracked is rotating in a clockwise direction.

[0064] At t13, the duty cycle of the CLK signal drops to zero in preparation for simulating a change in the rotation direction of a rotating device (such as a gear, etc.). CH A is at a high level and CH B transitions from low to high. The set and reset inputs of each flip - flop are at a low level.

[0065] At time t14, the set input of the first flip - flop and the reset input of the second flip - flop transition from low to high. The reset input of the first flip - flop and the set input of the second flip - flop remain low. As shown at 706, within the time interval between t14 and t15, the internal states of the first and second flip - flops are forced to a known state. Specifically, when CLK is low, the output of the first flip - flop drives CH A to a high level and the output of the second flip - flop drives CH B to a low level.

[0066] At t15, the duty cycle of the CLK signal changes from zero to a non - zero value, causing CH A to switch from high to low. CHB remains unchanged, and the set A and reset B signals transition from high to low.

[0067] At time t16, the CLK signal transitions to a low level, and the falling edge of the CLK signal causes CH B to transition from a low state to a high state. CH A remains unchanged, and the set and reset inputs of both flip - flops remain at a low level. Thus, the rising edge of CH B now leads the rising edge of CH A to indicate a change in the direction of the simulated rotating device.

[0068] Therefore, this system can simulate a change in the rotation direction by applying logic 1 (e.g., high level) to the S and R inputs of the first and second flip - flops of the speed sensor simulation circuit 250. The HIL system can determine whether the controller perceives a change in the rotation direction because the controller may perceive the change in the rotation direction.

[0069] See Figure 8 , which shows a state - machine diagram of a method for generating a signal that is used to simulate a speed sensor with a current output of the HIL system.Figure 8 The state machine and method can be stored at least in part as executable instructions in the controller memory of the Figures 1 - 3 system. Additionally, Figure 8 the state machine and method can include actions taken in the physical world to transition Figures 1 - 3 the operating state of the system.

[0070] Block diagram 800 includes state machine 802, pulse width modulation generator 804, speed sensor simulation circuit 250, and analog input block 806. State machine 802 can be implemented by controller software, which provides two outputs (such as duty cycle and period) to pulse width modulation generator 804. State machine 802 also provides digital output settings A, B, reset A, and reset B to speed sensor simulation circuit 250. Speed sensor simulation circuit 250 provides outputs CH A and CH B to the input of state machine 802. State machine 802 also includes inputs for the rotational frequency of the simulation device (such as a toothed wheel), frequency sign (indicating rotational direction), and threshold parameters. A more detailed description of state machine 802 can be found in Figure 9 .

[0071] Now look at Figure 9 , where figure 900 showing state machine 802 is presented. Figure 9 The state machine of Figures 1 - 3 can operate in conjunction with the Figures 1 - 3 system to adjust the operating state of the Figure 9 system in the real world. Figures 1 - 3 The method of

[0072] The state machine 802 includes four states: stationary, moving, Start_fwd, and Start_rev. The state machine enters through the initial condition Init of the toStandstill function. It can enter a state when specific conditions are met, and operations can be triggered when transitioning from one state to another. The arrows between the states and their condition requirements (such as in square brackets) and operations (such as in curly brackets) are used to show the conditions and operations when transitioning from one state to another. The state machine 802 includes four functions 902 - 908. The to_Standstill function 902 is called during initialization. When moving to the moving state 926, the to_Moving function 904 can be executed. When moving to the Start_fwd state 924, the to_Forward function 906 can be executed. When moving to the Start_rev state 920, the to_Reverse function 908 can be executed. The operations in these functions can be executed during the transition between states. For example, when entering the moving state 926, the inputs of the speed sensor simulation circuit 250 can be set to Reset A = false, Reset B = false, Set A = false, and Set B = false.

[0073] For example, arrow 910 shows the transition path from the Start_rev state 920 to the moving state 926. Operations such as setting the set input of the first flip - flop or flip - flop A to false, setting the set input of the second flip - flop or flip - flop B to false, setting the reset input of the first flip - flop to false, and setting the reset input of the second flip - flop to false are indicated along one side of arrow 910.

[0074] The HIL system user can request the HIL system to simulate the speed of a wheel or other rotating device as the input to the speed sensor simulation circuit. If the absolute value of the state machine input frequency value exceeds the threshold parameter threshold_move, the state machine state will become Start_rev (reverse) or Start_fwd (forward) according to the frequency sign. The state machine remains in one of the above - mentioned states until the feedback of CH A and Ch B causes it to transition to the moving state. Once in the moving state, the input frequency of the state machine is converted to the corresponding period, and the duty cycle is set to the duty_mab_pct value. For example, duty_mab_pct = 50% means that CHA and CH B are shifted by 90°. As Figure 8 shown, the frequency and duty cycle are then sent to the PWM generator, which creates a clock control signal for the speed sensor simulation circuit.

[0075] When the absolute value of the input frequency drops below the threshold _stop, the state machine can transition to the stationary state. Note that the set value of threshold_move is greater than threshold_stop, so that the hysteresis mechanism can prevent the state machine from bouncing back and forth between the stationary and moving states when the input frequency approaches one of the two thresholds.

[0076] During the transition from one state to another, one of the following functions is called: toReverse(), toForward(), toMoving(), toStandstill(). Each of these functions can assign values to the set / reset signals of the flip-flop states on the speed sensor simulation circuit 250, so as to provide a correct initial condition (a well-known defined state) before the clock signal starts to toggle. In addition, there are two transitions from the moving state to Start_rev and Start_fwd respectively, which can be completed without passing through the stationary state. These transitions cover the case where the sign of the input frequency changes without decreasing when its absolute value is below the threshold_stop (this may occur if the threshold is set small and the integration step is large).

[0077] The state machine 802 can also be used to output specific values to the set and reset input terminals of the speed sensor simulation circuit 250 to simulate the attenuation of the speed sensor. For example, the connection between the speed sensor output on CH A and the battery voltage can be simulated by adjusting the reset A input of the speed sensor simulation circuit 250 to true or logic 1.

[0078] Therefore, Figure 8 and Figure 9 the state machine can generate the clock signal CLK, set the input and reset the input to the speed sensor simulation circuit. The state machine can also simulate the forward and reverse rotation directions.

[0079] Figure 8 and Figure 9The method provides a method for simulating a speed sensor with a current output, including: providing a signal to the clock input terminal of the first storage device, and providing the inverse of the signal to the clock input terminal of the second storage device; and providing the output of the first storage device A to the first voltage-controlled current source, and providing the output of the second storage device to the second voltage-controlled current source. In the first example, the method includes providing signals through a hardware-in-the-loop system. In a second example that may include the first example, the method includes coupling the first voltage-controlled current source and the second voltage-controlled current source to the device under test. In a third example that may include one or both of the first and second examples, the method further includes generating signals through a hardware-in-the-loop system. In a fourth example that may include one or more of the first to third examples, the method further includes electrically coupling the S and R input terminals of the first flip-flop to the hardware-in-the-loop system. In a fifth example that may include one or more examples of the first to fourth examples, the method further includes electrically coupling the S and R input terminals of the second flip-flop to the hardware-in-the-loop system. In a sixth example that may include one or more examples of the first to fifth examples, the method further includes simulating a change in the direction of the device by applying a logic true input terminal to the S input terminal of the first flip-flop and the R input terminal of the second flip-flop.

[0080] In another notation, Figure 8 and Figure 9 The method provides a method for simulating a speed sensor with a current output, which includes: providing a signal to the clock input terminal of the first storage device and providing the inverse of the signal to the clock input terminal of the second storage device; and providing the first output of the first storage device to the first voltage-controlled current source and providing the first output of the second storage device to the second voltage-controlled current source, where both the first storage device and the second storage device are D flip-flops, and where the output terminal of the first storage device is connected (e.g., directly electrically coupled) to the D input terminal of the first storage device. The output terminal of the first storage device is connected (e.g., directly electrically coupled) to the D input terminal of the first storage device. The method further includes adjusting the signal levels provided to the S and R input terminals of the first storage device through a hardware-in-the-loop system.

[0081] Now look at Figure 10 , the figure shows an example of a sequence that can be generated by the system of Figures 1 - 3 in cooperation with the method of Figure 8 and Figure 9 . Figure 10 The sequence of Figure 10 simulates a short circuit of output CH B to ground. Figure 7 The vertical and horizontal axes of

[0082] In this example, the sequence starts at time t20. All signals are at a low level, and no simulation of a CH B ground short is shown.

[0083] At time t21, CLK transitions from low to high level 1002, and the CH A output transitions from low to high level. The set and reset inputs of the speed sensor simulation circuit 250 are at a low level.

[0084] At time t22, a CH B short to ground is simulated by holding CH B at a high level. This is achieved by applying a high level (e.g., logic 1) to the set input of the second flip - flop in the speed sensor simulation circuit 250. As shown at 1004, the CLK signal transitions to a low level.

[0085] Now look at Figure 11 , which shows an example of a sequence that can be generated by the system of Figures 1 - 3 in conjunction with the method of Figure 8 and Figure 9 . Figure 11 The sequence of Figure 11 simulates a CH A short to the battery voltage. Figure 7 The vertical and horizontal axes of

[0086] are the same as those shown in

[0087] For the sake of brevity, the description of each figure is omitted.

[0088] In this example, the sequence starts at time t30. All signals are at a low level, and no simulation of a CH A battery voltage short is shown.

[0089] At time t31, CLK transitions from low to high level, as shown at 1102, and the CH A output transitions from low to high level. The set and reset inputs of the speed sensor simulation circuit 250 are at a low level. Figure 12 Now refer to Figures 1 - 3 , which shows an example of a sequence that can be generated by the system of Figure 8 in conjunction with the method of Figure 9 and Figure 12 . Figure 12 The vertical and horizontal axes of Figure 7 are the same as those shown in

[0090] In this example, the sequence starts at time t40. All signals are at a low level, and there is no analog signal showing intermittent attenuation of the speed sensor.

[0091] At time t41, CLK transitions from low to high, as shown in 1202, and the CH A output transitions from low to high. The set and reset inputs of the speed sensor simulation circuit 250 are at a low level.

[0092] At time t42, the intermittent attenuation of the CH A output is simulated by toggling the reset input of the first flip - flop of the speed sensor simulation circuit 250. When the CLK signal moves between high and low levels, the CH A output toggles with the rising and falling edges of the CLK signal.

[0093] This description explains how two D - type flip - flops (such as storage devices), two voltage - controlled current sources, and executable instructions stored in non - transitory memory form the basis of an analog speed sensor with a current output. However, it can be understood that J - K flip - flops, reset / set flip - flops, binary storage devices, and other storage devices can be arranged and configured to simulate an analog speed sensor with a current output without departing from the scope or intent of this description.

[0094] It can be understood that the configurations and routines disclosed herein are exemplary in nature, and these specific examples are not restrictive as there can be many variations. For example, the above - mentioned techniques can be applied to power systems that include different types of propulsion sources (including different types of motors and transmissions). The subject matter of this disclosure includes all novel and non - obvious combinations and sub - combinations of various systems and configurations, as well as other features, functions, and / or characteristics disclosed herein.

[0095] The following claims particularly point out certain combinations and sub - combinations that are regarded as novel and non - obvious. These claims may refer to "an" element or "a first" element or the equivalent thereof. These claims can be understood to include one or more such elements, neither requiring nor precluding two or more such elements. Other combinations and sub - combinations of the disclosed features, functions, elements, and / or characteristics can be claimed by modifying these claims or by presenting new claims in this application or a related application. These claims, whether broader, narrower, the same, or different in scope from the original claims, are also regarded as included in the subject matter of this disclosure.

Claims

1. Sensor simulation system, comprising: A first storage device configured to receive a signal at an input of the first storage device and provide a first voltage output to a first voltage-controlled current source; And A second storage device configured to receive an inverted signal of the signal at an input of the second storage device and provide a second voltage output to a second voltage-controlled current source.

2. The sensor simulation system according to claim 1, wherein the first storage device and the second storage device are D flip-flops, the input of the first storage device is a clock input, and the input of the second storage device is a clock input.

3. The sensor simulation system according to claim 1, wherein the first storage device includes a first D input terminal and a first output terminal.

4. The sensor simulation system according to claim 3, wherein the second storage device includes a second D input terminal and a second output terminal.

5. The sensor simulation system according to claim 4, wherein the first output terminal is electrically coupled to the first D input terminal.

6. The sensor simulation system according to claim 5, wherein the second output terminal is electrically coupled to the second D input terminal.

7. The sensor simulation system according to claim 1, further comprising a first S input terminal and a first R input terminal on the first storage device, and a second S input terminal and a second R input terminal on the second storage device.

8. The sensor simulation system according to claim 7, wherein a hardware-in-the-loop system generates a signal, and the hardware-in-the-loop system comprises output terminals coupled to the first S input terminal, the first R input terminal, the second S input terminal, and the second R input terminal.

Images