Composite piezoelectric substrate and resonator
By layering a silicon oxide layer between a support substrate and a piezoelectric material with a specific atomic ratio, the impedance ratio and response capability of composite piezoelectric substrates are enhanced, addressing thermal mismatch and performance issues.
Patent Information
- Application Number
- CN202422106765.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2034-08-29
AI Technical Summary
In the prior art, LT and LN and silicon oxide materials cannot be bonded directly at room temperature, resulting in the induction ratio of the composite piezoelectric substrate being unable to be effectively controlled, affecting the device's response capability.
A polycrystalline silicon layer, a SiO2 layer and a silicon oxide layer are laminated between the support substrate and the piezoelectric material layer, and the amorphous silicon layer is converted into a silicon oxide layer through oxygen diffusion, and the bonding interface is modified.
It effectively improves the device's admittance ratio and response capabilities and optimizes the performance of the resonator.
Smart Images
Figure CN223109988U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductors, and particularly relates to a composite piezoelectric substrate and a resonator. Background Art
[0002] Nowadays, devices such as surface acoustic wave devices and resonators prepared with piezoelectric materials such as LT (lithium tantalate) and LN (lithium niobate) have excellent performance. Preparing composite piezoelectric materials through room-temperature bonding technology can avoid problems caused by differences in thermal expansion coefficients between the support substrate and the material layer, material thermal mismatch, etc. However, since LT and LN cannot be directly bonded to silicon oxide at room temperature, an intermediate dielectric layer needs to be used to achieve effective bonding, such as an amorphous silicon layer. Amorphous silicon layers with different compositions / thicknesses have different effects on device performance. Moreover, the prior art cannot effectively control the admittance ratio of the piezoelectric substrate using a single amorphous silicon layer.
[0003] Therefore, it is urgent to modify the bonding interface of the composite piezoelectric substrate so as to improve the admittance ratio of the device and enhance the response ability of the device. Summary of the Utility Model
[0004] Aiming at the deficiencies of the prior art, the purpose of the utility model is to provide a composite piezoelectric substrate and a resonator. The utility model realizes the modification of the bonding interface by laminating a polysilicon layer, a SiO2 layer, and a silicon oxide layer between the support substrate and the piezoelectric material layer, effectively improving the admittance ratio and response ability of the device.
[0005] To achieve the purpose of this utility model, the following technical solutions are adopted:
[0006] In the first aspect, the utility model provides a composite piezoelectric substrate, which includes a support substrate, a polysilicon layer, a SiO2 layer, a silicon oxide layer, and a piezoelectric material layer laminated in sequence;
[0007] The atomic ratio of O to Si in the silicon oxide layer is (0.2 - 0.5):1.
[0008] The utility model realizes the modification of the bonding interface by laminating a polysilicon layer, a SiO2 layer, and a silicon oxide layer between the support substrate and the piezoelectric material layer, effectively improving the admittance ratio and response ability of the device.
[0009] In the utility model, the atomic ratio of O to Si in the silicon oxide layer is (0.2 - 0.5):1, and for example, it can be 0.2:1, 0.25:1, 0.3:1, 0.35:1, 0.4:1, 0.45:1, or 0.5:1, etc.
[0010] In the present utility model, if the atomic ratio of O to Si in the silicon oxide layer is too large, the admittance ratio of the device will decrease; if the atomic ratio of O to Si in the silicon oxide layer is too small, the improvement of the admittance ratio of the resonator is not obvious.
[0011] Preferably, the thickness of the silicon oxide layer is 1 - 25 nm, and for example, it can be 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, etc.
[0012] In the present utility model, within the above - appropriate thickness range, the admittance ratio of the device will increase with the increase of the thickness. However, if the thickness of the silicon oxide layer is too large, the admittance ratio will no longer increase, and an overly thick silicon oxide layer is not conducive to improving the process efficiency.
[0013] Preferably, the thickness of the silicon oxide layer is 3 - 15 nm.
[0014] Preferably, the support substrate is a silicon layer.
[0015] Preferably, the resistivity of the silicon layer > 1000 Ω·m, and for example, it can be 1500 Ω·m, 2000 Ω·m, 2500 Ω·m, 3000 Ω·m, 3500 Ω·m, 4000 Ω·m, etc., preferably ≥ 3000 Ω·m, and further preferably 5000 - 15000 Ω·m.
[0016] In the present utility model, as a support substrate, the silicon layer can reflect sound waves and weaken harmonic interference.
[0017] Preferably, the support substrate is spinel.
[0018] It should be noted that when the present utility model uses spinel as the support substrate, the piezoelectric material layer can be a lithium tantalate layer.
[0019] Preferably, the density of the spinel ≥ 3.58 g / cm 3 , and for example, it can be 3.6 g / cm 3 , 3.7 g / cm 3 , 3.8 g / cm 3 , 3.9 g / cm 3 or 4 g / cm 3 etc.
[0020] Preferably, the thickness of the polysilicon layer is 500 - 3000 nm, and for example, it can be 500 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, 3000 nm, etc.
[0021] Preferably, the thickness of the SiO2 layer is 500 - 3000 nm, and it can be, for example, 500 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, or 3000 nm, etc.
[0022] Preferably, the piezoelectric material layer is a lithium niobate layer or a lithium tantalate layer.
[0023] Preferably, the thickness of the piezoelectric material layer is 0.4 - 1.2 μm, and it can be, for example, 0.4 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, or 1.2 μm, etc.
[0024] In a second aspect, the present invention provides a method for preparing a composite piezoelectric substrate as described in the first aspect. The preparation method includes the following steps:
[0025] (a) Deposit a polysilicon layer and a SiO2 layer in sequence on one side surface of a support substrate, and perform ion implantation on the bonding surface to be bonded of a piezoelectric material donor to form a damaged layer;
[0026] (b) Prepare a bonded body by using any one of the following methods, including:
[0027] Method 1: Deposit an amorphous silicon layer on the side surface of the SiO2 layer away from the support substrate, and then bond the bonding surface to be bonded of the piezoelectric material donor and the surface on the amorphous silicon layer side of the support substrate;
[0028] Method 2: Deposit an amorphous silicon layer on the bonding surface to be bonded of the piezoelectric material donor, and then bond the surface on the amorphous silicon layer side of the piezoelectric material donor and the surface on the SiO2 layer side of the support substrate;
[0029] Method 3: Deposit a first sub - amorphous silicon layer on the side surface of the SiO2 layer away from the support substrate, deposit a second sub - amorphous silicon layer on the bonding surface to be bonded of the piezoelectric material donor, and then bond the surface on the second sub - amorphous silicon layer side of the piezoelectric material donor and the surface on the first sub - amorphous silicon layer side of the support substrate;
[0030] (c) Perform a dicing process on the bonded body so that the bonded body splits along the damaged layer to obtain a composite piezoelectric substrate precursor and a residual mass layer, and then perform oxygen diffusion along the split surface of the composite piezoelectric substrate precursor and diffuse it into the amorphous silicon layer, so that the amorphous silicon layer is transformed into a silicon oxide layer to obtain the composite piezoelectric substrate.
[0031] The present invention makes the amorphous silicon layer transform into a silicon oxide layer through the way of oxygen diffusion. This process helps to achieve the modification of the bonding interface and improve the admittance ratio and response ability of the device.
[0032] Preferably, the deposition method of the polysilicon layer and the SiO2 layer includes:
[0033] Deposit a polysilicon source layer on one side surface of the support substrate, and then thermally oxidize the surface layer of the polysilicon source layer to form a SiO2 layer.
[0034] It should be noted that the present invention does not limit the deposition method of the polysilicon source layer. Exemplarily, for example, it can be the LPCVD (Low Pressure Chemical Vapor Deposition) method.
[0035] Preferably, the temperature of the thermal oxidation treatment is 900 - 1100 °C, for example, it can be 900 °C, 1000 °C or 1100 °C, etc.
[0036] Preferably, in step (a), the ion implantation is performed using hydrogen ions and / or helium ions.
[0037] Preferably, the depth of the ion implantation in step (a) is 0.5 - 1.5 μm, for example, it can be 0.5 μm, 0.7 μm, 1 μm, 1.2 μm, 1.4 μm or 1.5 μm, etc.
[0038] Preferably, the dose of the ion implantation in step (a) is 5×10 16 -1×10 17 Ions / cm 2 , for example, it can be 5×10 16 Ions / cm 2 , 6×10 16 Ions / cm 2 , 7×10 16 Ions / cm 2 , 8×10 16 Ions / cm 2 , 9×10 16 Ions / cm 2 or 1×10 17 Ions / cm 2 etc.
[0039] Preferably, the bonding pressures in the first bonding mode, the second bonding mode, and the third bonding mode in step (b) are independently 1 - 100 KN, for example, it can be 1 KN, 5 KN, 10 KN, 30 KN, 50 KN, 70 KN or 100 KN, etc.
[0040] Preferably, the deposition method of the amorphous silicon layer, the first sub - amorphous silicon layer, and the second sub - amorphous silicon layer in step (b) includes the PVD (Physical Vapor Deposition) method.
[0041] Preferably, the temperature for the cleavage treatment in step (c) is 180 - 290 °C, such as 180 °C, 200 °C, 220 °C, 240 °C, 260 °C or 280 °C, etc., and the time is 0.5 - 10 h, such as 0.5 h, 1 h, 2 h, 3 h, 4 h, 5 h, 6 h, 7 h, 8 h, 9 h or 10 h, etc.
[0042] It should be noted that when performing the cleavage treatment of the present utility model, it is preferred to use the vertical wafer placement method. The advantage of vertical wafer placement is that after cleavage, the residual layer will tilt and separate under the influence of its own weight, thus forming a gap between the residual layer and the composite piezoelectric substrate precursor, leaving space for oxygen diffusion. If the wafer is placed horizontally, the residual layer after cleavage still covers the composite piezoelectric substrate precursor, and the residual layer needs to be removed first before oxygen diffusion, which requires re-creating the temperature environment and increases the manufacturing cost.
[0043] Preferably, before the cleavage treatment of the bonded body in step (c), the bonded body is first thinned. The specific steps include: thinning the non-bonded surface of the piezoelectric material donor in the bonded body so that the thickness of the piezoelectric material layer is 10 - 30 μm, such as 10 μm, 15 μm, 20 μm, 25 μm or 30 μm, etc.
[0044] In the present utility model, thinning is to reduce the thermal mismatch stress caused by the difference in thermal expansion coefficient in the subsequent steps, and can prevent the composite substrate from fragmenting.
[0045] Preferably, the temperature of the oxygen diffusion is 450 - 550 °C, such as 450 °C, 475 °C, 500 °C, 525 °C or 550 °C, etc.
[0046] In the present utility model, the temperature of oxygen diffusion will affect the oxygen content of the silicon oxide layer. If the temperature of oxygen diffusion is too low, oxygen atoms do not have enough kinetic energy for effective diffusion, and at the same time, the lattice defects generated by ion implantation in the piezoelectric wafer cannot be repaired; if the temperature of oxygen diffusion is too high, the piezoelectric wafer is prone to losing its piezoelectric properties and the device performance is lost.
[0047] Preferably, the constant temperature time of the oxygen diffusion is 4 - 20 h, such as 4 h, 6 h, 8 h, 10 h, 12 h, 14 h, 16 h, 18 h or 20 h, etc.
[0048] Preferably, during the oxygen diffusion process, the flow rate of the gas source is 5 - 20 slm, such as 5 slm, 10 slm, 15 slm or 20 slm, etc.
[0049] Preferably, the preparation method includes the following steps:
[0050] (1) Deposit a polysilicon source layer on one side surface of a silicon substrate, and then thermally oxidize the surface layer of the polysilicon source layer at a temperature of 900 - 1100 °C to form a SiO2 layer;
[0051] Inject hydrogen ions and / or helium ions into the bonding surface of the piezoelectric material donor, with the ion implantation depth being 0.5 - 1.5 μm to form a damaged layer;
[0052] (2) In a vacuum environment, prepare a bonded body with a structure of silicon substrate / polysilicon layer / SiO2 layer / amorphous silicon layer / piezoelectric material donor by any one of the following methods, including:
[0053] Method 1: Deposit an amorphous silicon layer with a thickness of 1 - 25 nm on the side surface of the SiO2 layer away from the silicon substrate, and then bond the bonding surface of the piezoelectric material donor and the surface of the silicon substrate on the amorphous silicon layer side, with the bonding pressure being 1 - 100 KN;
[0054] Method 2: Deposit an amorphous silicon layer with a thickness of 1 - 25 nm on the bonding surface of the piezoelectric material donor, and then bond the surface of the amorphous silicon layer side on the piezoelectric material donor and the surface of the SiO2 layer side on the silicon substrate, with the bonding pressure being 1 - 100 KN;
[0055] Method 3: Deposit a first sub - amorphous silicon layer on the side surface of the SiO2 layer away from the silicon substrate, deposit a second sub - amorphous silicon layer on the bonding surface of the piezoelectric material donor, the total thickness of the first sub - amorphous silicon layer and the second sub - amorphous silicon layer being 1 - 25 nm, and then bond the surface of the second sub - amorphous silicon layer side on the piezoelectric material donor and the surface of the first sub - amorphous silicon layer side on the silicon substrate, with the bonding pressure being 1 - 100 KN;
[0056] (3) Thin the non - bonding surface of the piezoelectric material donor in the bonded body so that the thickness of the piezoelectric material donor is 10 - 30 μm, and then perform a splitting process at 180 - 290 °C for 0.5 - 10 h, so that the bonded body splits along the damaged layer to obtain a composite piezoelectric substrate precursor and a residual layer;
[0057] Then raise the temperature to 450 - 550 °C, introduce an oxygen source with a flow rate of 5 - 10 slm, and perform oxygen diffusion along the split surface of the composite piezoelectric substrate precursor. The constant - temperature time for oxygen diffusion is 4 - 20 h, and the diffusion reaches the amorphous silicon layer to transform the amorphous silicon layer into a silicon oxide layer to obtain the composite piezoelectric substrate.
[0058] Thirdly, the present utility model provides a resonator, and the resonator includes the composite piezoelectric substrate as described in the first aspect.
[0059] The numerical ranges described in the present utility model not only include the point values listed above, but also any point values between the above numerical ranges that are not listed. Due to space limitations and for the sake of simplicity, the present utility model does not exhaustively list the specific point values included in the said range.
[0060] Compared with the prior art, the present utility model has the following beneficial effects:
[0061] The present utility model realizes the modification of the bonding interface by laminating a polysilicon layer, a SiO2 layer, and a silicon oxide layer between the support substrate and the piezoelectric material layer, effectively improving the admittance ratio and response ability of the device. Description of the Drawings
[0062] Figure 1 It is a schematic structural diagram of the composite piezoelectric substrate provided in Embodiment 1 of the present utility model.
[0063] Figure 2 It is a schematic structural diagram of the precursor of the composite piezoelectric substrate provided in Embodiment 1 of the present utility model.
[0064] Figure 3 It is a schematic structural diagram of the composite piezoelectric substrate for a resonator provided by the present utility model.
[0065] Figure 4 It is a curve showing the influence of the thickness of the silicon oxide layer on the electromechanical coupling coefficient of the resonator provided by the present utility model.
[0066] Figure 5 It is a curve showing the influence of the thickness of the silicon oxide layer on the center frequency of the resonator provided by the present utility model.
[0067] Figure 6 It is a curve showing the influence of the thickness of the silicon oxide layer on the admittance ratio of the resonator provided by the present utility model.
[0068] Among them, 1 - high-resistance silicon substrate; 2 - polysilicon layer; 3 - SiO2 layer; 4 - silicon oxide layer; 5 - piezoelectric material layer; 6 - amorphous silicon layer; 7 - Al film. Detailed Embodiments
[0069] The technical solution of the present utility model will be further described below through specific embodiments. Those skilled in the art should understand that the said embodiments are only for helping to understand the present utility model and should not be regarded as specific limitations to the present utility model.
[0070] Embodiment 1
[0071] This embodiment provides a composite piezoelectric substrate, as Figure 1 shown, the composite piezoelectric substrate includes a high-resistance silicon substrate 1, a polysilicon layer 2, a SiO2 layer 3, a silicon oxide layer 4, and a piezoelectric material layer 5 that are sequentially laminated;
[0072] The atomic ratio of O to Si in the silicon oxide layer 4 is 0.35:1, and the thickness of the silicon oxide layer is 15 nm;
[0073] The resistivity of the high-resistance silicon substrate 1 is 3000 Ω·m;
[0074] The thickness of the polysilicon layer 2 is 1 μm, the thickness of the SiO2 layer 3 is 500 nm, and the piezoelectric material layer 4 is a lithium tantalate layer with a thickness of 0.6 μm.
[0075] This embodiment also provides a method for preparing the above composite piezoelectric substrate, and the preparation method includes the following steps:
[0076] (1) Deposit a polysilicon source layer on one side surface of a 6-inch high-resistance silicon substrate 1, and then thermally oxidize the surface layer of the polysilicon source layer at a temperature of 900 °C to form a SiO2 layer 3;
[0077] Perform hydrogen ion implantation on the bonding surface to be bonded of a 6-inch piezoelectric material donor, the depth of hydrogen ion implantation is 1 μm, and the ion implantation dose is 7.5×10 16 Ions / cm 2 , to form a damaged layer;
[0078] (2) In a vacuum environment, prepare a bonded body with a structure of high-resistance silicon substrate 1 / polysilicon layer / SiO2 layer / amorphous silicon layer / piezoelectric material donor in the following manner, including:
[0079] Deposit an amorphous silicon layer with a thickness of 15 nm on the side surface of the SiO2 layer away from the high-resistance silicon substrate 1, and then bond the bonding surface to be bonded of the piezoelectric material donor and the surface on the amorphous silicon layer side of the high-resistance silicon substrate 1, and the bonding pressure is 50 KN;
[0080] (3) Thin the non-bonding surface of the piezoelectric material donor in the bonded body so that the thickness of the piezoelectric material donor is 15 μm, and then perform a cleavage process at 230 °C for 5 h, so that the bonded body cracks along the damaged layer to obtain a composite piezoelectric substrate precursor and a residue layer as shown in Figure 2 , the composite piezoelectric substrate precursor includes a high-resistance silicon substrate 1, a polysilicon layer 2, a SiO2 layer 3, an amorphous silicon layer 6, and a piezoelectric material layer 5 stacked in sequence;
[0081] Then raise the temperature to 450 °C, introduce an oxygen source with a flow rate of 8 slm, and perform oxygen diffusion along the cleavage surface of the composite piezoelectric substrate precursor. The constant temperature time of oxygen diffusion is 6 h, and the oxygen diffuses into the amorphous silicon layer to transform the amorphous silicon layer into a silicon oxide layer, thereby obtaining the composite piezoelectric substrate.
[0082] Example 2
[0083] This embodiment provides a composite piezoelectric substrate, which includes a high-resistance silicon substrate, a polysilicon layer, a SiO2 layer, a silicon oxide layer, and a piezoelectric material layer that are sequentially stacked;
[0084] The atomic ratio of O to Si in the silicon oxide layer is 0.2:1, and the thickness of the silicon oxide layer is 25 nm;
[0085] The resistivity of the high-resistance silicon substrate is 3000 Ω·m;
[0086] The thickness of the polysilicon layer is 1.5 μm, the thickness of the SiO2 layer is 0.5 μm, and the piezoelectric material layer is a lithium tantalate layer with a thickness of 1.2 μm.
[0087] This embodiment also provides a preparation method for the above composite piezoelectric substrate, and the preparation method includes the following steps:
[0088] (1) Deposit a polysilicon source layer on one side surface of a 6-inch high-resistance silicon substrate, and then thermally oxidize the surface layer of the polysilicon source layer at a temperature of 920 °C to form a SiO2 layer;
[0089] Perform hydrogen ion implantation on the bonding surface to be bonded of a 6-inch piezoelectric material donor. The depth of hydrogen ion implantation is 0.5 μm, and the ion implantation dose is 7×10 16 Ions / cm 2 to form a damaged layer;
[0090] (2) In a vacuum environment, prepare a bonded body with a structure of high-resistance silicon substrate / polysilicon layer / SiO2 layer / amorphous silicon layer / piezoelectric material donor in the following manner, including:
[0091] Deposit an amorphous silicon layer with a thickness of 25 nm on the bonding surface to be bonded of the piezoelectric material donor, and then bond the side surface of the amorphous silicon layer on the piezoelectric material donor to the side surface of the SiO2 layer on the high-resistance silicon substrate. The bonding pressure is 50 KN;
[0092] (3) Thin the non-bonding surface of the piezoelectric material donor in the bonded body so that the thickness of the piezoelectric material donor is 30 μm, and then perform a splitting process at 180 °C for 10 h, so that the bonded body splits along the damaged layer to obtain a composite piezoelectric substrate precursor and a residual mass layer;
[0093] Then raise the temperature to 500 °C, introduce an oxygen source with a flow rate of 8 slm, and perform oxygen diffusion along the split surface of the composite piezoelectric substrate precursor. The constant temperature time for oxygen diffusion is 5 h, and diffuse into the amorphous silicon layer to convert the amorphous silicon layer into a silicon oxide layer to obtain the composite piezoelectric substrate.
[0094] Example 3
[0095] This embodiment provides a composite piezoelectric substrate, which includes a spinel substrate, a polysilicon layer, a SiO2 layer, a silicon oxide layer, and a piezoelectric material layer stacked in sequence;
[0096] The atomic ratio of O to Si in the silicon oxide layer is 0.5:1, and the thickness of the silicon oxide layer is 3 nm;
[0097] The density of the spinel substrate is 3.6 g / cm 3 ;
[0098] The thickness of the polysilicon layer is 1 μm, the thickness of the SiO2 layer is 0.5 μm, and the piezoelectric material layer is a lithium tantalate layer with a thickness of 1 μm.
[0099] This embodiment also provides a preparation method of the above composite piezoelectric substrate, and the preparation method includes the following steps:
[0100] (1) Deposit a polysilicon source layer on one side surface of a 6-inch spinel substrate, and then perform thermal oxidation treatment on the surface layer of the polysilicon source layer at a temperature of 920 °C to form a SiO2 layer;
[0101] Perform hydrogen ion implantation on the bonding surface to be bonded of a 6-inch piezoelectric material donor. The depth of hydrogen ion implantation is 1.5 μm, and the ion implantation dose is 9×10 16 Ions / cm 2 , to form a damaged layer;
[0102] (2) In a vacuum environment, prepare a bonded body with a structure of spinel substrate / polysilicon layer / SiO2 layer / amorphous silicon layer / piezoelectric material donor in the following manner, including:
[0103] Deposit a first sub-amorphous silicon layer on the surface of the SiO2 layer away from the spinel substrate, and deposit a second sub-amorphous silicon layer on the bonding surface to be bonded of the piezoelectric material donor. The total thickness of the first sub-amorphous silicon layer and the second sub-amorphous silicon layer is 1 nm, and then bond the surface of the second sub-amorphous silicon layer side on the piezoelectric material donor with the surface of the first sub-amorphous silicon layer side on the spinel substrate, and the bonding pressure is 50 KN;
[0104] (3) Thin the non-bonding surface of the piezoelectric material donor in the bonded body so that the thickness of the piezoelectric material donor is 10 μm, and then perform a cleaving process at 220 °C for 0.5 h, so that the bonded body splits along the damaged layer to obtain a composite piezoelectric substrate precursor and a residual mass layer;
[0105] Then, the temperature is raised to 550 °C, an oxygen source with a flow rate of 10 slm is introduced, and oxygen diffusion is carried out along the cleavage plane of the composite piezoelectric substrate precursor. The constant temperature time for oxygen diffusion is 4 h. The oxygen diffuses into the amorphous silicon layer to convert the amorphous silicon layer into a silicon oxide layer, and the composite piezoelectric substrate is obtained.
[0106] Example 4
[0107] The difference between this example and Example 1 is that the thickness of the silicon oxide layer is 5 nm.
[0108] The remaining preparation methods and parameters are the same as those in Example 1.
[0109] Example 5
[0110] The difference between this example and Example 1 is that the thickness of the silicon oxide layer is 6 nm.
[0111] The remaining preparation methods and parameters are the same as those in Example 1.
[0112] Example 6
[0113] The difference between this example and Example 1 is that the thickness of the silicon oxide layer is 7 nm.
[0114] The remaining preparation methods and parameters are the same as those in Example 1.
[0115] Example 7
[0116] The difference between this example and Example 1 is that the thickness of the silicon oxide layer is 8 nm.
[0117] The remaining preparation methods and parameters are the same as those in Example 1.
[0118] Example 8
[0119] The difference between this example and Example 1 is that the thickness of the silicon oxide layer is 9 nm.
[0120] The remaining preparation methods and parameters are the same as those in Example 1.
[0121] Example 9
[0122] The difference between this example and Example 1 is that the thickness of the silicon oxide layer is 10 nm.
[0123] The remaining preparation methods and parameters are the same as those in Example 1.
[0124] Example 10
[0125] The difference between this example and Example 1 is that the thickness of the silicon oxide layer is 20 nm.
[0126] The remaining preparation methods and parameters are the same as those in Example 1.
[0127] Example 11
[0128] The difference between this example and Example 1 is that the thickness of the silicon oxide layer is 5 nm and the annealing temperature is 550 °C.
[0129] The remaining preparation methods and parameters are the same as those in Example 1.
[0130] Example 12
[0131] The difference between this example and Example 1 is that the thickness of the silicon oxide layer is 10 nm and the annealing temperature is 550 °C.
[0132] The remaining preparation methods and parameters are the same as those in Example 1.
[0133] Example 13
[0134] The difference between this example and Example 1 is that the thickness of the silicon oxide layer is 30 nm.
[0135] The remaining preparation methods and parameters are the same as those in Example 1.
[0136] Example 14
[0137] The difference between this example and Example 1 is that the temperature of the oxygen diffusion in step (3) is 400 °C.
[0138] The remaining preparation methods and parameters are the same as those in Example 1.
[0139] Example 15
[0140] The difference between this example and Example 1 is that the temperature of the oxygen diffusion in step (3) is 600 °C.
[0141] The remaining preparation methods and parameters are the same as those in Example 1.
[0142] Comparative Example 1
[0143] The difference between this comparative example and Example 1 is that no silicon oxide layer is provided, that is, the amorphous silicon layer is not deposited in step (2).
[0144] The remaining preparation methods and parameters are the same as those in Example 1.
[0145] Comparative Example 2
[0146] The difference between this comparative example and Example 1 is that no oxygen diffusion treatment is performed in step (3), that is, the amorphous silicon layer is not converted.
[0147] The remaining preparation methods and parameters are the same as those in Example 1.
[0148] Comparative Example 3
[0149] The difference between this comparative example and Example 1 is that by adjusting the parameters of oxygen diffusion, the atomic ratio of O to Si in the silicon oxide layer is 0.1:1.
[0150] The remaining preparation methods and parameters are the same as those in Example 1.
[0151] Comparative Example 4
[0152] The difference between this comparative example and Example 1 is that by adjusting the parameters of oxygen diffusion, the atomic ratio of O to Si in the silicon oxide layer is 1:1.
[0153] The remaining preparation methods and parameters are the same as those in Example 1.
[0154] Comparative Example 5
[0155] The difference between this comparative example and Example 1 is that in step (3), the oxygen diffusion process is replaced by an oxygen ion implantation process.
[0156] The remaining preparation methods and parameters are the same as those in Example 1.
[0157] Performance Test
[0158] I. The composite piezoelectric substrates prepared in the above examples and comparative examples are made into resonators, and then filters are formed. As Figure 3 shown, the resonator includes a high-resistance silicon substrate 1, a polysilicon layer 2, a SiO2 layer 3, a silicon oxide layer 4, and a piezoelectric material layer 5 stacked in sequence, and an Al film 7 with a thickness of 160 nm is provided on the surface of the piezoelectric material layer 5.
[0159] The electromechanical coupling coefficient (K 2 ), center frequency (fc), and admittance ratio (AR) of the above resonator are tested.
[0160] The test results are as Figure 4 , Figure 5 , Figure 6 and Table 1 show.
[0161] As can be seen from Figures 4-6 , the composite piezoelectric substrate provided by the present invention has no influence on the electromechanical coupling coefficient and center frequency of the resonator, and the admittance ratio of the resonator increases with the increase of the thickness.
[0162] Table 1
[0163]
[0164]
[0165] Analysis:
[0166] As can be seen from the above table, the composite piezoelectric substrate provided by the present utility model realizes the modification of the bonding interface, effectively improving the admittance ratio and response ability of the device. Moreover, when the thickness of the silicon oxide layer ≤ 20 nm, it has no influence on the electromechanical coupling coefficient of the resonator, no influence on the center frequency of the resonator, and the admittance ratio of the resonator increases with the increase of the thickness.
[0167] As can be seen from Example 1 and Example 13, if the thickness of the silicon oxide layer is too large, it will cause the admittance ratio not to be further improved and the cost to increase.
[0168] As can be seen from Example 1 and Examples 14 - 15, if the temperature of the oxygen diffusion in step (3) is too low, the piezoelectric wafer cannot be effectively repaired; if the temperature of the oxygen diffusion in step (3) is too high, the piezoelectric performance of the piezoelectric wafer will decrease.
[0169] As can be seen from Example 1 and Comparative Example 1, if the silicon oxide layer is not provided and the piezoelectric material layer and the SiO2 layer are directly bonded, the admittance ratio of the resonator will decrease.
[0170] As can be seen from Example 1 and Comparative Example 2, if the amorphous silicon layer is not converted, the resonator K 2 will decrease.
[0171] As can be seen from Example 1 and Comparative Examples 3 - 4, if the atomic ratio of O and Si in the silicon oxide layer is too small, the K 2 will decrease; if the atomic ratio of O and Si in the silicon oxide layer is too large, the admittance ratio will decrease.
[0172] As can be seen from Example 1 and Comparative Example 5, if the oxygen diffusion process is replaced with an oxygen ion implantation process, the crystal structure in the piezoelectric material layer will be damaged, resulting in a decline in device performance.
[0173] The applicant declares that the present utility model uses the above - mentioned embodiments to illustrate the process method of the present utility model, but the present utility model is not limited to the above - mentioned process steps, that is, it does not mean that the present utility model must rely on the above - mentioned process steps to be implemented. Those skilled in the art should understand that any improvement to the present utility model, the equivalent substitution of the raw materials selected by the present utility model, the addition of auxiliary components, the selection of specific methods, etc., all fall within the protection scope and the disclosure scope of the present utility model.
Claims
1. A composite piezoelectric substrate, characterized in that, The composite piezoelectric substrate includes a support substrate, a polysilicon layer, a SiO2 layer, a silicon oxide layer, and a piezoelectric material layer that are sequentially stacked; The atomic ratio of O to Si in the silicon oxide layer is (0.2-0.5):
1.
2. The composite piezoelectric substrate according to claim 1, wherein, The thickness of the silicon oxide layer is 1-25 nm.
3. The composite piezoelectric substrate according to claim 2, characterized in that, The thickness of the silicon oxide layer is 3-15 nm.
4. The composite piezoelectric substrate according to claim 1, wherein The support substrate is a silicon layer; The resistivity of the silicon layer > 1000 Ω·m.
5. The composite piezoelectric substrate according to claim 1, wherein, The support substrate is spinel; The density of the spinel ≥ 3.58 g / cm 3 .
6. The composite piezoelectric substrate according to claim 1, characterized in that, The thickness of the polysilicon layer is 500-3000 nm.
7. The composite piezoelectric substrate according to claim 1, wherein The thickness of the SiO2 layer is 500-3000 nm.
8. The composite piezoelectric substrate according to claim 1, characterized in that, The piezoelectric material layer is a lithium niobate layer or a lithium tantalate layer.
9. The composite piezoelectric substrate according to claim 1, characterized in that, The thickness of the piezoelectric material layer is 0.4-1.2 μm.
10. A resonator, characterized in that, The resonator includes the composite piezoelectric substrate according to any one of claims 1-9.