Miniature static electricity eliminator

Abstract

The utility model discloses a miniature static electricity eliminator. The eliminator comprises an ADC sampling circuit, a high-voltage positive adjusting circuit and a high-voltage negative adjusting circuit. The ADC sampling circuit, the high-voltage positive adjusting circuit and the high-voltage negative adjusting circuit are all arranged on the circuit board. The high-voltage positive regulation circuit is connected with a PWM1 port of the second MCU processor, and the high-voltage positive regulation circuit regulates a collected positive voltage signal in real time through the second MCU processor; the high-voltage negative regulation circuit is connected with a PWM2 port of the second MCU processor, and the high-voltage negative regulation circuit adjusts the collected negative voltage signal in real time through the second MCU processor. According to the miniature static electricity eliminator, closed-loop control is adopted, super-strong static electricity elimination performance can be maintained, and ion balance voltage can be adjusted manually. And invisible static electricity is effectively eliminated, so that the original relatively fuzzy static electricity countermeasure becomes clearer and more reliable.

Description

Technical Field

[0001] The utility model relates to the technical field of static elimination, and particularly relates to a micro static eliminator. Background Art

[0002] Due to the friction, peeling, extrusion, induction, etc. between articles and materials during production, different static charges exist on the surface of objects. When the surface charge of an object accumulates to a certain extent, static adsorption and static discharge phenomena will occur.

[0003] Static discharge can cause great damage to products and industrial equipment. For example, static adsorption makes it difficult to remove the cleanliness of items such as display screens and laser heads. Static discharge can cause breakdown or soft breakdown of sensitive devices and products, thereby greatly reducing the performance and quality of products, resulting in a poor consumption experience for customers. Static discharge is also extremely harmful to industrial equipment.

[0004] In view of this, it is necessary to develop a static eliminator to effectively neutralize static electricity and prevent hazards from occurring. Summary of the Utility Model

[0005] Aiming at the deficiencies in the prior art, the technical problem to be solved by the utility model is to provide a micro static eliminator. The purpose of designing this static eliminator is to eliminate static electricity and prevent hazards.

[0006] To solve the above technical problems, the utility model is realized through the following solutions: A micro static eliminator of the utility model, which has a dual-chip control circuit, including a first MCU processor and a second MCU processor. The eliminator further includes:

[0007] An ADC sampling circuit, which is electrically connected to the ADC port of the second MCU processor. It senses the positive and negative ion voltages of the induction plasma generator and feeds the sampled voltage back to the second MCU processor in real time by using two-stage amplification.

[0008] A high-voltage positive regulation circuit, which is connected to the PWM1 port of the second MCU processor. This high-voltage positive regulation circuit adjusts the collected positive voltage signal in real time through the second MCU processor.

[0009] A high-voltage negative regulation circuit, which is connected to the PWM2 port of the second MCU processor. This high-voltage negative regulation circuit adjusts the collected negative voltage signal in real time through the second MCU processor.

[0010] Further, the second MCU processor uses a single-chip microcomputer of the STM32 series.

[0011] Further, the ADC sampling circuit includes operational amplifier U1A, operational amplifier U1B, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, capacitor C1, capacitor C2, capacitor C3, diode D1, diode D2, capacitor C1, capacitor C2, and capacitor C3;

[0012] The resistors R1, R2, and R3 are connected in series to form a series circuit. The first end of the series circuit is connected to a first voltage, and the second end of the series circuit is grounded. The first end of the capacitor C1 is connected to the non-inverting input terminal of the operational amplifier U1A, and the second end of the capacitor C1 is connected to the grounded end of the series circuit;

[0013] The non-inverting input terminal of the operational amplifier U1A is also connected to the circuit node between the resistors R2 and R3;

[0014] The inverting input terminal of the operational amplifier U1A is respectively connected to the first end of the resistor R4, the positive electrode of the diode D1, the negative electrode of the diode D2, and the second end of the resistor R6;

[0015] The second end of the resistor R4 is connected to the first end of the capacitor C2 and the second pin of the socket P2. The second end of the capacitor C2 is grounded, and the first pin of the socket P2 is grounded;

[0016] The negative electrode of the diode D1 is connected to the first voltage, and the positive electrode of the diode D2 is grounded;

[0017] The first end of the resistor R6 is connected to the output terminal of the operational amplifier U1A, and the capacitor C3 is connected in parallel with the resistor R6;

[0018] The first power supply pin of the operational amplifier U1A is connected to the first voltage, and the second power supply pin of the operational amplifier U1A is grounded;

[0019] The non-inverting input terminal of the operational amplifier U1B is connected to the output terminal of the operational amplifier U1A;

[0020] The inverting input terminal of the operational amplifier U1B is respectively connected to the first end of the resistor R5 and the second end of the resistor R7. The second end of the resistor R5 is grounded, and the first end of the resistor R7 is connected to the output terminal of the operational amplifier U1B. The output terminal of the operational amplifier U1B is connected to the ADC port of the second MCU processor.

[0021] Further, the first voltage is +3.3V.

[0022] Further, the high-voltage positive regulation circuit includes operational amplifier U2A, resistor R8, resistor R9, resistor R10, resistor R11, polarized capacitor C4, capacitor C5, diode D3, diode D4, and first voltage regulator U3;

[0023] The non-inverting input terminal of the operational amplifier U2A is connected to the first terminal of resistor R10 and the first terminal of capacitor C5. The second terminal of resistor R10 is connected to the PWM1 port of the second MCU processor, and the second terminal of capacitor C5 is grounded;

[0024] The inverting input terminal of the operational amplifier U2A is respectively connected to the first terminal of resistor R9 and the second terminal of resistor R8. The second terminal of resistor R9 is grounded, and the first terminal of resistor R8 is connected to the output terminal of the operational amplifier U2A;

[0025] The first power supply pin of the operational amplifier U2A is connected to the second voltage, and the second power supply pin of the operational amplifier U2A is grounded;

[0026] The output terminal of the operational amplifier U2A is respectively connected to the ADJ pin of the first voltage regulator U3, the first terminal of resistor R11, and the positive electrode of diode D4;

[0027] The Vin pin of the first voltage regulator U3 is connected to the negative electrode of diode D3 and the second voltage. The positive electrode of diode D3 is connected to the Vout pin of the first voltage regulator U3. The Vout pin of the first voltage regulator U3 is also respectively connected to the second terminal of resistor R11, the negative electrode of diode D4, and the positive electrode of polarized capacitor C4. The negative electrode of polarized capacitor C4 is grounded;

[0028] The Vout pin of the first voltage regulator U3 is also connected to the HV+ port;

[0029] The high-voltage negative regulation circuit includes operational amplifier U2B, resistor R12, resistor R14, resistor R16, resistor R17, polarized capacitor C11, capacitor C12, diode D5, diode D7, and second voltage regulator U4;

[0030] The non-inverting input terminal of the operational amplifier U2B is connected to the first terminal of resistor R16 and the first terminal of capacitor C12. The second terminal of resistor R16 is connected to the PWM2 port of the second MCU processor, and the second terminal of capacitor C12 is grounded;

[0031] The inverting input terminal of the operational amplifier U2B is respectively connected to the first terminal of resistor R14 and the second terminal of resistor R12. The second terminal of resistor R14 is grounded, and the first terminal of resistor R12 is connected to the output terminal of the operational amplifier U2B;

[0032] The output terminal of the operational amplifier U2B is respectively connected to the ADJ pin of the second voltage regulator U4, the first end of the resistor R17, and the positive electrode of the diode D7;

[0033] The Vin pin of the second voltage regulator U4 is connected to the negative electrode of the diode D5 and the second voltage. The positive electrode of the diode D5 is connected to the Vout pin of the second voltage regulator U4. The Vout pin of the second voltage regulator U4 is also respectively connected to the second end of the resistor R17, the negative electrode of the diode D7, and the positive electrode of the polarized capacitor C11. The negative electrode of the polarized capacitor C11 is grounded;

[0034] The Vout pin of the second voltage regulator U4 is also connected to the HV - port.

[0035] Furthermore, the second voltage is +24V.

[0036] Furthermore, the first voltage regulator U3 is a DC adjustable voltage regulator.

[0037] Furthermore, the second voltage regulator U4 is a DC adjustable voltage regulator.

[0038] Compared with the prior art, the beneficial effects of the present utility model are as follows:

[0039] 1. The micro static eliminator of the present utility model effectively improves the harm of static electricity to products and improves product quality.

[0040] 2. The ADC sampling circuit of the present utility model senses the positive and negative ion voltages of the induction plasma generator, and uses two - stage amplification to feedback the sampled voltage to the second MCU processor in real time to realize the real - time monitoring of the positive and negative ion voltages and make a comparison for subsequent positive and negative voltage adjustment.

[0041] 3. The micro static eliminator of the present utility model adopts closed - loop control, can maintain super - strong static elimination performance (within the range of the highest ion balance voltage of plus or minus 10V, the fastest static elimination speed of 0.3 seconds - 2 seconds, and the best test distance of 5CM - 30CM), and can manually adjust the ion balance voltage. It effectively eliminates invisible static electricity and makes the original relatively vague static electricity countermeasures clearer and more reliable. Description of the Drawings

[0042] Figure 1 It is the principle block diagram of the dual - chip control of the present utility model.

[0043] Figure 2 It is the circuit diagram of the second MCU processor of the present utility model.

[0044] Figure 3 It is the ADC sampling circuit diagram of the present utility model.

[0045] Figure 4This is the high-voltage positive regulation circuit diagram of the present utility model.

[0046] Figure 5 This is the high-voltage negative regulation circuit diagram of the present utility model.

[0047] Figure 6 This is the circuit diagram of the first MCU processor of the present utility model.

[0048] Reference signs in the drawings: the first MCU processor 1, the ADC sampling circuit 2, the high-voltage positive regulation circuit 3, the high-voltage negative regulation circuit 4, the second MCU processor 5. Detailed implementation manners

[0049] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the drawings in the embodiments of the present utility model, so that the advantages and features of the present utility model can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present utility model. Obviously, the embodiments described in the present utility model are only a part of the embodiments of the present utility model, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.

[0050] In addition, the technical features involved in different implementation manners of the present utility model described below can be combined with each other as long as they do not conflict with each other.

[0051] Embodiment 1: The specific structure of the present utility model is as follows:

[0052] Please refer to the attached Figures 1-5 , a micro static eliminator of the present utility model, the micro static eliminator is provided with a circuit board, and a dual-core control circuit is provided on the circuit board. The micro static eliminator includes a first MCU processor 1 and a second MCU processor 5. The eliminator further includes an ADC sampling circuit 2, a high-voltage positive regulation circuit 3, and a high-voltage negative regulation circuit 4. The ADC sampling circuit 2, the high-voltage positive regulation circuit 3, and the high-voltage negative regulation circuit 4 are all arranged on the circuit board. The high-voltage positive regulation circuit 3 is connected to the PWM1 port of the second MCU processor 5, and the high-voltage positive regulation circuit 3 adjusts the collected positive voltage signal in real time through the second MCU processor 5; the high-voltage negative regulation circuit 4 is connected to the PWM2 port of the second MCU processor 5, and the high-voltage negative regulation circuit 4 adjusts the collected negative voltage signal in real time through the second MCU processor 5. Preferably, the model of the first MCU processor 1 is the STC12C5A60S2-35I-LQFP48 processor. The second MCU processor 5 uses a single-chip microcomputer of the STM32 series. Preferably, the model of the second MCU processor 5 is STM32G030F6P6.

[0053] As Figure 3 shown, the ADC sampling circuit 2 is electrically connected to the ADC port of the second MCU processor 5. It senses the positive and negative ion voltages of the induction plasma generator and uses two-stage amplification to feedback the sampled voltage to the second MCU processor in real time. The ADC sampling circuit 2 includes operational amplifier U1A, operational amplifier U1B, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, capacitor C1, capacitor C2, capacitor C3, diode D1, diode D2, capacitor C1, capacitor C2, and capacitor C3;

[0054] The resistors R1, R2, and R3 are connected in series to form a series circuit. The first end of the series circuit is connected to a first voltage, and the second end of the series circuit is grounded. The first end of the capacitor C1 is connected to the non-inverting input terminal of the operational amplifier U1A, and the second end of the capacitor C1 is connected to the grounded end of the series circuit;

[0055] The non-inverting input terminal of the operational amplifier U1A is also connected to the circuit node between the resistors R2 and R3;

[0056] The inverting input terminal of the operational amplifier U1A is respectively connected to the first end of the resistor R4, the positive electrode of the diode D1, the negative electrode of the diode D2, and the second end of the resistor R6;

[0057] The second end of the resistor R4 is connected to the first end of the capacitor C2 and the 2nd pin of the socket P2. The second end of the capacitor C2 is grounded, and the 1st pin of the socket P2 is grounded;

[0058] The negative electrode of the diode D1 is connected to the first voltage, and the positive electrode of the diode D2 is grounded;

[0059] The first end of the resistor R6 is connected to the output terminal of the operational amplifier U1A, and the capacitor C3 is in parallel with the resistor R6;

[0060] The first power supply pin of the operational amplifier U1A is connected to the first voltage, and the second power supply pin of the operational amplifier U1A is grounded;

[0061] The non-inverting input terminal of the operational amplifier U1B is connected to the output terminal of the operational amplifier U1A;

[0062] The inverting input terminal of the operational amplifier U1B is respectively connected to the first end of the resistor R5 and the second end of the resistor R7. The second end of the resistor R5 is grounded, and the first end of the resistor R7 is connected to the output terminal of the operational amplifier U1B. The output terminal of the operational amplifier U1B is connected to the ADC port of the second MCU processor 5.

[0063] The first voltage is +3.3V.

[0064] The high-voltage positive regulation circuit 3 includes an operational amplifier U2A, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a polarized capacitor C4, a capacitor C5, a diode D3, a diode D4, and a first voltage regulator U3;

[0065] The non-inverting input terminal of the operational amplifier U2A is connected to the first terminal of the resistor R10 and the first terminal of the capacitor C5. The second terminal of the resistor R10 is connected to the PWM1 port of the second MCU processor 5. The second terminal of the capacitor C5 is grounded;

[0066] The inverting input terminal of the operational amplifier U2A is respectively connected to the first terminal of the resistor R9 and the second terminal of the resistor R8. The second terminal of the resistor R9 is grounded. The first terminal of the resistor R8 is connected to the output terminal of the operational amplifier U2A;

[0067] The first power supply pin of the operational amplifier U2A is connected to the second voltage, and the second power supply pin of the operational amplifier U2A is grounded;

[0068] The output terminal of the operational amplifier U2A is respectively connected to the ADJ pin of the first voltage regulator U3, the first terminal of the resistor R11, and the positive electrode of the diode D4;

[0069] The Vin pin of the first voltage regulator U3 is connected to the negative electrode of the diode D3 and the second voltage. The positive electrode of the diode D3 is connected to the Vout pin of the first voltage regulator U3. The Vout pin of the first voltage regulator U3 is also respectively connected to the second terminal of the resistor R11, the negative electrode of the diode D4, and the positive electrode of the polarized capacitor C4. The negative electrode of the polarized capacitor C4 is grounded;

[0070] The Vout pin of the first voltage regulator U3 is also connected to the HV+ port;

[0071] The high-voltage negative regulation circuit 4 includes an operational amplifier U2B, a resistor R12, a resistor R14, a resistor R16, a resistor R17, a polarized capacitor C11, a capacitor C12, a diode D5, a diode D7, and a second voltage regulator U4;

[0072] The non-inverting input terminal of the operational amplifier U2B is connected to the first terminal of the resistor R16 and the first terminal of the capacitor C12. The second terminal of the resistor R16 is connected to the PWM2 port of the second MCU processor 5. The second terminal of the capacitor C12 is grounded;

[0073] The inverting input terminal of the operational amplifier U2B is respectively connected to the first terminal of the resistor R14 and the second terminal of the resistor R12. The second terminal of the resistor R14 is grounded. The first terminal of the resistor R12 is connected to the output terminal of the operational amplifier U2B;

[0074] The output terminal of the operational amplifier U2B is respectively connected to the ADJ pin of the second voltage regulator U4, the first end of the resistor R17, and the positive electrode of the diode D7;

[0075] The Vin pin of the second voltage regulator U4 is connected to the negative electrode of the diode D5 and the second voltage. The positive electrode of the diode D5 is connected to the Vout pin of the second voltage regulator U4. The Vout pin of the second voltage regulator U4 is also respectively connected to the second end of the resistor R17, the negative electrode of the diode D7, and the positive electrode of the polarized capacitor C11. The negative electrode of the polarized capacitor C11 is grounded;

[0076] The Vout pin of the second voltage regulator U4 is also connected to the HV - port.

[0077] The second voltage is +24V.

[0078] Both the first voltage regulator U3 and the second voltage regulator U4 are DC adjustable voltage regulators. Preferably, the model of the DC adjustable voltage regulator is LM3176.

[0079] Figures 3-5 In the ADC sampling circuit 2 of the present invention, two groups of operational amplifiers are adopted. The sampled voltage is fed back to the second MCU processor 5 in real - time through the two groups of operational amplifiers. The second MCU processor 5 compares the fed - back voltage signal with the parameters set inside the second MCU processor 5 to determine whether the positive and negative ion voltages of the plasma generator are within the parameter range. If the positive and negative ion voltages of the plasma generator are not within the range, then according to the magnitude of the value, as well as the positive voltage signal collected by the high - voltage positive regulation circuit 3 and the negative voltage signal collected by the high - voltage negative regulation circuit 4, the second MCU processor 5 controls the operation of the plasma generator. Since the plasma generator generates abundant positive and negative charges, the positive and negative charges in the air are blown onto the object surface by the fan, so that the static ions of the object are neutralized and the static electricity is eliminated.

[0080] Through the circuit design of the present invention, the static eliminator of the present invention can reduce the volume.

[0081] Such as Figure 1 、 Figure 6 As shown, the first MCU processor 1 of the present invention is also respectively connected to an infrared circuit, a fan control circuit, and an LED display circuit. The LED display circuit has 7 - level displays for the magnitude of the fan output air volume. The infrared circuit is equipped with an external remote control to control the air volume output of the fan.

[0082] In summary, the micro static eliminator of the present utility model effectively improves the harm of static electricity to products and enhances product quality. The ADC sampling circuit of the present utility model senses the positive and negative ion voltages of the induction plasma generator and uses two-stage amplification to feedback the sampled voltage to the second MCU processor in real time, so as to achieve real-time monitoring of the positive and negative ion voltages and make a comparison for subsequent adjustment of positive and negative voltages. The micro static eliminator of the present utility model adopts closed-loop control, can maintain super strong static elimination performance (the maximum ion balance voltage is within ±10V, the fastest static elimination speed is 0.3 seconds - 2 seconds, and the best test distance is 5CM - 30CM), and can manually adjust the ion balance voltage. It effectively eliminates invisible static electricity and makes the original relatively vague static electricity countermeasures clearer and more reliable.

[0083] The above are only the preferred embodiments of the present utility model, and do not limit the patent scope of the present utility model. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present utility model, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of the present utility model.

Claims

1. Miniature static eliminator, the eliminator has a dual-chip control circuit, including a first MCU processor (1) and a second MCU processor (5), characterized in that, The eliminator further includes: An ADC sampling circuit (2), which is electrically connected to the ADC port of the second MCU processor (5). It senses the positive and negative ion voltages of the induction plasma generator and uses two-stage amplification to feedback the sampled voltage to the second MCU processor in real time. A high-voltage positive regulation circuit (3), which is connected to the PWM1 port of the second MCU processor (5). This high-voltage positive regulation circuit (3) adjusts the collected positive voltage signal in real time through the second MCU processor (5). A high-voltage negative regulation circuit (4), which is connected to the PWM2 port of the second MCU processor (5). This high-voltage negative regulation circuit (4) adjusts the collected negative voltage signal in real time through the second MCU processor (5).

2. The micro static eliminator according to claim 1, wherein, The second MCU processor (5) uses a single-chip microcomputer of the STM32 series.

3. The micro static eliminator according to claim 2, characterized in that, The ADC sampling circuit (2) includes operational amplifier U1A, operational amplifier U1B, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, capacitor C1, capacitor C2, capacitor C3, diode D1, diode D2, capacitor C1, capacitor C2, and capacitor C3. The resistors R1, R2, and R3 are connected in series to form a series circuit. The first end of the series circuit is connected to a first voltage, and the second end of the series circuit is grounded. The first end of the capacitor C1 is connected to the non-inverting input terminal of the operational amplifier U1A, and the second end of the capacitor C1 is connected to the grounded end of the series circuit. The non-inverting input terminal of the operational amplifier U1A is also connected to the circuit node between the resistors R2 and R3. The inverting input terminal of the operational amplifier U1A is respectively connected to the first end of the resistor R4, the positive electrode of the diode D1, the negative electrode of the diode D2, and the second end of the resistor R6. The second end of the resistor R4 is connected to the first end of the capacitor C2 and the 2nd pin of the socket P2. The second end of the capacitor C2 is grounded, and the 1st pin of the socket P2 is grounded. The negative electrode of the diode D1 is connected to the first voltage, and the positive electrode of the diode D2 is grounded. The first end of the resistor R6 is connected to the output terminal of the operational amplifier U1A, and the capacitor C3 is in parallel with the resistor R6. The first power supply pin of the operational amplifier U1A is connected to the first voltage, and the second power supply pin of the operational amplifier U1A is grounded. The non-inverting input terminal of the operational amplifier U1B is connected to the output terminal of the operational amplifier U1A. The inverting input terminal of the operational amplifier U1B is respectively connected to the first end of the resistor R5 and the second end of the resistor R7. The second end of the resistor R5 is grounded, the first end of the resistor R7 is connected to the output terminal of the operational amplifier U1B, and the output terminal of the operational amplifier U1B is connected to the ADC port of the second MCU processor (5).

4. The micro static eliminator according to claim 3, characterized in that, The first voltage is +3.3V.

5. The micro static eliminator according to claim 2, characterized in that, The high-voltage positive regulation circuit (3) includes operational amplifier U2A, resistor R8, resistor R9, resistor R10, resistor R11, polarized capacitor C4, capacitor C5, diode D3, diode D4, and first voltage regulator U3. The non-inverting input terminal of the operational amplifier U2A is connected to the first terminal of the resistor R10 and the first terminal of the capacitor C5. The second terminal of the resistor R10 is connected to the PWM1 port of the second MCU processor (5), and the second terminal of the capacitor C5 is grounded. The inverting input terminal of the operational amplifier U2A is respectively connected to the first terminal of the resistor R9 and the second terminal of the resistor R8. The second terminal of the resistor R9 is grounded, and the first terminal of the resistor R8 is connected to the output terminal of the operational amplifier U2A. The first power supply pin of the operational amplifier U2A is connected to the second voltage, and the second power supply pin of the operational amplifier U2A is grounded. The output terminal of the operational amplifier U2A is respectively connected to the ADJ pin of the first voltage regulator U3, the first terminal of the resistor R11, and the positive electrode of the diode D4. The Vin pin of the first voltage regulator U3 is connected to the negative electrode of the diode D3 and the second voltage. The positive electrode of the diode D3 is connected to the Vout pin of the first voltage regulator U3. The Vout pin of the first voltage regulator U3 is also respectively connected to the second terminal of the resistor R11, the negative electrode of the diode D4, and the positive electrode of the polarized capacitor C4. The negative electrode of the polarized capacitor C4 is grounded. The Vout pin of the first voltage regulator U3 is also connected to the HV+ port. The high-voltage negative regulation circuit (4) includes an operational amplifier U2B, a resistor R12, a resistor R14, a resistor R16, a resistor R17, a polarized capacitor C11, a capacitor C12, a diode D5, a diode D7, and a second voltage regulator U4. The non-inverting input terminal of the operational amplifier U2B is connected to the first terminal of the resistor R16 and the first terminal of the capacitor C12. The second terminal of the resistor R16 is connected to the PWM2 port of the second MCU processor (5), and the second terminal of the capacitor C12 is grounded. The inverting input terminal of the operational amplifier U2B is respectively connected to the first terminal of the resistor R14 and the second terminal of the resistor R12. The second terminal of the resistor R14 is grounded, and the first terminal of the resistor R12 is connected to the output terminal of the operational amplifier U2B. The output terminal of the operational amplifier U2B is respectively connected to the ADJ pin of the second voltage regulator U4, the first terminal of the resistor R17, and the positive electrode of the diode D7. The Vin pin of the second voltage regulator U4 is connected to the negative electrode of the diode D5 and the second voltage. The positive electrode of the diode D5 is connected to the Vout pin of the second voltage regulator U4. The Vout pin of the second voltage regulator U4 is also respectively connected to the second terminal of the resistor R17, the negative electrode of the diode D7, and the positive electrode of the polarized capacitor C11. The negative electrode of the polarized capacitor C11 is grounded. The Vout pin of the second voltage regulator U4 is also connected to the HV- port.

6. The micro static eliminator according to claim 5, characterized in that, The second voltage is +24V.

7. The micro static eliminator according to claim 5, characterized in that, The first voltage regulator U3 is a DC adjustable voltage regulator.

8. The micro static eliminator according to claim 5, characterized in that The second voltage regulator U4 is a DC adjustable voltage regulator.

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