Test fixture for Mipi C-PHY signals
By designing a test fixture for signal generators, FPGA processors and bridged integrated circuits, the problem that the Mipi D-PHY fixture cannot transmit C-PHY signals is solved, and the effective detection and stable transmission of C-PHY signals are realized, and the flexibility and cost-effectiveness of adapting to different needs is achieved.
Patent Information
- Application Number
- CN202421936354.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-12
- Publication Date
- 2025-07-18
- Estimated Expiration
- 2034-08-12
AI Technical Summary
The existing Mipi D-PHY test fixtures cannot effectively transmit C-PHY signals, resulting in the inability to effectively detect the screen, which may cause the screen to be off light or the screen to be abnormal.
A test fixture including a signal generator, a C-PHY signal box and a screen module is designed. The signal generator generates a high-speed differential bus signal, converts the signal into a C-PHY signal through an FPGA processor and a bridge integrated circuit. The screen module receives and detects the C-PHY signal, and the display driver chip converts the signal into a dot-screen signal to light up the screen body.
It realizes effective transmission and detection of C-PHY signals, adapts to the flexible replacement of different work sites and screen models, reduces production and management costs, and improves signal quality and stability.
Smart Images
Figure CN223123136U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of signal test fixtures, in particular to a test fixture for Mipi C-PHY signals. Background Art
[0002] At present, in the domestic and foreign display screen industries, especially for small and medium-sized mobile phone screens, tablet screens, wearable screens, etc., there is a trend towards higher screen resolutions and higher refresh rates. In this trend, the maximum transmission speed of Mipi D-PHY has tended to saturate; therefore, domestic and foreign display panel factories have begun to increase the production of Mipi C-PHY screens with a larger maximum transmission speed and fewer signal pins.
[0003] The maximum transmission speed of a single Lane of Mipi D-PHY is 2.5 Gbps. The D-PHY signal of 1 Link includes 4 Lane signals and 1 Lane clock, and the total number of pins is 10 Pin. The maximum transmission speed of the D-PHY signal of 1 Link is 10 Gbps.
[0004] The maximum transmission speed of a single Lane of Mipi C-PHY is 5.7 Gbps. The C-PHY signal of 1 Link includes 3 Lane signals, and the total number of pins is 9 Pin. The maximum transmission speed of the C-PHY signal of 1 Link is 17.1 Gbps.
[0005] Compared with Mipi D-PHY signals, the advantages of Mipi C-PHY signals are fewer signal pins and faster signal transmission speed. Reducing the number of pins of components in more product applications is more suitable for products with higher precision requirements; however, the disadvantage of Mipi C-PHY signals is that in order to ensure the stability of signal transmission quality, the Mipi Alliance stipulates that the maximum length of the C-PHY signal transmission line cannot exceed 175 mm, and in special cases (when the FPC wiring length inside the screen body reaches 100 mm), the length of the C-PHY signal transmission line cannot exceed 75 mm.
[0006] For traditional Mipi D-PHY test fixtures, the length of the D-PHY signal transmission line usually reaches or even exceeds 300 mm. Therefore, the architecture of traditional Mipi D-PHY test fixtures is not applicable to C-PHY test fixtures, so there is an urgent need to develop a convenient Mipi C-PHY signal test fixture with high signal quality.
[0007] In the traditional test fixture architecture, the length of the Mipi signal line usually reaches or even exceeds 300 mm, which obviously exceeds the length of the C-PHY signal transmission line specified by the Mipi Alliance. If the traditional test fixture architecture is applied to test the C-PHY screen body, there is a high probability that the C-PHY signal transmission will be abnormal, which will in turn cause abnormalities such as the C-PHY screen body not lighting up or the screen painting being abnormal when dotting the screen. Summary of the Invention
[0008] To this end, the technical problem to be solved by the present utility model is to overcome the problem that the Mipi D-PHY test fixture in the prior art cannot effectively transmit the C-PHY signal, and thus cannot effectively detect the screen body.
[0009] To solve the above technical problem, the present utility model provides a test fixture for Mipi C-PHY signals, which includes a signal generator, a C-PHY signal box, and a screen body module to be detected. The C-PHY signal box includes an FPGA processor and a bridge integrated circuit Bridge IC. The signal generator is connected to the FPGA processor in the C-PHY signal box. The FPGA processor is connected to the bridge integrated circuit Bridge IC. The bridge integrated circuit Bridge IC is connected to the screen body module.
[0010] The signal generator is used to generate a high-speed differential bus signal. The FPGA processor is used to convert the high-speed differential bus signal from the signal generator into an RGB signal, and control the bridge integrated circuit Bridge IC to convert the RGB signal into a C-PHY signal. The screen body module is used to receive the C-PHY signal from the bridge integrated circuit Bridge IC for detection.
[0011] In an embodiment of the present utility model, the screen body module includes a screen body FPC and a screen body to be detected. The screen body FPC is respectively connected to the bridge integrated circuit Bridge IC and the screen body. The screen body FPC is used to receive the C-PHY signal output by the bridge integrated circuit Bridge IC, and transmit the C-PHY signal to the screen body to be detected to detect the screen body.
[0012] In an embodiment of the present utility model, a display driver chip is further provided in the screen body. The display driver chip converts the C-PHY signal received by the screen body into a dot screen signal to light up the screen body for detection.
[0013] In an embodiment of the present utility model, the signal generator and the C-PHY signal box are connected by a high-speed differential bus.
[0014] In an embodiment of the present utility model, the high-speed differential bus is any one of the high-speed differential buses formed by an LVDS interface, the high-speed differential buses formed by an EDP interface, or the high-speed differential buses formed by a SERDES interface.
[0015] In an embodiment of the present utility model, the C-PHY signal box is provided with a PCB board, and the FPGA processor and the bridge integrated circuit Bridge IC are integrated on the PCB board.
[0016] In an embodiment of the present utility model, the C-PHY signal box is provided with two PCB boards, and the two PCB boards include a core board and a signal base board. The signal generator is connected to the signal base board, the signal base board is connected to the core board, the signal base board is connected to the FPC of the screen body, and the FPGA processor and the bridge integrated circuit Bridge IC are integrated on the core board.
[0017] In an embodiment of the present utility model, the signal base board is connected to the core board through a board-to-board connector, and the signal base board is connected to the FPC of the screen body through a board-to-board connector or a crimping method.
[0018] In an embodiment of the present utility model, a transfer FPC for adapting to different FPCs of the screen body is provided between the C-PHY signal box and the FPC of the screen body, and the transfer FPC is respectively connected to the signal base board and the FPC of the screen body.
[0019] In an embodiment of the present utility model, the transfer FPC is connected to the signal base board through an FPC connector, and the transfer FPC is connected to the FPC of the screen body through a board-to-board connector or a crimping method.
[0020] The above technical solution of the present utility model has the following advantages compared with the prior art:
[0021] The test fixture for Mipi C-PHY signals constructed by the present utility model can effectively transmit C-PHY signals to the screen body for detecting the screen body;
[0022] The signal base board of the present utility model can be flexibly replaced according to the different requirements of different work stations in the module factory, and can also be flexibly replaced according to the requirements of the screen bodies of different model types; the transfer FPC of the present utility model can be flexibly replaced according to the different requirements of different work stations in the module factory, and can also be flexibly replaced according to the requirements of the screen bodies of different model types;
[0023] The present utility model has strong practicability and is easy to be popularized on a large scale. Description of the Drawings
[0024] To make the content of the present utility model easier to understand clearly, the following further elaborates on the present utility model in detail according to the specific embodiments of the present utility model and in conjunction with the attached drawings, where
[0025] Figure 1 is the structural block diagram of the test fixture for Mipi C-PHY signals in the first embodiment of the present utility model;
[0026] Figure 2 is the structural block diagram of the test fixture for Mipi C-PHY signals in the second embodiment of the present utility model;
[0027] Figure 3 is the structural block diagram of the test fixture for Mipi C-PHY signals in the third embodiment of the present utility model;
[0028] Explanation of the reference numerals in the drawings of the specification: 1. Signal generator; 2. C-PHY signal box; 3. FPGA processor; 4. Bridge integrated circuit Bridge IC; 5. Screen body FPC; 6. Screen body; 7. Core board; 8. Signal baseboard; 9. Transfer FPC. Detailed implementation manners
[0029] The following further illustrates the present utility model in conjunction with the attached drawings and specific embodiments, so that those skilled in the art can better understand the present utility model and be able to implement it, but the embodiments cited do not limit the present utility model.
[0030] Refer to Figure 1 As shown, the present utility model relates to a test fixture for Mipi C-PHY signals, including a signal generator (Pattern Generator) 1, a C-PHY signal box 2, and a screen module to be detected. The C-PHY signal box 2 includes an FPGA processor 3 and a bridge integrated circuit Bridge IC 4. The signal generator 1 is connected to the FPGA processor 3 in the C-PHY signal box 2. The FPGA processor 3 is connected to the bridge integrated circuit Bridge IC 4. The bridge integrated circuit Bridge IC 4 is connected to the screen module.
[0031] The signal generator 1 is used to generate high-speed differential bus signals. The FPGA processor 3 is used to convert the high-speed differential bus signals from the signal generator 1 into RGB signals and control the bridge integrated circuit Bridge IC 4 to convert the RGB signals into C-PHY signals. The screen module is used to receive the C-PHY signals from the bridge integrated circuit Bridge IC 4 for detection.
[0032] Mipi (Mobile Industry Processor Interface) is the abbreviation of Mobile Industry Processor Interface. It is a set of open standards and specifications defined by the MIPI Alliance for the hardware interface in mobile devices. Mipi C-PHY (Common PHY) is a physical layer (PHY) standard for high-speed serial communication interfaces in mobile devices defined by the MIPI Alliance. C-PHY aims to provide a high-bandwidth, low-power, and multi-purpose interface solution suitable for a variety of applications, including but not limited to displays, cameras, sensors, etc.
[0033] It should be noted that the screen body FPC5 refers to the flexible printed circuit of the screen body. This is a flexible circuit board commonly used in electronic devices to provide a flexible connection method.
[0034] Furthermore, a power line is also connected between the signal generator 1 and the C-PHY signal box 2.
[0035] Furthermore, the screen body module includes a screen body FPC5 and a screen body 6 to be detected. The screen body FPC5 is respectively connected to the bridge integrated circuit Bridge IC4 and the screen body 6. The screen body FPC5 is used to receive the C-PHY signal output by the bridge integrated circuit Bridge IC4 and transmit the C-PHY signal to the screen body 6 to be detected for detecting the screen body 6.
[0036] Furthermore, a display driver chip is also provided inside the screen body 6. The display driver chip converts the C-PHY signal received by the screen body 6 into a dot screen signal to light up the screen body 6 for detection.
[0037] Furthermore, the signal generator 1 and the C-PHY signal box 2 are connected by a high-speed differential bus.
[0038] Furthermore, the high-speed differential bus is any one of the high-speed differential buses formed by the LVDS interface, the high-speed differential buses formed by the EDP interface, or the high-speed differential buses formed by the SERDES interface.
[0039] Furthermore, the C-PHY signal box 1 is provided with a PCB board, and the FPGA processor 3 and the bridge integrated circuit Bridge IC4 are integrated on the PCB board.
[0040] Furthermore, the C-PHY signal box 1 is provided with two PCB boards. The two PCB boards include a core board 7 and a signal base board 8. The signal generator 1 is connected to the signal base board 8, the signal base board 8 is connected to the core board 7, the signal base board 8 is connected to the screen body FPC 5, and the FPGA processor 3 and the bridge integrated circuit Bridge IC 4 are integrated on the core board 7.
[0041] Furthermore, the signal base board 8 and the core board 7 are connected by a board-to-board connector, and the signal base board 8 and the screen body FPC 5 are connected by a board-to-board connector or a crimping method.
[0042] Furthermore, a transfer FPC 9 for adapting to different screen body FPC 5s is provided between the C-PHY signal box 2 and the screen body FPC 5. The transfer FPC 9 can also extend the C-PHY signal transmission length to adapt to different screen bodies and different crimping jig requirements. The transfer FPC 9 is respectively connected to the signal base board 8 and the screen body FPC 5.
[0043] Furthermore, the transfer FPC 9 and the signal base board 8 are connected by an FPC connector, and the transfer FPC 9 and the screen body FPC 5 are connected by a board-to-board connector or a crimping method.
[0044] The following details the present utility model through three embodiments:
[0045] Embodiment 1
[0046] Please refer to Figure 1 , the signal generator 1 in this embodiment still uses the signal generating device in the traditional test jig, which can save the cost of developing a new signal generating device; the high-speed differential bus output by the signal generator 1 mainly includes the high-speed differential bus formed by the LVDS interface, or the high-speed differential bus formed by the EDP interface, or the high-speed differential bus formed by the SERDES interface, etc.; the C-PHY signal box 2 mainly includes the FPGA processor 3 and the bridge integrated circuit Bridge IC 4. The signal generator 1 communicates with the FPGA processor 3 of the C-PHY signal box 2 through the high-speed differential bus, and then the FPGA processor 3 controls the bridge integrated circuit Bridge IC 4 to output the C-PHY signal; the C-PHY signal output by the C-PHY signal box 2 is directly connected to the screen body FPC 5, and the C-PHY signal is then converted into a dot screen signal through the DDIC (display driver chip) in the screen body 6 to directly light up the screen body 6 for testing the screen body 6.
[0047] In Embodiment 1, inside the C-PHY signal box 2, a PCB board integrates signal input, power input, an FPGA processor 3, a bridge integrated circuit Bridge IC4 (i.e., a C-PHY signal bridging chip), signal output, and power output.
[0048] The advantage of the test fixture architecture in Embodiment 1 is that the C-PHY signal transmission path is the shortest, greatly improving signal quality and stability, and is applicable to C-PHY panels with a relatively long FPC5 of the panel; the longer the FPC5 of the panel is, the longer the routing of the C-PHY signal line at the panel end is, which requires the C-PHY signal transmission line at the test fixture end to be shorter.
[0049] In actual applications, different stations in the display module factory have different requirements for the external structure and output interface method of the C-PHY signal box 2, and the connectors and pin definitions of different models of panels 6 are also different; in this case, different workstations and different models of panels 6 all require a different PCB board for the C-PHY signal box 2 to be made, which will cause the production cost and management cost of the test fixture to increase exponentially; to better solve this problem, Embodiment 1 needs to be expanded, and for details, please refer to Embodiment 2 and Embodiment 3.
[0050] Embodiment 2
[0051] Please refer to Figure 2 , Embodiment 2 is an expanded architecture of Embodiment 1, mainly changing the C-PHY signal box 2 from one PCB board to two PCB boards that can be snap-connected board-to-board (including a signal base board 8 and a core board 7).
[0052] The advantage of Embodiment 2 is that the costly core board 7 remains unchanged, and for different workstations and different screen models, only the corresponding signal base board 8 needs to be replaced, which can effectively save costs; at the same time, the output interface of the core board 7 is as close as possible to the output interface of the signal base board 8 to ensure that the C-PHY signal transmission path is as short as possible to ensure the quality and stability of the C-PHY signal;
[0053] The signal generator 1 in this embodiment still uses the signal generating device in the traditional test fixture, which can save the cost of developing a new signal generating device. The high-speed differential bus output by the signal generator 1 mainly includes the high-speed differential bus formed by the LVDS interface, or the high-speed differential bus formed by the EDP interface, or the high-speed differential bus formed by the SERDES interface, etc. The high-speed differential bus is input from the signal base plate 8 of the C-PHY signal box 2, and then transmitted from the signal base plate 8 to the FPGA processor 3 of the core board 7 through the board-to-board connector. Then, the FPGA processor 3 controls the bridge integrated circuit Bridge IC4 to output the C-PHY signal. The C-PHY signal is transmitted to the signal base plate 8 through the board-to-board connector. The C-PHY signal is directly connected to the screen body FPC5 in the signal base plate 8 by means of crimping or board-to-board connector. The C-PHY signal is then converted into a dot screen signal by the DDIC (display driver chip) in the screen body 6 to directly light up the screen body 6 for testing the screen body 6.
[0054] In the second embodiment, the signal base plate 8 and the screen body 6 have different connection methods at different work stations. For example, in the automated machine, the signal base plate 8 and the screen body 6 adopt the automatic crimping method, and at the same time, the structure of the signal base plate 8 needs to be designed according to the structure of the automatic crimping fixture. In the semi-automatic lighting machine, the signal base plate 8 and the screen body 6 adopt the semi-automatic crimping method, and at the same time, the structure of the signal base plate 8 also needs to be designed according to the structure of the semi-automatic lighting fixture. In other work stations where the screen body is manually buckled, the signal base plate 8 and the screen body 6 are directly buckled to the screen body FPC5 through the board-to-board connector.
[0055] Embodiment Three
[0056] Please refer to Figure 3 , Embodiment Three is a further extended architecture of Embodiment Two. It mainly adds a transfer FPC9 on the basis of Embodiment Two. The transfer FPC9 is directly connected to the signal base plate 8 with an FPC connector. The transfer FPC9 and the screen body FPC5 can be directly buckled through the board-to-board connector or connected by the crimping method.
[0057] The advantage of Embodiment Three is that the costly core board 7 and signal base plate 8 remain unchanged. For different work stations and different screen models, only the corresponding transfer FPC9 needs to be replaced for docking, which can save costs to the greatest extent. Given the limitation of the length of the C-PHY signal transmission line, the length of the transfer FPC9 should be as short as possible (usually required to exceed 50 mm) to ensure the stability of the C-PHY signal quality.
[0058] The signal generator 1 in this embodiment still uses the signal generating device in the traditional test fixture, which can save the cost of developing a new signal generating device; the high-speed differential bus output by the signal generator 1 mainly includes the high-speed differential bus formed by the LVDS interface, or the high-speed differential bus formed by the EDP interface, or the high-speed differential bus formed by the SERDES interface, etc.; the high-speed differential bus is input from the signal base plate 8 of the C-PHY signal box 2, and then transmitted from the signal base plate 8 to the FPGA processor 3 of the core board 7 through the board-to-board connector, and then the FPGA processor 3 controls the bridge integrated circuit Bridge IC4 to output the C-PHY signal, and the C-PHY signal is transmitted to the signal base plate 8 through the board-to-board connector. The C-PHY signal is directly connected to the transfer FPC9 through the FPC connector in the signal base plate 8. The C-PHY signal passes through the transfer FPC9 and is directly buckled or connected to the screen body FPC5 through the board-to-board connector. The C-PHY signal is then converted into a dot screen signal by the DDIC (display driver chip) in the screen body 6 and directly lights up the screen body 6 to test the screen body 6.
[0059] In the third embodiment, the transfer FPC9 and the screen body 6 have different connection methods at different working stations; for example, in the automated machine tool, the transfer FPC9 and the screen body 6 adopt the automatic crimping method, and at the same time, the structure of the transfer FPC9 needs to be designed according to the structure of the automatic crimping fixture; in the semi-automatic lighting machine tool, the transfer FPC9 and the screen body 6 adopt the semi-automatic crimping method, and at the same time, the structure of the transfer FPC9 also needs to be designed according to the structure of the semi-automatic lighting fixture; in other working stations where the screen body is manually buckled, the transfer FPC9 and the screen body 6 are directly buckled to the screen body FPC5 through the board-to-board connector;
[0060] Because the C-PHY signal has limitations on the length of the signal transmission line, this embodiment needs to design the optimal test fixture solution according to the actual situation of different models of C-PHY screen bodies and different working stations; the first requirement is that the C-PHY signal quality meets the actual dot screen requirements, and on this basis, the production cost of the test fixture is reduced as much as possible.
[0061] Obviously, the above embodiments are only examples clearly described and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.
Claims
1. A test fixture for Mipi C-PHY signals, characterized in that: It includes a signal generator (1), a C-PHY signal box (2), and a screen module to be detected. The C-PHY signal box (2) includes an FPGA processor (3) and a bridge integrated circuit Bridge IC (4). The signal generator (1) is connected to the FPGA processor (3) in the C-PHY signal box (2). The FPGA processor (3) is connected to the bridge integrated circuit Bridge IC (4). The bridge integrated circuit Bridge IC (4) is connected to the screen module. The signal generator (1) is used to generate high-speed differential bus signals. The FPGA processor (3) is used to convert the high-speed differential bus signals from the signal generator (1) into RGB signals and control the bridge integrated circuit Bridge IC (4) to convert the RGB signals into C-PHY signals. The screen module is used to receive the C-PHY signals from the bridge integrated circuit Bridge IC (4) for detection.
2. The test fixture for Mipi C-PHY signals according to claim 1, wherein: The screen module includes a screen FPC (5) and a screen (6) to be detected. The screen FPC (5) is respectively connected to the bridge integrated circuit Bridge IC (4) and the screen (6). The screen FPC (5) is used to receive the C-PHY signals output by the bridge integrated circuit Bridge IC (4) and transmit the C-PHY signals to the screen (6) to be detected to detect the screen (6).
3. The test fixture for Mipi C-PHY signals according to claim 2, characterized in that: A display driver chip is also provided in the screen (6). The display driver chip converts the C-PHY signals received by the screen (6) into dot screen signals to light up the screen (6) for detection.
4. The test fixture for Mipi C-PHY signals according to claim 1, characterized in that: The signal generator (1) and the C-PHY signal box (2) are connected by a high-speed differential bus.
5. The test fixture for Mipi C-PHY signals according to claim 4, characterized in that: The high-speed differential bus is any one of the high-speed differential buses formed by an LVDS interface, the high-speed differential buses formed by an EDP interface, or the high-speed differential buses formed by a SERDES interface.
6. The test fixture for Mipi C-PHY signals according to claim 1, wherein: The C-PHY signal box (2) is provided with a PCB board. The FPGA processor (3) and the bridge integrated circuit Bridge IC (4) are integrated on the PCB board.
7. The test fixture for Mipi C-PHY signals according to claim 2, characterized in that: The C-PHY signal box (2) is provided with two PCB boards. The two PCB boards include a core board (7) and a signal base board (8). The signal generator (1) is connected to the signal base board (8). The signal base board (8) is connected to the core board (7). The signal base board (8) is connected to the screen FPC (5). The FPGA processor (3) and the bridge integrated circuit Bridge IC (4) are integrated on the core board (7).
8. The test fixture for Mipi C-PHY signals according to claim 7, wherein: The signal base board (8) is connected to the core board (7) through a board-to-board connector. The signal base board (8) is connected to the screen FPC (5) through a board-to-board connector or a crimping method.
9. The test fixture for Mipi C-PHY signals according to claim 7, characterized in that: A transfer FPC (9) for adapting to different screen FPCs (5) is provided between the C-PHY signal box (2) and the screen FPC (5). The transfer FPC (9) is respectively connected to the signal base board (8) and the screen FPC (5).
10. The test fixture for Mipi C-PHY signals according to claim 9, characterized in that: The intermediate FPC (9) is connected to the signal backplane (8) through an FPC connector, and the intermediate FPC (9) is connected to the panel FPC (5) through a board-to-board connector or a crimping method.