Isolated SBUS signal conversion circuit

Abstract

The utility model discloses an isolation type SBUS signal conversion circuit. The circuit comprises an inverter circuit, a microcontroller and an isolation circuit, the input end of the phase inverter circuit is connected with the output end of an SBUS signal, the output end of the phase inverter circuit is connected with the microcontroller, and the phase inverter circuit is used for converting the SBUS signal into a logic level signal; the isolation circuit comprises a power isolation circuit and a signal isolation circuit, the input end of the signal isolation circuit is connected with the microcontroller, the input end of the power isolation circuit is connected with a power supply, and the output end of the power isolation circuit is connected with the inverter circuit, the microcontroller and the power supply end of the signal isolation circuit. According to the utility model, the conversion from the SBUS signal to the logic level signal is realized through the inverter circuit and the microcontroller, so that a developer can flexibly adjust and optimize the conversion process according to specific requirements, and the development flexibility and the secondary development capability are remarkably improved.

Description

Technical Field

[0001] The utility model relates to the technical field of circuits, and particularly relates to an isolated SBUS signal conversion circuit. Background Art

[0002] SBUS, the full name is Serial Bus, that is, a serial communication bus. SBUS is a serial communication protocol, using a baud rate of 100K, 8 data bits, 2 stop bits, and even parity, that is, 8E2 serial communication.

[0003] In the prior art, the SBUS communication module usually adopts a dedicated SBUS to UART chip. Although these dedicated chips can realize the conversion between SBUS signals and UART signals, the structure of the dedicated SBUS to UART chip is closed and it is difficult to carry out secondary development. This is a significant obstacle for users who need to expand functions and deeply customize. Developers cannot flexibly adjust and optimize the chip functions according to specific requirements, which greatly limits developers during use and affects the diversity of innovation and applications. Summary of the Utility Model

[0004] Therefore, the embodiment of the utility model provides an isolated SBUS signal conversion circuit to solve the problem that the structure of the dedicated SBUS to UART chip in the prior art is closed and it is difficult to carry out secondary development.

[0005] In order to achieve the above purpose, the embodiment of the utility model provides the following technical solutions:

[0006] An isolated SBUS signal conversion circuit includes an inverter circuit, a microcontroller, and an isolation circuit;

[0007] The input end of the inverter circuit is connected to the output end of the SBUS signal, the output end of the inverter circuit is connected to the microcontroller, and the inverter circuit is used to convert the SBUS signal into a logic level signal;

[0008] The isolation circuit includes a power isolation circuit and a signal isolation circuit. The input end of the signal isolation circuit is connected to the microcontroller, the input end of the power isolation circuit is connected to the power supply, and the output end of the power isolation circuit is respectively connected to the power supply terminals of the inverter circuit, the microcontroller, and the signal isolation circuit.

[0009] Optionally, the microcontroller is an STM32F103C8T6 microcontroller.

[0010] Optionally, the inverter circuit includes a second triode Q2;

[0011] The first end of the second triode Q2 is divided into two paths. One path is connected to the output end of the SBUS signal via the twelfth resistor R12, and the other path is grounded via the thirteenth resistor R13;

[0012] The second end of the second triode Q2 is grounded;

[0013] The third end of the second triode Q2 is divided into two paths. One path is connected to the +3.3V voltage output end via the eleventh resistor R11, and the other path is connected to the 13th pin of the microcontroller.

[0014] Optionally, the signal isolation circuit includes a first triode Q1 and a first chip U1, and the first chip U1 includes a CA-IS3082WX chip.

[0015] Optionally, the first end of the first triode Q1 is connected to one end of the eighth resistor R8. The other end of the eighth resistor R8 is divided into two paths. One path is connected to the +3.3V voltage output end via the fifth resistor R5, and the other path is connected to the 30th pin of the microcontroller;

[0016] The second end of the first triode Q1 is grounded;

[0017] The third end of the first triode Q1 is divided into two paths. One path is connected to the +3.3V voltage output end via the third resistor R3, and the other path is connected to the 5th pin of the first chip U1.

[0018] Optionally, the 1st pin of the first chip U1 is divided into two paths. One path is connected to the +3.3V voltage output end, and the other path is grounded via the second capacitor C2; the 2nd pin and the 8th pin of the first chip U1 are both grounded; the 3rd pin of the first chip U1 is divided into two paths. One path is connected to the 31st pin of the microcontroller, and the other path is connected to the +3.3V voltage output end via the first resistor R1; the 4th pin of the first chip U1 is connected to the 5th pin of the first chip U1; the 6th pin of the first chip U1 is connected to the 30th pin of the microcontroller; the 7th pin of the first chip U1 is divided into three paths. One path is grounded via the ninth resistor R9, another path is grounded via the third capacitor C3, and the third path is connected to the +3.3V voltage output end via the sixth resistor R6;

[0019] The 9th pin of the first chip U1 is connected to the isolated ground; the 10th pin of the first chip U1 is connected to the isolated ground via the tenth resistor R10; the 11th and 14th pins of the first chip U1 are both floating; the 12th pin of the first chip U1 is divided into two paths, one path is connected to the 5V isolated voltage output terminal via the twelfth resistor R12, and the other path is connected to the 4th pin of the second chip U2; the 13th pin of the first chip U1 is divided into two paths, one path is connected to the isolated ground via the seventh resistor R7, and the other path is connected to the 3rd pin of the second chip U2; the 15th pin of the first chip U1 is divided into two paths, one path is connected to the isolated ground, and the other path is connected to the 5V isolated voltage output terminal via the first capacitor C1; the 16th pin of the first chip U1 is connected to the 5V isolated voltage output terminal;

[0020] The 1st pin of the second chip U2 is divided into two paths, one path is connected to one end of the second diode D2, and the other path is connected to one end of the third diode D3; the 2nd pin of the second chip U2 is divided into two paths, one path is connected to the other end of the second diode D2, and the other path is connected to one end of the first diode D1;

[0021] The other ends of the first diode D1 and the third diode D3 are both connected to the isolated ground; the connection end of the first diode D1 and the second diode D2 is divided into two paths, one path is connected to one end of the fourth resistor R4, and the other path is connected to the 1st pin of the terminal block P4; the connection end of the second diode D2 and the third diode D3 is divided into two paths, one path is connected to the other end of the fourth resistor R4, and the other path is connected to the 2nd pin of the terminal block P4, the 3rd pin of the terminal block P4 is grounded, and the 4th pin of the terminal block P4 is connected to the 24V DC voltage output terminal.

[0022] Optionally, the power isolation circuit includes a first buck circuit, a second buck circuit, and an isolation circuit;

[0023] The input end of the first buck circuit is connected to the power supply, the output end of the first buck circuit is connected to the input end of the second buck circuit, and the output end of the second buck circuit is connected to the power supply ends of the inverter circuit, the microcontroller, and the signal isolation circuit;

[0024] The input end of the isolation circuit is connected to the output end of the first buck circuit, and the output end of the isolation circuit is connected to the power supply end of the signal isolation circuit.

[0025] Optionally, the first buck circuit includes a third chip U3, and the third chip U3 includes an RT7272BGSP chip.

[0026] Optionally, the second step-down circuit includes a fifth chip U5, and the fifth chip U5 includes an LM1117IMPX-3.3 / NOPB chip.

[0027] Optionally, the isolation circuit includes a seventh chip U7, and the seventh chip U7 includes a B0505S-1WR3 chip;

[0028] The first pin of the seventh chip U7 is divided into two paths, one path is grounded, and the other path is connected to one end of the sixteenth capacitor C16; the second pin of the seventh chip U7 is divided into two paths, one path is connected to the +5V voltage output terminal of the first step-down circuit, and the other path is connected to the other end of the sixteenth capacitor C16; the third pin of the seventh chip U7 is divided into two paths, one path is connected to the isolated ground, and the other path is connected to one end of the seventeenth capacitor C17; the fourth pin of the seventh chip U7 is divided into two paths, one path is the 5V isolated voltage output terminal, and the other path is connected to the other end of the seventeenth capacitor C17.

[0029] The utility model has at least the following beneficial effects:

[0030] The utility model provides an isolated SBUS signal conversion circuit, which includes an inverter circuit, a microcontroller and an isolation circuit; the input end of the inverter circuit is connected to the output end of the SBUS signal, the output end of the inverter circuit is connected to the microcontroller, and the inverter circuit is used to convert the SBUS signal into a logic level signal; the isolation circuit includes a power isolation circuit and a signal isolation circuit, the input end of the signal isolation circuit is connected to the microcontroller, the input end of the power isolation circuit is connected to the power supply, and the output end of the power isolation circuit is respectively connected to the power supply terminals of the inverter circuit, the microcontroller and the signal isolation circuit. The utility model realizes the conversion of the SBUS signal to the logic level signal through the inverter circuit and the microcontroller, rather than relying on a dedicated SBUS to UART chip, which is convenient for developers to flexibly adjust and optimize the conversion process according to specific requirements, and significantly improves the development flexibility and secondary development ability. Description of the Drawings

[0031] In order to more clearly illustrate the prior art and the present utility model, the drawings required for describing the prior art and the embodiments of the present utility model will be briefly introduced below. Obviously, the drawings described below are only exemplary, and those of ordinary skill in the art can also obtain other drawings according to the provided drawings without creative efforts.

[0032] The structures, proportions, sizes, etc. illustrated in this specification are only used to cooperate with the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the implementation conditions of the present utility model. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present utility model can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present utility model.

[0033] Figure 1 It is a circuit principle block diagram of an isolation type SBUS signal conversion circuit provided by an embodiment of the present utility model;

[0034] Figure 2 It is a circuit schematic diagram of a microcontroller provided by an embodiment of the present utility model;

[0035] Figure 3 It is a circuit schematic diagram of an inverter circuit provided by an embodiment of the present utility model;

[0036] Figure 4 It is a circuit schematic diagram of a signal isolation circuit provided by an embodiment of the present utility model;

[0037] Figure 5 It is a circuit schematic diagram of a first step-down circuit provided by an embodiment of the present utility model;

[0038] Figure 6 It is a circuit schematic diagram of a second step-down circuit provided by an embodiment of the present utility model;

[0039] Figure 7 It is a circuit schematic diagram of an isolation circuit provided by an embodiment of the present utility model. Detailed implementation manners

[0040] In order to make the objectives, technical solutions and advantages of this application clearer, the following further elaborates on this application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0041] In the description of the present utility model, unless otherwise specified, "a plurality of" means two or more. Terms such as "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present utility model and the above-mentioned drawings are intended to distinguish the objects being referred to. For solutions with a time sequence process, this way of term expression does not necessarily need to be understood as describing a specific order or sequence, and for solutions of device structures, this way of term expression also does not distinguish the importance level, positional relationship, etc.

[0042] In addition, the terms "comprising", "having", and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units need not be limited to those steps or units explicitly listed, but may also include other steps or units that are inherent to these processes, methods, products, or devices although not explicitly listed, or steps or units added based on further optimization schemes of the inventive concept of the present utility model.

[0043] In the related art, the SBUS communication module usually adopts a dedicated SBUS-to-UART chip. Although these dedicated chips can achieve the conversion between SBUS signals and UART signals, the structure of the dedicated SBUS-to-UART chip is closed and it is difficult to perform secondary development. This is a significant obstacle for users who need to expand functions and deeply customize. Developers cannot flexibly adjust and optimize the chip functions according to specific requirements, which greatly limits developers during use and affects the diversity of innovation and applications. In addition, since dedicated chips are mostly produced by specific manufacturers and the supply channels are limited, their market prices remain high, increasing the cost of products and being unfavorable for large-scale promotion and application, especially in cost-sensitive consumer electronic products, which is particularly prominent. During the actual communication process, the existing SBUS-to-UART chips also have problems such as high bit error rate and data packet loss. These problems are mainly reflected in the reliability and stability of data transmission, especially obvious in harsh environments or long-distance transmissions. The high bit error rate and data packet loss phenomena not only affect the accuracy of data transmission, but may also lead to a decline in the overall performance of the system and even pose potential safety hazards.

[0044] An isolated SBUS signal conversion circuit provided by this application realizes the conversion from SBUS signals to logic level signals through an inverter circuit and a microcontroller, rather than relying on a dedicated SBUS-to-UART chip, which facilitates developers to flexibly adjust and optimize the conversion process according to specific requirements, significantly improving the flexibility of development and the ability of secondary development; and the circuit of this application no longer relies on expensive dedicated chips, but uses a general microcontroller and an inverter circuit, reducing the overall cost and contributing to large-scale promotion and application. In addition, the isolated SBUS signal conversion circuit of this application also introduces an isolation circuit, including a power isolation circuit and a signal isolation circuit, effectively isolating the power supply and signal paths, and reducing the influence of electromagnetic interference and noise on data transmission. Through this isolation design, the reliability and stability of data transmission are significantly improved, and the bit error rate and data packet loss phenomena are reduced.

[0045] As Figure 1 shown, an isolated SBUS signal conversion circuit includes an inverter circuit, a microcontroller, and an isolation circuit;

[0046] The input end of the inverter circuit is connected to the output end of the SBUS signal, and the output end of the inverter circuit is connected to the microcontroller. The inverter circuit is used to convert the SBUS signal into a logic level signal;

[0047] The isolation circuit includes a power isolation circuit and a signal isolation circuit. The input end of the signal isolation circuit is connected to the microcontroller, the input end of the power isolation circuit is connected to the power supply, and the output end of the power isolation circuit is respectively connected to the power supply terminals of the inverter circuit, the microcontroller, and the signal isolation circuit.

[0048] Among them, an isolation type SBUS signal conversion circuit provided by the present application is characterized in that: an SBUS to serial port system circuit, the system circuit includes an inverter circuit, a signal isolation circuit, a power isolation circuit, and an STM32 control system. This system combines signal isolation technology with serial port communication conversion technology to design an isolation type SBUS to serial port circuit. The utility model converts the SBUS signal into a normal logic level through the SBUS to serial port circuit, and sequentially converts the non-standard communication protocol into a standard isolation type serial port communication protocol through the STM32 control system and the signal isolation circuit. As an isolation type SBUS to serial port circuit, the utility model has a simple circuit structure, strong anti-interference ability, low cost, and stable communication between devices, and is widely used in the field of wireless communication of electronic circuits.

[0049] It should be noted that an isolation type SBUS signal conversion circuit provided by the present application aims to solve the problems of converting the level of the physical layer into a normal logic level, converting the non-standard communication protocol into a standard communication protocol, reducing the phenomenon of high communication error rate, and solving the problem of data packet loss.

[0050] It should be noted that the present application uses an inverter circuit to convert the SBUS signal into a normal logic level, and then the microcontroller processes it to convert the non-standard communication protocol into a standard communication protocol. Compared with the SBUS communication module, it is easier for secondary development, has stable performance, and low cost.

[0051] In the embodiment of the present application, the conversion from SBUS signal to logic level signal is achieved through an inverter circuit and a microcontroller, rather than relying on a dedicated SBUS-to-UART chip. This facilitates developers to flexibly adjust and optimize the conversion process according to specific requirements, significantly improving the flexibility of development and the ability of secondary development. Moreover, the circuit of the present application no longer relies on expensive dedicated chips, but uses a general microcontroller and an inverter circuit, reducing the overall cost and contributing to large-scale promotion and application. In addition, the isolated SBUS signal conversion circuit of the present application also introduces an isolation circuit, including a power isolation circuit and a signal isolation circuit, effectively isolating the power supply and signal paths, and reducing the impact of electromagnetic interference and noise on data transmission. Through this isolation design, the reliability and stability of data transmission are significantly improved, reducing the error rate and data packet loss phenomenon.

[0052] As Figure 2 shown, in an embodiment of the present application, the microcontroller is an STM32F103C8T6 microcontroller.

[0053] As Figure 3 shown, in an embodiment of the present application, the inverter circuit includes a second triode Q2;

[0054] The first end of the second triode Q2 is divided into two paths. One path is connected to the output end of the SBUS signal through a twelfth resistor R12, and the other path is grounded through a thirteenth resistor R13;

[0055] The second end of the second triode Q2 is grounded;

[0056] The third end of the second triode Q2 is divided into two paths. One path is connected to the +3.3V voltage output end through an eleventh resistor R11, and the other path is connected to the 13th pin of the microcontroller.

[0057] It should be noted that the main components of the inverter circuit include the second triode Q2, the twelfth resistor R12 with a resistance value of 1K, and the eleventh resistor R11 with a resistance value of 10K.

[0058] The SBUS signal is input from the base of the second triode Q2 and output from the collector of the second triode Q2. When "0" is input to the base of the second triode Q2, the output at the collector of the second triode Q2 is pulled up to "1"; when "1" is input to the base of the second triode Q2, the second triode Q2 conducts, and the output of the second triode Q2 is pulled low to "0", achieving inversion.

[0059] As Figure 4 shown, in an embodiment of the present application, the signal isolation circuit includes a first triode Q1 and a first chip U1, and the first chip U1 includes a CA-IS3082WX chip.

[0060] Among them, the main functions of the signal isolation circuit include improving the reliability and stability of communication, protecting device safety, and improving signal quality.

[0061] It should be noted that the main component of the signal isolation circuit is the first chip U1. The CA-IS308x chip is a series of isolated RS-485 / RS-422 transceivers, and the logic input and output buffers inside this series of devices are isolated by a silicon dioxide (SiO2) insulating gate.

[0062] In an embodiment of the present application, the first end of the first triode Q1 is connected to one end of the eighth resistor R8. The other end of the eighth resistor R8 is divided into two paths. One path is connected to the +3.3V voltage output terminal through the fifth resistor R5, and the other path is connected to the 30th pin of the microcontroller.

[0063] The second end of the first triode Q1 is grounded.

[0064] The third end of the first triode Q1 is divided into two paths. One path is connected to the +3.3V voltage output terminal through the third resistor R3, and the other path is connected to the 5th pin of the first chip U1.

[0065] In an embodiment of the present application, the 1st pin of the first chip U1 is divided into two paths. One path is connected to the +3.3V voltage output terminal, and the other path is grounded through the second capacitor C2. The 2nd and 8th pins of the first chip U1 are both grounded. The 3rd pin of the first chip U1 is divided into two paths. One path is connected to the 31st pin of the microcontroller, and the other path is connected to the +3.3V voltage output terminal through the first resistor R1. The 4th pin of the first chip U1 is connected to the 5th pin of the first chip U1. The 6th pin of the first chip U1 is connected to the 30th pin of the microcontroller. The 7th pin of the first chip U1 is divided into three paths. One path is grounded through the ninth resistor R9, another path is grounded through the third capacitor C3, and the third path is connected to the +3.3V voltage output terminal through the sixth resistor R6.

[0066] The 9th pin of the first chip U1 is connected to the isolated ground. The 10th pin of the first chip U1 is connected to the isolated ground through the tenth resistor R10. The 11th and 14th pins of the first chip U1 are both floating. The 12th pin of the first chip U1 is divided into two paths. One path is connected to the 5V isolated voltage output terminal through the twelfth resistor R12, and the other path is connected to the 4th pin of the second chip U2. The 13th pin of the first chip U1 is divided into two paths. One path is connected to the isolated ground through the seventh resistor R7, and the other path is connected to the 3rd pin of the second chip U2. The 15th pin of the first chip U1 is divided into two paths. One path is connected to the isolated ground, and the other path is connected to the 5V isolated voltage output terminal through the first capacitor C1. The 16th pin of the first chip U1 is connected to the 5V isolated voltage output terminal.

[0067] The first pin of the second chip U2 is divided into two paths. One path is connected to one end of the second diode D2, and the other path is connected to one end of the third diode D3. The second pin of the second chip U2 is divided into two paths. One path is connected to the other end of the second diode D2, and the other path is connected to one end of the first diode D1.

[0068] The other ends of the first diode D1 and the third diode D3 are both connected to the isolated ground. The connection end of the first diode D1 and the second diode D2 is divided into two paths. One path is connected to one end of the fourth resistor R4, and the other path is connected to the first pin of the terminal block P4. The connection end of the second diode D2 and the third diode D3 is divided into two paths. One path is connected to the other end of the fourth resistor R4, and the other path is connected to the second pin of the terminal block P4. The third pin of the terminal block P4 is grounded, and the fourth pin of the terminal block P4 is connected to the 24V DC voltage output terminal.

[0069] In an embodiment of the present application, the power isolation circuit includes a first step-down circuit, a second step-down circuit, and an isolation circuit.

[0070] The input end of the first step-down circuit is connected to the power supply, the output end of the first step-down circuit is connected to the input end of the second step-down circuit, and the output end of the second step-down circuit is connected to the power supply terminals of the inverter circuit, the microcontroller, and the signal isolation circuit.

[0071] The input end of the isolation circuit is connected to the output end of the first step-down circuit, and the output end of the isolation circuit is connected to the power supply terminal of the signal isolation circuit.

[0072] As Figure 5 shown, in an embodiment of the present application, the first step-down circuit includes a third chip U3, and the third chip U3 includes an RT7272BGSP chip.

[0073] As Figure 6 shown, in an embodiment of the present application, the second step-down circuit includes a fifth chip U5, and the fifth chip U5 includes an LM1117IMPX-3.3 / NOPB chip.

[0074] As Figure 7 shown, in an embodiment of the present application, the isolation circuit includes a seventh chip U7, and the seventh chip U7 includes a B0505S-1WR3 chip.

[0075] The first pin of the seventh chip U7 is divided into two paths. One path is grounded, and the other path is connected to one end of the sixteenth capacitor C16. The second pin of the seventh chip U7 is divided into two paths. One path is connected to the +5V voltage output terminal of the first buck circuit, and the other path is connected to the other end of the sixteenth capacitor C16. The third pin of the seventh chip U7 is divided into two paths. One path is connected to the isolated ground, and the other path is connected to one end of the seventeenth capacitor C17. The fourth pin of the seventh chip U7 is divided into two paths. One path is the 5V isolated voltage output terminal, and the other path is connected to the other end of the seventeenth capacitor C17.

[0076] It should be noted that the isolation circuit is used to create a safe isolation space between two different circuits to reduce or eliminate interference between AC and DC voltages. It can effectively protect electrical equipment.

[0077] The above-described embodiments only represent the specific implementation manners of the present utility model, and the description thereof is relatively specific and detailed. However, it should not be construed as a limitation on the scope of the patent of the present utility model. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present utility model, several modifications and improvements can still be made, and these all belong to the protection scope of the present utility model.

Claims

1. An isolated SBUS signal conversion circuit, characterized in that It includes an inverter circuit, a microcontroller, and an isolation circuit; The input end of the inverter circuit is connected to the output end of the SBUS signal. The output end of the inverter circuit is connected to the microcontroller. The inverter circuit is used to convert the SBUS signal into a logic level signal; The isolation circuit includes a power isolation circuit and a signal isolation circuit. The input end of the signal isolation circuit is connected to the microcontroller. The input end of the power isolation circuit is connected to the power supply. The output end of the power isolation circuit is respectively connected to the power supply terminals of the inverter circuit, the microcontroller, and the signal isolation circuit.

2. The isolated SBUS signal conversion circuit according to claim 1, wherein The microcontroller is an STM32F103C8T6 microcontroller.

3. The isolated SBUS signal conversion circuit according to claim 2, wherein The inverter circuit includes a second triode Q2; The first end of the second triode Q2 is divided into two paths. One path is connected to the output end of the SBUS signal through a twelfth resistor R12, and the other path is grounded through a thirteenth resistor R13; The second end of the second triode Q2 is grounded; The third end of the second triode Q2 is divided into two paths. One path is connected to the +3.3V voltage output end through an eleventh resistor R11, and the other path is connected to the 13th pin of the microcontroller.

4. The isolated SBUS signal conversion circuit according to claim 3, wherein The signal isolation circuit includes a first triode Q1 and a first chip U1. The first chip U1 includes a CA-IS3082WX chip.

5. An isolated SBUS signal conversion circuit according to claim 4, wherein The first end of the first triode Q1 is connected to one end of an eighth resistor R8. The other end of the eighth resistor R8 is divided into two paths. One path is connected to the +3.3V voltage output end through a fifth resistor R5, and the other path is connected to the 30th pin of the microcontroller; The second end of the first triode Q1 is grounded; The third end of the first triode Q1 is divided into two paths. One path is connected to the +3.3V voltage output end through a third resistor R3, and the other path is connected to the 5th pin of the first chip U1.

6. The isolated SBUS signal conversion circuit according to claim 4, wherein The first pin of the first chip U1 is divided into two paths. One path is connected to the +3.3V voltage output end, and the other path is grounded through a second capacitor C2. The second pin and the eighth pin of the first chip U1 are both grounded. The third pin of the first chip U1 is divided into two paths. One path is connected to the 31st pin of the microcontroller, and the other path is connected to the +3.3V voltage output end through a first resistor R1. The fourth pin of the first chip U1 is connected to the fifth pin of the first chip U1. The sixth pin of the first chip U1 is connected to the 30th pin of the microcontroller. The seventh pin of the first chip U1 is divided into three paths. One path is grounded through a ninth resistor R9, another path is grounded through a third capacitor C3, and the third path is connected to the +3.3V voltage output end through a sixth resistor R6; The 9th pin of the first chip U1 is connected to the isolated ground; the 10th pin of the first chip U1 is connected to the isolated ground via the tenth resistor R10; the 11th and 14th pins of the first chip U1 are both floating; the 12th pin of the first chip U1 is divided into two paths, one path is connected to the 5V isolated voltage output terminal via the twelfth resistor R12, and the other path is connected to the 4th pin of the second chip U2; the 13th pin of the first chip U1 is divided into two paths, one path is connected to the isolated ground via the seventh resistor R7, and the other path is connected to the 3rd pin of the second chip U2; the 15th pin of the first chip U1 is divided into two paths, one path is connected to the isolated ground, and the other path is connected to the 5V isolated voltage output terminal via the first capacitor C1; the 16th pin of the first chip U1 is connected to the 5V isolated voltage output terminal; The 1st pin of the second chip U2 is divided into two paths, one path is connected to one end of the second diode D2, and the other path is connected to one end of the third diode D3; the 2nd pin of the second chip U2 is divided into two paths, one path is connected to the other end of the second diode D2, and the other path is connected to one end of the first diode D1; The other ends of the first diode D1 and the third diode D3 are both connected to the isolated ground; the connection end of the first diode D1 and the second diode D2 is divided into two paths, one path is connected to one end of the fourth resistor R4, and the other path is connected to the 1st pin of the terminal block P4; the connection end of the second diode D2 and the third diode D3 is divided into two paths, one path is connected to the other end of the fourth resistor R4, and the other path is connected to the 2nd pin of the terminal block P4, the 3rd pin of the terminal block P4 is grounded, and the 4th pin of the terminal block P4 is connected to the 24V DC voltage output terminal.

7. An isolated SBUS signal conversion circuit according to claim 1, characterized in that, The power isolation circuit includes a first buck circuit, a second buck circuit, and an isolation circuit; The input end of the first buck circuit is connected to the power supply, the output end of the first buck circuit is connected to the input end of the second buck circuit, and the output end of the second buck circuit is connected to the power supply terminals of the inverter circuit, the microcontroller, and the signal isolation circuit; The input end of the isolation circuit is connected to the output end of the first buck circuit, and the output end of the isolation circuit is connected to the power supply terminal of the signal isolation circuit.

8. An isolated SBUS signal conversion circuit according to claim 7, characterized in that, The first buck circuit includes a third chip U3, and the third chip U3 includes an RT7272BGSP chip.

9. The isolated SBUS signal conversion circuit according to claim 7, wherein The second buck circuit includes a fifth chip U5, and the fifth chip U5 includes an LM1117IMPX-3.3 / NOPB chip.

10. A isolated SBUS signal conversion circuit according to claim 7, characterized in that, The isolation circuit includes a seventh chip U7, and the seventh chip U7 includes a B0505S-1WR3 chip; The first pin of the seventh chip U7 is divided into two paths, one path is grounded and the other path is connected to one end of the sixteenth capacitor C16; the second pin of the seventh chip U7 is divided into two paths, one path is connected to the +5V voltage output terminal of the first buck circuit and the other path is connected to the other end of the sixteenth capacitor C16; the third pin of the seventh chip U7 is divided into two paths, one path is connected to the isolated ground and the other path is connected to one end of the seventeenth capacitor C17; the fourth pin of the seventh chip U7 is divided into two paths, one path is the 5V isolated voltage output terminal and the other path is connected to the other end of the seventeenth capacitor C17.

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