Electronic component

Abstract

The utility model provides an electronic component, and the electronic component comprises a power component which is disposed on a carrier plate; the connecting element is arranged on the carrier plate and exposes the external contact of the carrier plate; a first cladding layer covering the power element and exposing the connecting element; a pin partially embedded in the connecting element and electrically connected with the external contact of the carrier plate and partially protruding from the first coating layer; and the second coating layer is filled in a gap between the pin and the first coating layer. According to the invention, the plastic package material is injected into the mold in an injection molding manner to form the first coating layer, and then the gap between the pin and the first coating layer is filled with the potting material in a potting manner, so that sites such as dispensing and screw locking are not needed, the potting process can be simplified, and the time of the potting process can be shortened.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and specifically relates to an electronic component. Background Art

[0002] The existing potting process requires preparing an outer frame to load the potting material. Specifically, first, the outer frame and the product substrate are combined through a temporary dispensing process, then fixed by screwing, and finally, the potting material is poured into the outer frame for encapsulation by potting. After the potting is completed, the outer frame is removed.

[0003] However, this method requires stations such as dispensing and screwing, and the entire potting process is relatively cumbersome and time-consuming. Summary of the Utility Model

[0004] This application proposes an electronic component.

[0005] In a first aspect, this application provides an electronic component, including: a power component disposed on a carrier board; a connection component disposed on the carrier board and exposing external connection points of the carrier board; a first coating layer covering the power component and exposing the connection component; pins, partially embedded in the connection component and electrically connecting the external connection points of the carrier board and partially protruding from the first coating layer; a second coating layer filled in the gap between the pins and the first coating layer.

[0006] In some optional embodiments, the first coating layer exposes a part other than the external connection points of the carrier board.

[0007] In some optional embodiments, the first coating layer includes grooves, and the first coating layer exposes a plurality of the connection components through the grooves.

[0008] In some optional embodiments, there are a plurality of the pins, and the second coating layer continuously coats a plurality of the connection components and the plurality of pins in the grooves.

[0009] In some optional embodiments, the first coating layer includes a plurality of groove arrays arranged.

[0010] In some optional embodiments, a plurality of the grooves surround the power component.

[0011] In some optional embodiments, the second coating layer coats the periphery of the connection component.

[0012] In some optional embodiments, the second coating layer covers the upper surface of the connection component.

[0013] In some optional embodiments, the power component is separated by the first coating layer and the grooves.

[0014] In some alternative embodiments, the height of the pin is greater than the height of the first coating layer.

[0015] To solve the problem that in the potting process, operations such as dispensing and screwing are required at certain stations, resulting in a relatively cumbersome and time-consuming overall potting process, the present application proposes an electronic component. By means of injection molding, a plastic encapsulation

[0016] material is injected into a mold to form a first coating layer, and then a potting material is filled into the gap between the pin and the first coating layer by means of potting. In this way, the potting process can be simplified and the time of the potting process can be shortened. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features, objects, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings:

[0018] Figure 1 is a schematic structural diagram of an existing electronic component;

[0019] Figures 2 - 6 is a schematic diagram of the potting process steps of an existing electronic component;

[0020] Figure 7 is a schematic structural diagram of an embodiment 7a of the electronic component according to the present application;

[0021] Figures 8 - 12 is a schematic diagram of the manufacturing steps of an embodiment 7a of the electronic component according to the present application.

[0022] REFERENCE SIGNS / SYMBOL DESCRIPTION:

[0023] 101 - Substrate; 102 - Power element; 103 - Sleeve; 104 - Pin; 105 - Adhesive material; 106 - Outer frame; 107 - Screw; 201 - Power element; 202 - Carrier board; 203 - Connecting element; 204 - Pin; 205 - First coating layer; 206 - Second coating layer; 2051 - Groove; 2052 - Upper surface of the first coating layer; 2061 - Upper surface of the second coating layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The following describes the specific embodiments of the present application in conjunction with the drawings and embodiments. Those skilled in the art can easily understand the technical problems solved by the present application and the technical effects produced through the content recorded in this specification. It can be understood that the specific embodiments described herein are only used to explain the related invention and are not intended to limit the invention. In addition, for the sake of description, only parts related to the relevant invention are shown in the drawings.

[0025] It should be readily understood that the meanings of "on", "above", and "over" in this application should be interpreted in the broadest sense, such that "on" not only means "directly on something", but also means "on something" including the presence of intermediate components or layers therebetween.

[0026] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component shown in the drawings. In addition to the orientation depicted in the figures, the spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented otherwise (rotated 90° or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0027] The term "layer" as used herein refers to a portion of material that includes a region having a certain thickness. The layer may extend over the entire underlying or overlying structure, or may have an extent less than that of the underlying or overlying structure. In addition, the layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may

[0028] be a layer, may include one or more layers therein, and / or may have one or more layers thereon, thereabove, and / or therebelow. A layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers and may have the same or different materials.

[0029] The term "substrate" as used herein refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or a sapphire wafer, etc. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0030] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content described in the specification for the understanding and reading of those skilled in the art, and are not used to limit the implementation conditions of this application. Therefore, they do not have substantial technical significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that this application can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in this application. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of clear narration and are not used to limit the scope of implementation of this application. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope within which this application can be implemented.

[0031] It should also be noted that the longitudinal section corresponding to the embodiment of this application can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0032] In addition, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The following will detail this application with reference to the drawings and in combination with the embodiments.

[0033] As Figure 1 shown, Figure 1 is a schematic structural diagram of an existing electronic component.

[0034] As Figure 1 shown, the electronic component includes a substrate 101, a power component 102, a sleeve 103, pins 104, and a glue material 105.

[0035] Among them, the power component 102 and the sleeve 103 are arranged on the substrate 101, the pins 104 are arranged to be partially embedded in the sleeve 103, the glue material 105 covers the power component 102 and the sleeve 103, and the pins 104 partially protrude from the glue material 105.

[0036] As Figures 2 - 6 shown, Figures 2 - 6 is a schematic diagram of the potting process steps of an existing electronic component.

[0037] Referring to Figure 2 , a substrate 101, a power component 102, a sleeve 103, and pins 104 are provided.

[0038] The power component 102 and the sleeve 103 are arranged on the substrate 101, and the pins 104 are partially embedded in the sleeve 103.

[0039] Referring to Figure 3 , an external frame 106 is provided.

[0040] Referring toFigure 4 , dispense glue to bond the outer frame 106 and the substrate 101 together.

[0041] Reference Figure 5 , provide screws 107 to further fix the outer frame 106 and the substrate 101.

[0042] Reference Figure 6 , pour the encapsulant 105 into the outer frame 106 for potting, so that the encapsulant 105 covers the power component 102 and the sleeve 103, and remove the outer frame 106 after the potting is completed.

[0043] In this way, since multiple processes such as dispensing glue, screwing, and removing the outer frame are required, the overall potting process is relatively cumbersome and time-consuming.

[0044] Reference Figure 7 , Figure 7 is a schematic structural diagram of an embodiment 7a of an electronic component according to the present application.

[0045] As Figure 7 shown, the electronic component of the present application includes a power component 201, a carrier board 202, a connection component 203, pins 204, a first coating layer 205, and a second coating layer 206. Among them, the power component 201 is disposed on the carrier board 202; the connection component 203 is disposed on the carrier board 202 and exposes the external connection points of the carrier board 202; the first coating layer 205 covers the power component 201 and exposes the connection component 203; the pins 204 are partially embedded in the connection component 203 and are electrically connected to the external connection points of the carrier board 202 and partially protrude from the first coating layer 205; the second coating layer 206 fills the gap between the pins 204 and the first coating layer 205.

[0046] Reference Figure 8 , here, the connection component 203 can be, for example, a sleeve, and the external connection points of the carrier board 202 can refer to the pads located on the carrier board 202.

[0047] The first coating layer 205 can be formed by injecting a plastic encapsulation material into a mold by injection molding, and the first coating layer 205 has a shape matching the inner surface of the mold.

[0048] The pins 204 can be partially embedded in the connection component 203. Specifically, the bottom of the end of the pins 204 embedded in the connection component 203 can contact the external connection points of the carrier board 202, realizing the electrical connection between the pins 204 and the external connection points of the carrier board 202. At the same time, it can play a role in initially fixing the position of the pins 204.

[0049] In some alternative embodiments, the height of pin 204 is greater than the height of the first encapsulation layer 205. In this way, when a part of pin 204 is embedded in the connection element 203, there may be a part of pin 204 that is not embedded in the connection element 203 protruding from the first encapsulation layer 205.

[0050] The second encapsulation layer 206 can fill the gap between the pin 204 and the first encapsulation layer 205 with potting material by potting.

[0051] In some alternative embodiments, the materials of the first encapsulation layer 205 and the second encapsulation layer 206 can be different.

[0052] The curing time of the first encapsulation layer 205 can be less than the curing time of the second encapsulation layer 206.

[0053] In this way, the potting process does not require stations such as dispensing and screwing. The entire potting process is relatively simple, which can save the time of the potting process. And, since the first encapsulation layer 205 occupies most of the area, but its curing time is fast, although the second encapsulation layer 206 has a slow curing time, it only fills the gap between the pin 204 and the first encapsulation layer 205, which can further shorten the time of the potting process. In addition, since the first encapsulation layer 205 is formed by injection molding, problems such as bubbles and voids are likely to occur. While the second encapsulation layer 206 is formed by potting, it can fill into every corner of the product and is more firm and reliable. In this way, while shortening the filling process time, the stability and reliability of the electronic components can be ensured, and, through the second encapsulation layer 206, the second fixing and stabilizing of the position of the pin 204 can also be achieved.

[0054] In some alternative embodiments, a part of the first encapsulation layer 205 exposes outside the external contact points of the carrier board 202.

[0055] Here, a part of the first encapsulation layer 205 exposing outside the external contact points of the carrier board 202 may mean that there is a certain interval between the first encapsulation layer 205 and the outer sidewall of the connection element 203, and the first encapsulation layer 205 does not

[0056] contact the connection element 203. In this way, it can be ensured that the potting material fills the gap between the pin 204 and the first encapsulation layer 205 to fully contact the connection element 203, ensuring the stability and reliability of the electronic components, and the second fixing and stabilizing of the position of the pin 204 is carried out through the second encapsulation layer 206.

[0057] In some alternative embodiments, there can be multiple connection elements 203 arranged around the power element 201.

[0058] In some alternative embodiments, there can also be multiple power elements 201.

[0059] For example, a plurality of connection elements 203 may be disposed around the left and right sides of the plurality of power elements 201.

[0060] In some alternative embodiments, the first coating layer 205 includes grooves 2051, and the first coating layer 205 exposes at least one connection element 203 through the grooves 2051. By providing the grooves 2051, it is possible to prevent the first coating layer 205 from overflowing and thus contacting the plurality of connection elements 203.

[0061] In some alternative embodiments, there may be a plurality of pins, and the second coating layer 206 may continuously coat the plurality of connection elements 203 and the plurality of pins 204 in the grooves 2051, and the positions of the pins 204 can be secondarily fixed and stabilized.

[0062] In some alternative embodiments, the number of connection elements 203 may be the same as the number of pins 204, and each connection element 203 may be embedded with a pin 204.

[0063] In some alternative embodiments, the second coating layer 206 covers the upper surface of the connection element 203. Thus, the second coating layer 206 can directly contact the pin 204 to strengthen the fixation of the position of the pin 204.

[0064] In some alternative embodiments, the plurality of pins 204 in the grooves 2051 may transmit signals of different functions.

[0065] In some alternative embodiments, the first coating layer 205 may include a plurality of grooves arranged in an array.

[0066] In some alternative embodiments, a plurality of grooves 2051 are disposed around the power element.

[0067] For example, a plurality of grooves 2051 may be disposed around the left and right sides of the power element 201.

[0068] Here, one groove 2051 may expose at least one connection element 203.

[0069] In some alternative embodiments, at least one connection element 203 exposed through the same groove 2051 may be equidistantly distributed. Thus, the overall stability of the electronic component can be improved, and the performance and reliability of the electronic component can be enhanced.

[0070] In some alternative embodiments, the second coating layer 206 coats the periphery of the connection element 203.

[0071] Here, the second coating layer 206 coating the periphery of the connection element 203 can play a role in protecting the connection element 203.

[0072] In some alternative embodiments, the upper surface 2052 of the first coating layer 205 and the upper surface 2061 of the second coating layer 206 are flush with each other.

[0073] In some alternative embodiments, the diameter of the cross-section of the pin 204 is not greater than the inner diameter of the cross-section of the connecting element 203.

[0074] Specifically, the diameter of the cross-section of the pin 204 may be equal to or slightly less than the inner diameter of the cross-section of the connecting element 203. In this way, when the pin 204 is embedded in the connecting element 203, the gap between the inner side surface of the pin 204 and the connecting element

[0075] 203 is very small, and the pin 204 can be in direct contact with the connecting element 203, with almost no gap between the two, which can enable the connecting element 203 to better fix the position of the pin 204.

[0076] In some alternative embodiments, the power element 201 is separated from the first coating layer 205 by the groove 2051.

[0077] Above, an embodiment 7a of the electronic device of the present application has been introduced.

[0078] Reference Figures 8 - 12 , Figures 8 - 12 is a schematic diagram of the manufacturing steps of an embodiment 7a of the electronic component according to the present application.

[0079] Reference Figure 8 , a power element 201, a carrier board 202, and a connecting element 203 are provided.

[0080] Among them, the power element 201 is disposed on the carrier board 202, and the connecting element 203 is disposed on the carrier board 202 and exposes the external contact points of the carrier board 202.

[0081] The connecting element 203 may be, for example, a sleeve, and the external contact points of the carrier board 202 may refer to the pads located on the carrier board 202.

[0082] Here, a plurality of connecting elements 203 may be disposed around the power element 201. At the same time, a plurality of power elements 201 may also be included.

[0083] For example, a plurality of connecting elements 203 may be disposed on the left and right sides of the power element 201.

[0084] Reference Figure 9 , a first coating layer 205 is provided.

[0085] The first coating layer 205 covers the power element 201 and exposes the connecting element 203.

[0086] The plastic encapsulation material can be injected into the mold by injection molding to form the first encapsulation layer 205, and the first encapsulation layer 205 has a shape matching the inner surface of the mold.

[0087] Among them, the first encapsulation layer 205 includes grooves 2051, and the connection element 203 is exposed through the grooves 2051 of the first encapsulation layer. At least one connection element 203 can be exposed through one groove 2051.

[0088] Here, the first encapsulation layer 205 can include a plurality of grooves 2051 arranged in an array. For example, a plurality of grooves 2051 can be arranged around the left and right sides of the power element 201.

[0089] Here, at least one connection element 203 exposed through the same groove 2051 can be equidistantly distributed. In this way, the overall stability of the electronic component can be improved, and the performance and reliability of the electronic component can be improved.

[0090] Reference Figure 10 and Figure 11 , pins 204 are provided.

[0091] Here, the pins 204 can be partially inserted into the connection elements 203 to achieve partial embedding of the pins 204 into the connection elements.

[0092] Here, the first encapsulation layer 205 can expose the connection element 203 through the groove 2051. Then, the pins 204 can be inserted into the connection element 203. Specifically, the bottom of one end of the pins 204 embedded in the connection element 203 can contact the external contact pins 204 of the carrier board 202, realizing electrical connection of the pins 204 to the external contacts of the carrier board 202 and partially protruding from the first encapsulation layer 205. By partially embedding the pins 204 into the connection element 203, the first position fixing effect on the pins can be achieved.

[0093] Reference Figure 12 , a second encapsulation layer 206 is provided.

[0094] Here, the potting material can be introduced into the groove 2051 to form the second encapsulation layer 206, and the second encapsulation layer 206 fills the gap between the pins 204 and the first encapsulation layer 205.

[0095] The materials of the first encapsulation layer 205 and the second encapsulation layer 206 can be different.

[0096] The curing time of the first encapsulation layer 205 can be less than the curing time of the second encapsulation layer 206.

[0097] Thus, the potting process does not require stations such as dispensing and screwing. The entire potting process is relatively simple, which can save the time of the potting process. Moreover, since the first coating layer 205 occupies most of the area but has a relatively fast curing time, although the second coating layer 206 has a relatively slow curing time, it only fills the gap between the pins 204 and the first coating layer 205, which can further shorten the time of the potting process. In addition, since the first coating layer 205 is formed by injection molding, problems such as bubbles and voids are likely to occur. However, the second coating layer 206 is formed by potting and can fill into every corner of the product, making it more firm and reliable. In this way, while shortening the filling process time, the stability and reliability of the electronic components can be ensured. Also, the second coating layer 206 can be used to achieve the second fixation and stabilization of the positions of the pins 204.

[0098] Although the present application has been described and illustrated with reference to specific embodiments of the present application, such description and illustration do not limit the present application. It will be clearly understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of the present application as defined by the appended claims. The drawings may not necessarily be drawn to scale. Due to variables in the manufacturing process and so on, there may be differences between the technical reproduction and the actual implementation in the present application. There may be other embodiments of the present application that are not specifically described. The specification and the drawings should be regarded as illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objectives, spirit, and scope of the present application. All such modifications fall within the scope of the appended claims herein. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered without departing from the teachings of the present application to form equivalent methods. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present application.

Claims

1. An electronic component, characterized in that, Comprising: A power component, disposed on a carrier board; A connecting component, disposed on the carrier board and exposing external connection points of the carrier board; A first coating layer, covering the power component and exposing the connecting component; A pin, partially embedded in the connecting component and electrically connected to the external connection points of the carrier board and partially protruding from the first coating layer; A second coating layer, filling a gap between the pin and the first coating layer.

2. The electronic component according to claim 1, characterized in that, The first coating layer exposes a part other than the external connection points of the carrier board.

3. The electronic component according to claim 1, wherein The first coating layer includes grooves, and the first coating layer exposes a plurality of the connecting components through the grooves.

4. The electronic component according to claim 3, characterized in that, There are a plurality of the pins, and the second coating layer continuously covers a plurality of the connecting components and a plurality of the pins in the grooves.

5. The electronic component according to claim 1, characterized in that, The first coating layer includes a plurality of groove arrays arranged.

6. The electronic component according to claim 5, wherein, A plurality of the grooves surround the power component.

7. The electronic component according to claim 1, characterized in that, The second coating layer covers the periphery of the connecting component.

8. The electronic component according to claim 1, characterized in that, The second coating layer covers the upper surface of the connecting component.

9. The electronic component according to claim 3, characterized in that, The power component is separated by the first coating layer and the grooves.

10. The electronic component according to claim 1, wherein The height of the pin is greater than the height of the first coating layer.

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