Packaging structure

Abstract

Some embodiments of the present application provide a package structure, comprising: a substrate; a first electronic element disposed on the substrate; a second electronic component disposed on the back surface of the first electronic component, the second electronic component including a back surface facing the first electronic component and an active surface opposite to the back surface of the second electronic component; a first encapsulation layer encapsulating the first electronic element and the second electronic element; and a first via disposed on the substrate, where the first via extends within the first encapsulation layer and is electrically connected to the second electronic component through the active surface of the second electronic component. The packaging structure with good bonding performance is provided by using the first through hole.

Description

Technical Field

[0001] Embodiments of the present application relate to a packaging structure. Background Art

[0002] In existing packaging structures, referring to Figure 1A and Figure 1B , the bilateral I / O (input / output) substrate die 11 disposed on a substrate (such as the substrate 14 shown in Figure 1C and Figure 1D ) usually uses a through-substrate via (TSV) 11V as a conduction channel for upper and lower components (such as a substrate 14 and a die 12). Considering the path length of the through-substrate via (TSV) 11V, the die 11 will be thinned to reduce the path of the through-substrate via (TSV) 11V to improve the electrical transmission efficiency. However, when stacking components (such as a die 12) on the substrate die 11 after thinning (for example, by hybrid bonding (HBI)) to form a packaging structure 10, the substrate die 11 may break at C due to the operating force of bonding the die 12.

[0003] The following will refer to Figure 1C and Figure 1D to describe in detail the formation of the break C at the thinned substrate die 11 (which may also be a thinned redistribution structure (RDL)). Referring to Figure 1C , the thinned substrate die 11 attached to the carrier 15 is bonded to the substrate 14 (such as a redistribution structure). Since the thinned substrate die 11 is thinner, the edge S of the thinned substrate die 11 (or the thinned RDL) is deformed. Then, as shown in Figure 1D , after bonding the die 12 to the substrate die 11, the problem of break C may occur in the substrate die 11. It can be seen that in the case of forming a packaging structure 10 (such as FOSUB (fan-out substrate)) from a thinned substrate die 11 (thin RDL) to a thicker die 12 (thick RDL), in single-unit manufacturing, both of these (the thinned substrate die 11 and the die 12) usually result in poor electrical performance, and solder necking or break C problems may occur in the substrate die 11, or the edge S of the thinned substrate die 11 may be deformed.

[0004] Specifically, during the formation of a packaging structure 10 such as a FOSUB (Fan-Out Substrate), the base die 11 needs to be attached to the carrier 15, which results in a relatively high cost. Additionally, the bumps 13 of the base die 11 need to be precisely bonded to form a fine fan-out RDL (FORDL) bond between the base 14 and the base die 11. After the carrier 15 is removed (released), defects are formed in the packaging structure such as a FOSUB (Fan-Out Substrate), such as deformation of the edge S of the base die 11. Subsequently, the die 12 and the base die 11 are bonded through a front-to-front hybrid bonding, which may cause incorrect connections between the thinned base die 11 and the die 12. It may also cause problems such as solder necking or fracture C in the base die 11, or deformation of the edge S of the thinned base die 11 as described above. In the above packaging structure 10, the thickness of each thinned base die 11 is between approximately 3μm and 10μm. Due to the deformation of the thinned base die 11 during and after the soldering process, the edge S of the thinned base die 11 does not have sufficient stiffness to support, resulting in problems such as solder necking or fracture C in the base die 11 or deformation of the edge S of the thinned base die 11 during subsequent bonding processes. Therefore, there is a need to provide a packaging structure with better bonding performance. Summary of the Utility Model

[0005] The present application provides a packaging structure with better bonding performance by using enhanced components and vias extending through corresponding electronic components.

[0006] Some embodiments of the present application provide a packaging structure, including: a substrate; a first electronic component disposed on the substrate; a second electronic component disposed on the back surface of the first electronic component, the second electronic component including a back surface facing the first electronic component and an active surface opposite to the back surface of the second electronic component; a first encapsulation layer encapsulating the first electronic component and the second electronic component; and a first via disposed on the substrate, wherein the first via extends within the first encapsulation layer and is electrically connected to the second electronic component through the active surface of the second electronic component.

[0007] In some embodiments, the first via extends through the first encapsulation layer.

[0008] In some embodiments, in a first direction in which the first electronic component and the second electronic component are stacked, the depth of the first via is greater than the sum of the thicknesses of the first electronic component and the second electronic component.

[0009] In some embodiments, the first via passes through the first encapsulation layer and extends to the surface of the first electronic component facing the second electronic component.

[0010] In some embodiments, the aspect ratio of the first through-hole is less than 0.5.

[0011] In some embodiments, in the first direction in which the first electronic component and the second electronic component are stacked, the thickness of the second electronic component is less than the thickness of the first electronic component.

[0012] In some embodiments, the package structure further includes:

[0013] A second encapsulation layer located on the active surface of the second electronic component,

[0014] wherein a second through-hole is provided in the second encapsulation layer, and the second through-hole is electrically connected to the active surface of the second electronic component.

[0015] In some embodiments, in a second direction perpendicular to the first direction in which the first electronic component and the second electronic component are stacked, the width of the second electronic component is less than or greater than the width of the first electronic component.

[0016] In some embodiments, the second electronic component is bonded to the first electronic component by hybrid bonding.

[0017] In some embodiments, a plurality of the second electronic components are bonded side by side to a single first electronic component, wherein the plurality of second electronic components are spaced apart from each other by a gap.

[0018] In some embodiments, a plurality of the second electronic components are bonded to corresponding plurality of the first electronic components, wherein the stacks formed by the second electronic components and the corresponding first electronic components are spaced apart from each other.

[0019] In some embodiments, in the first direction in which the first electronic component and the second electronic component are stacked, the first through-hole has a tapered shape.

[0020] In some embodiments, the first through-hole is directly connected to the second through-hole.

[0021] In some embodiments, the package structure further includes:

[0022] A pad stack provided on the second through-hole,

[0023] wherein the first through-hole is directly connected to the pad stack.

[0024] In some embodiments, the first encapsulation layer fills the gap.

[0025] In some embodiments, the package structure further includes:

[0026] A third encapsulation layer surrounds the plurality of second electronic components and fills the gap.

[0027] In some embodiments, the encapsulation structure further includes:

[0028] A third electronic component is disposed on the substrate and on a side of the first via opposite to the first electronic component and the second electronic component, wherein the third electronic component is encapsulated by the fixing layer,

[0029] wherein, a top surface of the fixing layer protrudes from a top surface of the first encapsulation layer or is flush with the top surface of the first encapsulation layer.

[0030] Some other embodiments of the present application provide an encapsulation structure, including: a substrate; a first electronic component disposed on the substrate; a second electronic component disposed on the first electronic component, the second electronic component including a back surface facing the first electronic component and an active surface opposite to the back surface; and a connector electrically connecting the substrate to the active surface of the second electronic component, wherein the connector extends across the first electronic component and the second electronic component and is connected to the substrate.

[0031] In some embodiments, the encapsulation structure further includes:

[0032] An encapsulation layer encapsulates the first electronic component, the second electronic component, and the connector,

[0033] wherein the connector is a first via that extends through the first encapsulation layer, and wherein, in a first direction in which the first electronic component and the second electronic component are stacked, a depth of the first via is greater than a sum of thicknesses of the first electronic component and the second electronic component.

[0034] In some embodiments, the connector is a bonding lead that directly extends from the substrate above the second electronic component.

[0035] The present application can provide a need for the first via as a power supply via by thinning the thick first electronic component as a base die, providing an electrical benefit. In the present application, a height of the first via as a power supply via is greater than a total height of the first electronic component and the second electronic component. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of the various components can be increased or decreased arbitrarily.

[0037] Figures 1A to 1DShows a packaging structure of the prior art.

[0038] Figures 2 to 9B Shows a packaging structure of some embodiments of the present application.

[0039] Figures 10 to 49 Shows a forming process of a packaging structure of some embodiments of the present application. Detailed implementation manners

[0040] The following disclosure provides many different embodiments or examples for implementing different features of the present utility model. Specific examples of components and arrangements are described below to simplify the present utility model. Of course, these are merely examples and are not intended to limit the present utility model. In addition, when a numerical value or a numerical range is described by terms such as "substantially", "about", "substantially", "essentially", etc., unless otherwise specified, the term is intended to cover numerical values within ±10% of the described numerical value. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm.

[0041] Refer to Figure 2 , some embodiments of the present application provide a packaging structure 100, and the packaging structure 100 includes: a substrate 101; a first electronic component 102 disposed on the substrate 101; a second electronic component 103 disposed on the back surface 102b of the first electronic component 102, and the second electronic component 103 includes a back surface 103b facing the first electronic component 102 and an active surface 103s opposite to the back surface 103b of the second electronic component 103; a first encapsulation layer 104 encapsulating the first electronic component 102 and the second electronic component 103; and a first through hole 105 disposed on the substrate 101, wherein the first through hole 105 extends within the first encapsulation layer 104 and is electrically connected to the second electronic component 103 through the active surface 103s of the second electronic component 103. In some embodiments, the first through hole 105 extends through the first encapsulation layer 104. In some embodiments, the second electronic component 103 is bonded to the first electronic component 102 by hybrid bonding. Specifically, the back surface 103b of the second electronic component 103 is bonded to the back surface 102b of the first electronic component 102 by hybrid bonding. In the first direction D in which the first electronic component 102 and the second electronic component 103 are stacked, as Figure 2A shown, Figure 2A shows a simplified view of the first electronic component 102 and the second electronic component 103, and the thickness h2 of the second electronic component 103 is less than the thickness h1 of the first electronic component 102. In some embodiments, a seed layer 105s is disposed between the first through hole 105 and the first encapsulation layer 104.

[0042] In addition, in Figure 2In a second direction H perpendicular to the first direction D as shown, the width of the second electronic component 103 is smaller than the width of the first electronic component 102, and a plurality of second electronic components 103 are attached to the first electronic component 102. Specifically, a plurality of second electronic components 103 are joined side by side to a single first electronic component 102, wherein the plurality of second electronic components 103 are spaced apart by a gap G, and a first encapsulation layer 104 is filled into the gap G and fills the gap G. Further as Figure 2 shown, a redistribution structure 108 is provided at the active surface 102s of the first electronic component 102 opposite to the back surface 102b. In this redistribution structure 108, there are a plurality of dielectric layers 108I and a plurality of metal lines 108M disposed in the dielectric layers 108I and vias 108V interconnecting the plurality of metal lines 108M. In the present application, the dielectric layer 108I may include, but is not limited to, polyimide (PI), which can be used to form a reinforcing structure. The metal lines 108M and the vias 108V may include, but are not limited to, metals such as copper.

[0043] Furthermore, Figure 2B shows Figure 2 an enlarged view of region A, and Figure 2C shows Figure 2B an enlarged view of region A'. It can be seen from Figure 2B and Figure 2C that the first electronic component 102 is joined to the second electronic component 103 through pads 102P at its back side (back surface 102b) and pads 103P at the back side (back surface 103b) of the second electronic component 103, thereby achieving back-to-back joining of the first electronic component 102 and the second electronic component 103. In addition, from Figure 2BIt can be further seen that the pad 102P at the back 102b of the first electronic component 102 is connected to the pad 102P2 at the active surface 102s of the first electronic component 102 through a through-hole 102V inside it, and the pad 102P2 is further connected to the metal line 108M and the via 108V in the underlying redistribution structure 108. Similarly, the pad 103P at the back 103b of the second electronic component 103 is connected to the pad 103P2 at the active surface 103s of the second electronic component 103 through a through-hole 103V inside it, and the pad 103P2 is further connected to the second via 106. Further, a seed layer 108s may exist between the pad 102P2 and the via 108V, and a seed layer 106s may exist between the pad 103P2 and the second via 106. In a further embodiment, the bonding between the pad 102P and the pad 103P is a hybrid bonding. It can be seen that the backside power pads 102P and 103P of the first electronic component 102 and the second electronic component 103 such as chips are bonded (hybrid bonding or wire bonding), which directly provides a thin structure of the package structure (PKG) 100 and has better electrical performance with the shortest circuit path. Therefore, the hybrid bonding or wire bonding structure provides a thinner overall package structure (PKG) 100 and lower cost. Compared with the solder interconnect, no additional redistribution structure manufacturing is required for the unit bonding pads (such as pads 102P and 103P).

[0044] In some embodiments, as Figure 2 shown, in the first direction D in which the first electronic component 102 and the second electronic component 103 are stacked, the depth of the first via 105 is greater than the sum of the thicknesses of the first electronic component 102 and the second electronic component 103. Further, in some embodiments, the aspect ratio of the first via 105 is less than 0.5, that is, the ratio of the height of the first via 105 in the first direction D to the width of the first via 105 at the top surface 104t of the first package layer 104 (the width in the second direction H perpendicular to the first direction D) is less than 0.5, because when it is within the range of less than 0.5, good filling of the first via 105 can be ensured.

[0045] Further referring to Figure 2 this, the package structure 100 further includes: a second package layer 107 located on the active surface 103s of the second electronic component 103, and from Figure 2As can be seen, a second through-hole 106 is provided in the second encapsulation layer 107, and the second through-hole 106 is electrically connected to the active surface 103s of the second electronic component 103. Specifically, the second through-hole 106 extends through the second encapsulation layer 107 to contact the active surface 103s of the second electronic component 103. Further, at the top surface 104t of the first encapsulation layer 104, the first through-hole 105 is directly connected to the second through-hole 106. In some embodiments, in the first direction D, the first through-hole 105 and the second through-hole 106 have a tapered shape. That is, the width gradually decreases from the top at the top surface 104t of the first encapsulation layer 104 to the bottom. Further, a pad stack 103bP is provided on the second through-hole 106, and the first through-hole 105 is directly connected to the pad stack 103bP.

[0046] Further referring to Figure 2 , the encapsulation structure 100 further includes: a third electronic component 109 disposed on the substrate 101, from Figure 2 As can be seen, the third electronic component 109 is located on the side of the first through-hole 105 opposite to the first electronic component 102 and the second electronic component 103, that is, the third electronic component 109 and the first electronic component 102 and the second electronic component 103 are respectively disposed on opposite sides of the first through-hole 105. Further, the third electronic component 109 is encapsulated by a fixing layer 110, from Figure 2 As can be seen, the top surface 110t of the fixing layer 110 protrudes from the top surface 104t of the first encapsulation layer 104.

[0047] Continuing to refer to Figure 2 , from Figure 2 As can be further seen, in the encapsulation structure 100, the redistribution structure is connected to the pad 101P1 at the top surface 101t of the substrate 101 through the micro-bumps 111, and the third electronic component 109 is connected to the pad 101P1 at the top surface 101t of the substrate 101 through the micro-bumps 112. Further, an external connector 113 is connected to the pad 101P2 at the bottom surface 101d of the substrate 101 opposite to the top surface 101t to make a connection to the outside. Further, the first through-hole 105 is also connected to the pad 101P1 at the top surface 101t of the substrate 101.

[0048] In the above encapsulation structure, the first electronic component 102 and the RDL 108 below it and the structure of the substrate 101 form a fan-out substrate (FOSUB-C) F, and the second electronic component 103 and the second encapsulation layer 107 above it form a control chip C. In a specific embodiment, the first electronic component 102 is an ultra-thin EIC (electronic integrated circuit), and the second electronic component 103 is an ultra-thin IVR (integrated voltage regulator).

[0049] In the present application, the back surfaces 102b of the first electronic component 102 and 103b of the second electronic component 103 are thinned to overcome and avoid edge problems at the edges S of the first electronic component 102 and the second electronic component 103 and the corresponding redistribution structure (RDL) 108, such as edge deformation problems. Further, the back surface 103b of the second electronic component 103 is bonded to the back surface 102b of the first electronic component 102, i.e., back-to-back (PBtB (fusion bonding)) between electronic components such as chips for hybrid bonding (HBI). This provides good performance applications in the dimensions of the thinned package structure 100 for miniaturization. In addition, the fan-out substrate F incorporates the RDL 108 (fan-out redistribution structure (FORDL)), the first electronic component 102, and the substrate 101, providing a good production structure (avoiding deformation or warping at the edge S of the RDL 108), because the thinned first electronic component 102 has a higher hardness than plastic. For example, an enhanced structure is formed using PI (polyimide) in the first electronic component 102.

[0050] Further, in the RDL 108 (FORDL), the designed fine metal lines 108M (e.g., L (width in the second direction H) / S (thickness in the first direction D) < 1um / 1um) can be used to benefit from sufficient I / O (input / output) applications. Further, the active surface 102s of the first electronic component 102 faces the substrate 101, which is beneficial for more efficient heat dissipation.

[0051] In summary, the overall WL (wafer-level) (or PNL (panel-level)) manufacturing of the package structure 100 can be used for low-cost solutions.

[0052] See Figure 3A and Figure 3B , Figure 3A and Figure 3B show enlarged views of different embodiments of the region B for Figure 2 For the pad stack 103bP of the package structure 100 shown in Figure 3A , the corresponding pads 103PP are stacked above the second vias 106 through the corresponding seed layers 103bPS to form the pad stack 103bP; while for Figure 3B the pad stack 103bP shown in

[0053] See Figure 4A and Figure 4B , Figure 4A the package structure 100-1 shown in Figure 4B and Figure 2 the package structure 100-2 shown inFigure 2 In the encapsulated structure 100 shown, the top surface 110t of the fixing layer 110 protrudes from the top surface 104t of the first encapsulation layer 104, and in Figure 4A in the encapsulated structure 100-1 shown, the top surface 110t of the fixing layer 110 is lower than the top surface 104t of the first encapsulation layer 104, and in Figure 4B in the encapsulated structure 100-2 shown, the top surface 110t of the fixing layer 110 is flush with the top surface 104t of the first encapsulation layer 104.

[0054] See Figure 5 , Figure 5 the encapsulated structure 100-3 shown is substantially the same as Figure 2 the encapsulated structure 100 shown, except that, in Figure 5 the encapsulated structure 100-3 shown, instead of multiple second electronic components 103 being bonded to a single first electronic component 102, multiple second electronic components 103 are respectively bonded to corresponding multiple first electronic components 102-1, 102-2, etc., where the stacks formed by the second electronic components 103 and the corresponding first electronic components 102-1 or 102-2 are spaced apart from each other.

[0055] See Figure 6A and Figure 6B , Figure 6A the encapsulated structure 100-4 shown and Figure 6B the encapsulated structure 100-5 shown are substantially the same as Figure 2 the encapsulated structure 100 shown, except that Figure 6A in the encapsulated structure 100-4 shown, a bonding lead 116 is used to connect the pad stack 103bP to the blind via 101P1 at the top surface 101t of the substrate 101 instead of using the first via 105. And in Figure 6B in the encapsulated structure 100-5 shown, the first via 105' and the corresponding seed layer 105s' are used instead of Figure 2 the first via 105 and the seed layer 105s shown, specifically, see Figure 6B , the first via 105' passes through the first encapsulation layer 104 and extends to the back surface 102b of the first electronic component 102 facing the second electronic component 103.

[0056] See Figure 7 , Figure 7 the encapsulated structure 100-6 shown is substantially the same as Figure 2 the encapsulated structure 100 shown, except that Figure 7In the encapsulated structure 100-5 shown, the wider second electronic component 103 is disposed above the narrower first electronic component 102, that is, a structure with a larger top (the second electronic component 103 is at the top) and a smaller bottom (the first electronic component 102 is at the bottom) is formed, which is different from Figure 2 the encapsulated structure 100 in which has a smaller top and a larger bottom. Further, in Figure 7 the second direction H perpendicular to the first direction D shown, the width of the second electronic component 103 is greater than the width of the first electronic component 102.

[0057] See Figure 8A and Figure 8B for Figure 8A the encapsulated structure 100-7 and Figure 8B the encapsulated structure 100-8 shown, which are substantially the same as the encapsulated structure 100 shown in Figure 2 . The difference is that in the encapsulated structure 100-7 shown in Figure 8A , there is a third encapsulation layer 114 that seals the second electronic component 103 and the second encapsulation layer 107. The third encapsulation layer 114 surrounds a plurality of second electronic components 103 and fills into the gap G. While in the encapsulated structure 100-8 shown in Figure 8B , there is a bottom filler 115 that fills the space between the redistribution structure 108 and the substrate 101, and the bottom filler 115 further extends into the gap G and fills part of the gap G. In some embodiments, the first encapsulation layer 104 includes, but is not limited to, molding compound, and the third encapsulation layer 114 includes, but is not limited to, pre-molded molding compound.

[0058] Further, as shown in Figure 9A and Figure 9B , the substrate 101 carrying the first electronic component 102 and the second electronic component 103 can be circular or square in shape, or any other suitable shape.

[0059] In addition, see Figure 2 , some other embodiments of the present application further provide an encapsulated structure 100, which includes: a substrate 101; a first electronic component 102 disposed on the substrate 101; a second electronic component 103 disposed on the first electronic component 102, the second electronic component 103 including a back surface 103b facing the first electronic component 102 and an active surface 103s opposite to the back surface 103b; and a connecting member that electrically connects the substrate 101 to the active surface 103s of the second electronic component 103, wherein the connecting member extends across the first electronic component 102 and the second electronic component 103 and is connected to the substrate 101. In some embodiments, the encapsulated structure 100 further includes an encapsulation layer 104 that encapsulates the first electronic component 102, the second electronic component 103, and the connecting member. In some embodiments, the connecting member isFigure 2 The first through-hole 105 shown, the first through-hole 105 extends through the first encapsulation layer 104, and in the first direction D in which the first electronic component 102 and the second electronic component 103 are stacked, the depth of the first through-hole 105 is greater than the sum of the thickness h1 of the first electronic component 102 and the thickness h2 of the second electronic component 103 (see Figure 2A ). In some embodiments, as Figure 6A shown, the connecting member is a bonding lead 116, and the bonding lead 116 extends directly from the substrate 101 above the second electronic component 103.

[0060] In the above packaging structure, the dielectric layer 108I, the second encapsulation layer 107, and the fixing layer 110 in the redistribution structure 108 include but are not limited to PI (polyimide), epoxy resin, ABF (Ajinomoto Build-up Film), pp (polypropylene), or / and acrylic resin or organic photosensitive or / and non-photosensitive liquid or / and dry film material. In addition, the materials of the first through-holes 105 / 105’, the second through-holes 106, the metal lines 108M and the through-holes 108V, the pads 102P-102P2, the pads 103P-103P2, and the pads 101P1-101P2 and the pad stack 103bP and other through-holes and pads include but are not limited to Cu, Au, Ag, Al, Pd, Pt, and Ni and their alloys. The seed layers 105s / 105s’, the seed layer 106s, and other seed layers include but are not limited to Ti, Ni, W, Pd, Pt, and their alloys. The through-holes 102V and 103V, etc. include but are not limited to W, Ti, Au, Cu, Ag, Pa, Pt, and their alloys. The micro-bumps 111 and 112 include but are not limited to solder, Cu, Au, Ag, Al, Pd, Pt, and Ni and their alloys. The external connecting member 113 includes but is not limited to solder, ACP (Anisotropic Conductive Paste) / ACF (Anisotropic Conductive Film), etc.

[0061] In addition, in the above packaging structure, the widths of the first electronic component 102 and the second electronic component 103 in the second direction H are in the range of dozens of micrometers to hundreds of micrometers, and see Figure 2A , the thickness h1 of the first electronic component 102 and the thickness h2 of the second electronic component 103 are in the range of 1 μm to 50 μm. In addition, the gap between the redistribution structure 108 and the substrate 101 is in the range of 2 μm to 30 μm, and the gap between the third electronic component 109 and the corresponding side walls of the first encapsulation layer 104 is in the range of 2 μm to 30 μm. In some embodiments, the thickness of the dielectric layer 108I closest to the substrate 101 in the redistribution structure 108 in the first direction D is in the range of 2 μm to 20 μm, and the overall thickness of the packages 100, 100-1 to 100-8 is in the range of 30 μm to 300 μm.

[0062] The following refers to Figures 10 to 49 to introduce Figure 2 the formation of the encapsulation structure 100 shown.

[0063] First, refer to Figures 10 to 24 to introduce the related formation process of the first electronic component 102. Refer to Figure 10 , a wafer 102' of the first electronic component is provided, such as an EIC die. The wafer 102' of the first electronic component has an active surface 102s and a back surface 102b opposite to the active surface 102s. Among them, pads 102P2 exist at the active surface 102s, and pads are also embedded in the wafer 102' of the first electronic component.

[0064] Refer to Figure 11 , a dielectric layer 108I covering the pads 102P2 is formed at the active surface 102s through a process such as coating, such as a polyamide (PA) layer. After that, the dielectric layer 108I is exposed P1, so as to expose the pads 102P2 under the dielectric layer 108I. After that, refer to Figure 12 , a seed layer 108s' such as copper is formed on the dielectric layer 108I and the pads 102P2, such as by physical vapor deposition (PVD). Next, refer to Figure 13 , a photoresist 1001 is formed above the seed layer 108s', and the photoresist 1001 is exposed and developed P2. Refer to Figure 14 , an opening 100O is formed in the photoresist 1001, and a metal layer such as copper is formed in the opening 1001O through a process such as electroless plating or electroplating, so as to form a metal wire 108M and a via 108V.

[0065] Next, refer to Figure 15 , the photoresist 1001 is removed, and the part of the seed layer 108s' not covered by the metal wire 108M and the via 108V is removed by etching and other methods, so as to form Figure 15 the structure shown. After that, refer to Figure 16 , a dielectric layer 108I is formed using a process similar to Figure 11 , and after that, the process of Figures 12 to 15 is repeated until the desired number of dielectric layers 108I, metal wires 108M and vias 108V are formed.

[0066] After the desired number of dielectric layers 108I and the corresponding metal wires 108M and vias 108V are formed, refer to Figure 17 , the topmost dielectric layer 108I is etched to expose part of the metal wire 108M. After the metal wire 108M is exposed, a seed layer 108s' is formed on the dielectric layer 108I. After the seed layer 108s' is formed, refer to Figure 18 and Figure 19, a photoresist 1002 is coated over the seed layer 108s’, and the photoresist is exposed and developed by P4 to form an opening 1002O that exposes the metal line 108M. After that, continue to refer to Figure 19 , a metal such as copper is plated in the opening 1002O through a plating process to form the top metal line 108M. Next, refer to Figure 20 , solder 111’ is continuously formed in the opening 1002O through a plating process.

[0067] After that, refer to Figure 21 and Figure 22 , the photoresist 1002 is removed, and the solder 111’ is formed into a desired shape through a reflow process R, thereby forming Figure 22 the microbump 111 (solder ball) shown. Refer to Figure 23 and Figure 24 , the obtained structure is cut and manufactured by a blade or the like, thereby forming Figure 22 the unit formed by the single first electronic component 102 and the corresponding redistribution structure 108 shown. Finally, the unit formed by the single first electronic component 102 and the corresponding redistribution structure 108 is stored for standby through a pushing process P5 such as a pick-and-place process. Figure 24

[0068] After that, the related formation process of the second electronic component 103 is introduced with reference to Figures 25 to 33 . Referring to Figure 25 , a wafer 103’ of the second electronic component is provided, such as an IVR die. The wafer 103’ of the second electronic component has an active surface 103s and a back surface 103b opposite to the active surface 103s, wherein pads 103P2 exist at the active surface 103s, and pads are also embedded in the wafer 103’ of the second electronic component.

[0069] Figure 26 Refer to , a second encapsulation layer 107 is manufactured on the active surface 103s through a molding process, such as using molding compound. After preparing the second encapsulation layer 107, as Figure 27 shown, an opening 107O that exposes the pad 103P2 is formed in the second encapsulation layer 107 through a laser drilling process P6, and after forming the opening 107O, a seed layer 106s’ is formed above the second encapsulation layer 107 and in the opening 107O through PVD. Next, refer to Figures 29 to 30 , a photoresist 1003 is formed on the seed layer 106S’, and the photoresist 1003 is exposed and developed to form corresponding openings at the pads 103P2. After that, a metal layer such as copper is plated in the openings through a plating process, thereby forming the second via 106 as Figure 30 shown.

[0070] Figures 31 to 33 Refer to Figures 31 to 33, the obtained structure is flipped, and the back side of the wafer 103' of the second electronic component is thinned by an etching process P8 such as wet etching commonly used in the art, thereby forming a wafer 103' of the thinned second electronic component as shown in Figure 30 . As shown in Figure 32 , the back side 103b of the thinned wafer 103' of the second electronic component exposes the pads 103P inside it. Then, the obtained structure is cut by a seven-cutting process such as a blade B2, thereby obtaining Figure 32 a single second electronic component 103 and a unit formed by a second encapsulation layer 107 and corresponding second vias 106 on its active surface 103s as shown in Figure 32 . Finally, the unit formed by the single second electronic component 103, the corresponding second encapsulation layer 107, and the corresponding second vias 106 is stored for standby through a pushing process P9 such as a pick-and-place process. Figure 33

[0071] Finally, with reference to Figures 34 to 49 , the formation process of the packaging structure 100 shown in Figure 2 is introduced. With reference to Figure 34 , a substrate 101 is provided, and the substrate 101 can be any suitable substrate such as a reinforced circuit board. The substrate 101 is provided with pads 101P1 at its top surface 101t and pads 101P2 at its bottom surface 101d.

[0072] With reference to Figure 35 , the unit formed by the first electronic component 102 and the redistribution structure 108 manufactured in Figure 24 is bonded to the substrate 101, that is, the micro-bumps 111 on the redistribution structure 108 are bonded to the corresponding pads 101P1.

[0073] After that, with reference to Figure 36 , underfilling may or may not be performed between the redistribution structure 108 and the substrate 101. Underfilling is performed using a material such as the first encapsulation layer 104, such as a molding compound, and is filled through a capillary flow process.

[0074] See Figure 37 , the back side of the first electronic component 102 is thinned by a chemical etching P10 such as wet etching commonly used in the art, so that the back side 102b of the first electronic component 102 is formed to expose the pads 102P inside it.

[0075] See Figure 38 and Figure 39 ​, after thinning the first electronic component 102, the second electronic component 103 is successively attached to the back surface 102b of the first electronic component 102, that is, the pad 103P of the second electronic component 103 is directly attached to the back surface 102b of the first electronic component 102, thereby completing the chip bonding manufacturing.

[0076] After that, referring to Figure 40 , a first encapsulation layer 104 is formed through a molding process, thereby encapsulating the first electronic component 102 and the second electronic component 103 therein. Referring to Figure 41 , an opening exposing the pad 101P1 is formed in the first encapsulation layer 104 around the first electronic component 102 and the second electronic component 103 through a laser drilling process P11. Next, referring to Figure 42 , a seed layer 105s is formed above the first encapsulation layer and in the opening. After that, referring to Figures 43 to 45 , a photoresist 1004 is formed above the seed layer 105s, the photoresist 1004 is exposed and developed, thereby forming an opening at the corresponding position of the pad 101P1, a metal layer is plated in the opening, thereby forming a first through-hole 105 and a corresponding pad stack 103bP, and finally, the portions of the photoresist layer 1004 and the seed layer 105s that are not covered by the first through-hole 105 and outside the pad stack 103bP are removed, thereby forming Figure 45 the structure shown.

[0077] Finally, referring to Figures 46 to 47 , the third electronic component 109 is bonded to the pad 101P1 of the substrate 101, and a fixing layer 110 is formed through underfill. After that, referring to Figure 48 , flip Figure 47 the obtained structure, and an external connection member 113 such as a solder ball is formed on the pad 101P2 on the bottom surface 101d of the substrate 101. Finally, as Figure 49 shown, it is formed through sawing Figure 2 the package structure 100 shown.

[0078] In the above method, the metal layer can be formed by methods such as PVD, electroplating, electroless plating, printing, potting metal, etc.

[0079] In summary, in the present application, first, the first electronic component (such as an EIC) 102 and the redistribution structure 108 are bonded onto the PNL (or WL) substrate 101 through micro-bumps 111 to form the fan-out substrate F. The multi-layer redistribution structure 108 is manufactured through electroplating and photolithography processes, and the first electronic component (such as an EIC) 102 is separated from the wafer 102' through dicing manufacturing. Secondly, the back surface 102b of the first electronic component (such as an EIC) 102 is chemically etched to expose the power pads 102P. In addition, an interconnect structure is formed by hybrid bonding the pads 102P on the back surface 102b of the first electronic component (such as an EIC) 102 to the pads 103P of the second electronic component (such as an IVR) 103. The front surface (active surface 103s) of the second electronic component (such as an IVR) 103 is manufactured before the backside chemical etching and has some vias. Finally, a first encapsulation layer 104 (molding compound, CPD) such as molding compound and the first vias 105 of the encapsulation structure 100 are formed. Then the third electronic component 109 (HBM) is bonded into the cavity on the substrate. After ball placement and dicing, the final encapsulation structure 100 is formed.

[0080] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present utility model. Those skilled in the art should understand that they can easily use the present utility model as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments illustrated herein. Those skilled in the art should also be aware that such equivalent constructs do not depart from the spirit and scope of the present utility model, and various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of the present utility model.

Claims

1. An encapsulation structure, characterized in that, Comprising: A substrate; A first electronic component disposed on the substrate; A second electronic component disposed on the back surface of the first electronic component, the second electronic component including a back surface facing the first electronic component and an active surface opposite to the back surface of the second electronic component; A first encapsulation layer encapsulating the first electronic component and the second electronic component; And A first through-hole disposed on the substrate, wherein the first through-hole extends within the first encapsulation layer and is electrically connected to the second electronic component through the active surface of the second electronic component.

2. The encapsulation structure according to claim 1, characterized in that The first through-hole extends through the first encapsulation layer.

3. The encapsulation structure according to claim 2, wherein In a first direction in which the first electronic component and the second electronic component are stacked, the depth of the first through-hole is greater than the sum of the thicknesses of the first electronic component and the second electronic component.

4. The encapsulation structure according to claim 1, wherein The first through-hole passes through the first encapsulation layer and extends to the surface of the first electronic component facing the second electronic component.

5. The encapsulation structure according to claim 1, characterized in that, The aspect ratio of the first through-hole is below 0.

5.

6. The encapsulation structure according to claim 1, wherein Further comprising: A second encapsulation layer located on the active surface of the second electronic component, wherein a second through-hole is provided in the second encapsulation layer, and the second through-hole is electrically connected to the active surface of the second electronic component.

7. The encapsulation structure according to claim 1, wherein In a second direction perpendicular to the first direction in which the first electronic component and the second electronic component are stacked, the width of the second electronic component is less than or greater than the width of the first electronic component.

8. The encapsulation structure according to claim 1, wherein A plurality of the second electronic components are joined side by side to a single first electronic component, wherein the plurality of second electronic components are spaced apart from each other by a gap.

9. The encapsulation structure according to claim 1, wherein A plurality of the second electronic components are joined to a corresponding plurality of the first electronic components, wherein the stacks formed by the second electronic components and the corresponding first electronic components are spaced apart from each other.

10. The encapsulation structure according to claim 6, wherein The first through-hole is directly connected to the second through-hole.

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