Multi-port output hardware protocol intelligent distribution circuit

Abstract

The utility model provides a multi-port output hardware protocol intelligent distribution circuit, which comprises a TypeC1 interface circuit, a TypeC2 interface circuit, a USBA interface circuit, a protocol chip U14 and an analog switch chip U15, the common end of the TypeC1 interface circuit, the TypeC2 interface circuit and the USBA interface circuit is connected with the protocol chip U14, the protocol chip U14 is connected with the analog switch chip U15, and by increasing the use of the analog switch protocol U15, the protocol chip U14 is connected with the analog switch chip U15. The problem that pin positions of a protocol chip U14 are not enough is solved, and meanwhile the fast charging function of a USBA interface is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of multi-port output circuits, and particularly to an intelligent distribution circuit for multi-port output hardware protocols. Background Art

[0002] With the rapid development of electronic technology, the functions of various electronic products such as mobile phones, digital cameras, e-readers, MP3 players, and MP4 players are becoming more and more powerful, resulting in an increasing demand for charging.

[0003] In today's society, consumers' demand for power supply is becoming more and more diverse. Especially in the field of charging devices, users hope that the same device can support the charging needs of multiple devices. However, traditional charging devices often only provide a single output port, or although they provide multiple output ports, there are problems in power distribution and cannot achieve intelligent and efficient distribution. With the rapid development of consumer electronic products, chargers or mobile power supplies have more and more functions. For chargers or mobile power supplies with multi-port fast charging, the CC signals and D+, D- signals of some cheap protocol chips on the market are not enough for multiple output ports, and this problem needs to be expanded and solved. Summary of the Utility Model

[0004] The purpose of the utility model is to provide an intelligent distribution circuit for multi-port output hardware protocols to solve the problems raised in the above background art.

[0005] The utility model is realized through the following technical solutions: An intelligent distribution circuit for multi-port output hardware protocols includes a TypeC1 interface circuit, a TypeC2 interface circuit, a USBA interface circuit, a protocol chip U14, and an analog switch chip U15. The common terminals of the TypeC1 interface circuit, the TypeC2 interface circuit, and the USBA interface circuit are connected to the protocol chip U14, and the protocol chip U14 is connected to the analog switch chip U15.

[0006] Specifically, the 18th and 19th pins of the protocol chip U14 are respectively connected to the corresponding pins of the analog switch chip U15. The 2nd and 8th pins of the analog switch chip U15 are respectively connected to the TypeC2 interface circuit, and the 3rd and 7th pins of the analog switch chip U15 are respectively connected to the USBA interface circuit.

[0007] Specifically, the TypeC1 interface circuit includes a female socket JP1, a first P-MOS transistor Q7, and a second P-MOS transistor Q8. The female socket JP1 is successively connected to the first P-MOS transistor Q7 and the second P-MOS transistor Q8, and the female socket JP1 is connected to the protocol chip U14.

[0008] Specifically, the Type-C2 interface circuit includes a female socket JP2, a third P-MOS transistor Q12, and a fourth P-MOS transistor Q11. The female socket JP2 is successively connected to the third P-MOS transistor Q1 and the fourth P-MOS transistor Q11, and the female socket JP2 is connected to the protocol chip U14.

[0009] Specifically, the USB-A interface circuit includes a female socket JP3, a fifth P-MOS transistor Q13, and a sixth P-MOS transistor Q14. The female socket JP3 is successively connected to the fifth P-MOS transistor Q13 and the sixth P-MOS transistor Q14, and the female socket JP3 is connected to the protocol chip U14.

[0010] Specifically, the protocol chip U14 is CS32G020 of Core Sea.

[0011] Specifically, the analog switch chip U15 is RX2228 of Run Shi.

[0012] Compared with the prior art, the beneficial effects achieved by the present utility model are as follows:

[0013] A multi-port output hardware protocol intelligent distribution circuit provided by the present utility model solves the problem of insufficient pin positions of the protocol chip U14 by increasing the use of the analog switch protocol U15. At the same time, the fast charging function of the USB-A interface is also realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only the preferred embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0015] Figure 1 It is a structural diagram of the Type-C1 interface circuit.

[0016] Figure 2 It is a structural diagram of the Type-C2 interface circuit.

[0017] Figure 3 It is a structural diagram of the USB-A interface circuit.

[0018] Figure 4 It is a structural diagram of the protocol chip U14.

[0019] Figure 5 It is a structural diagram of the analog switch chip U15. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] To make the objectives, technical solutions and advantages of the present invention more apparent, the exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments of the present invention. It should be understood that the present invention is not limited by the exemplary embodiments described herein. Based on the embodiments of the present invention described herein, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

[0021] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known to those skilled in the art are not described.

[0022] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0023] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. When used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the related listed items.

[0024] To thoroughly understand the present invention, detailed structures will be presented in the following description to illustrate the technical solutions proposed by the present invention. The alternative embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention can also have other implementation manners.

[0025] See Figures 1 to 5 , a multi-port output hardware protocol intelligent allocation circuit, including a TypeC1 interface circuit, a TypeC2 interface circuit, a USBA interface circuit, a protocol chip U14 and an analog switch chip U15. The common terminals of the TypeC1 interface circuit, the TypeC2 interface circuit and the USBA interface circuit are connected to the protocol chip U14, and the protocol chip U14 is connected to the analog switch chip U15.

[0026] Specifically, the 18th and 19th pins of the protocol chip U14 are respectively connected to the corresponding pins of the analog switch chip U15. The 2nd and 8th pins of the analog switch chip U15 are respectively connected to the TypeC2 interface circuit, and the 3rd and 7th pins of the analog switch chip U15 are respectively connected to the USBA interface circuit.

[0027] Specifically, refer to Figure 1 The TypeC1 interface circuit includes a female socket JP1, a first P-MOS transistor Q7, and a second P-MOS transistor Q8. The female socket JP1 is successively connected to the first P-MOS transistor Q7 and the second P-MOS transistor Q8, and the female socket JP1 is connected to the protocol chip U14.

[0028] Exemplarily, to prevent the CC signal from being interfered, there are filter capacitors C141 and C142 on the CC signal; DPA is the positive differential signal of the TypeC1 interface, DMA is the negative differential signal of the TypeC1 interface, and R153 is the output current detection resistor of the TypeC1 interface.

[0029] Specifically, refer to Figure 2 The TypeC2 interface circuit includes a female socket JP2, a third P-MOS transistor Q12, and a fourth P-MOS transistor Q11. The female socket JP2 is successively connected to the third P-MOS transistor Q1 and the fourth P-MOS transistor Q11, and the female socket JP2 is connected to the protocol chip U14.

[0030] Exemplarily, to prevent the CC signal from being interfered, there are filter capacitors C137 and C138 on the CC signal; DPB is the positive differential signal of the TypeC2 interface, DMB is the negative differential signal of the TypeC2 interface, and R152 is the output current detection resistor of the TypeC2 interface.

[0031] Specifically, refer to Figure 3 The USBA interface circuit includes a female socket JP3, a fifth P-MOS transistor Q13, and a sixth P-MOS transistor Q14. The female socket JP3 is successively connected to the fifth P-MOS transistor Q13 and the sixth P-MOS transistor Q14, and the female socket JP3 is connected to the protocol chip U14.

[0032] Exemplarily, USBA_DP is the positive differential signal of the USBA interface, USBA_DM is the negative differential signal of the USBA interface, and R60 is the output current detection resistor of the USBA interface.

[0033] Specifically, the protocol chip U14 is the CoreSea CS32G020.

[0034] Exemplarily, refer to Figure 4, the protocol chip U14 includes USBC1_Current current detection signal, USBC2_Current current detection signal, and USBA_Current current detection signal. These three signals are the current detection signals for three output ports respectively; CC1A and CC1B signals are the CC signals of the TypeC1 interface, CC2A and CC2B are the CC signals of the TypeC2 interface, SCL, SDA, and INT signals are all communication signals, NRST2, SWD2, and SWCLK signals are all programming pin signals, EN series signals are all enable signals of P-MOS transistors, and VDD3V3 is the power supply signal for the protocol chip U14.

[0035] Specifically, the analog switch chip U15 is Runshi RX2228.

[0036] Exemplarily, refer to Figure 5 , the analog switch chip U15 includes VDD3V3 as the power supply signal, GND as the ground signal. The D+ and D- signals on the analog switch chip U15 are respectively connected to the D+ and D- signals on the protocol chip U14. HSD1+, HSD1-, HSD2+, and HSD2- are two groups of switches. The HSD1+ signal is connected to the positive differential signal DPB of the TypeC2 interface, the HSD1- signal is connected to the negative differential signal DMB of the TypeC2 interface, the HSD2+ signal is connected to the positive differential signal USBA_DP of the USBA interface, the HSD2- signal is connected to the negative differential signal USBA_DM of the USBA interface, and OE is the enable signal of the analog switch chip U15.

[0037] For the multi-port output hardware protocol intelligent distribution circuit provided by the present utility model, its working principle is as follows. As Figure 4 and Figure 5 shown, when the protocol chip U14 (Xinhai CS32G020) is in use, there are only two groups of CC signals (pins 6, 7, 3, 4) and two groups of D+, D- signals (pins 18, 19, 21, 22) inside the chip. It can only meet the output of 2 C ports, resulting in no protocol for USBA and unable to perform boost output. Therefore, an analog switch chip U15 (Runshi RX2228) is added. During use, the pins 18 and 19 on the protocol chip U14 are switched. When only the TypeC2 interface output is used, the pins 18 and 19 of the protocol chip U14 are switched to pins 2 and 8 of U15 through the analog switch chip U15 and connected to the female socket JP2. When only the USBA interface output is used, the pin 18 and pin 19 of U14 are switched to pins 3 and 7 of the analog switch chip U15 through the analog switch chip U15, and thus connected to the female socket JP3. In this way, the fast charging function can be satisfied during output.

[0038] That is to say, when it is detected that the TypeC2 interface is inserted, the analog switch chip U15 switches the D+ and D- signals to DPB and DMB, enabling the TypeC2 to have the QC fast charging boost function. When it is detected that the USBA interface is inserted, the analog switch chip U15 switches the D+ and D- signals to USBA_DP and USBA_DM, enabling the USBA to also have the fast charging boost function. By increasing the use of the analog switch protocol U15, the problem of insufficient pin positions of the protocol chip U14 is solved. At the same time, the fast charging function of the USBA interface is also realized.

[0039] It should be noted that the electronic components used in the above embodiments are all conventional electronic components for those skilled in the art. The specific connection circuit and how to select the specific model are common knowledge for those skilled in the art, and the above embodiments will not be specifically elaborated.

[0040] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A multi-port output hardware protocol intelligent allocation circuit, characterized in that, It includes a Type-C1 interface circuit, a Type-C2 interface circuit, a USB-A interface circuit, a protocol chip U14, and an analog switch chip U15. The common terminals of the Type-C1 interface circuit, the Type-C2 interface circuit, and the USB-A interface circuit are connected to the protocol chip U14, and the protocol chip U14 is connected to the analog switch chip U15.

2. The intelligent allocation circuit for a multi-port output hardware protocol according to claim 1, characterized in that The 18th and 19th pins of the protocol chip U14 are respectively connected to the corresponding pins of the analog switch chip U15. The 2nd and 8th pins of the analog switch chip U15 are respectively connected to the Type-C2 interface circuit, and the 3rd and 7th pins of the analog switch chip U15 are respectively connected to the USB-A interface circuit.

3. The intelligent allocation circuit for hardware protocols with multiple outputs according to claim 1, wherein The Type-C1 interface circuit includes a female socket JP1, a first P-MOS transistor Q7, and a second P-MOS transistor Q8. The female socket JP1 is sequentially connected to the first P-MOS transistor Q7 and the second P-MOS transistor Q8, and the female socket JP1 is connected to the protocol chip U14.

4. A multi-port output hardware protocol intelligent allocation circuit according to claim 1, characterized in that, The Type-C2 interface circuit includes a female socket JP2, a third P-MOS transistor Q12, and a fourth P-MOS transistor Q11. The female socket JP2 is sequentially connected to the third P-MOS transistor Q1 and the fourth P-MOS transistor Q11, and the female socket JP2 is connected to the protocol chip U14.

5. A multi-port output hardware protocol intelligent allocation circuit according to claim 1, characterized in that, The USB-A interface circuit includes a female socket JP3, a fifth P-MOS transistor Q13, and a sixth P-MOS transistor Q14. The female socket JP3 is sequentially connected to the fifth P-MOS transistor Q13 and the sixth P-MOS transistor Q14, and the female socket JP3 is connected to the protocol chip U14.

6. A multi-port output hardware protocol intelligent allocation circuit according to any one of claims 1 to 4, characterized in that, The protocol chip U14 is CS32G020 of CoreSea.

7. A multi-port output hardware protocol intelligent allocation circuit according to any one of claims 1 to 4, characterized in that, The analog switch chip U15 is RX2228 of RunShi.

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