Radio frequency switch circuit for improving ESD protection capability and isolation
By introducing a series resonant structure of MOS tube M5 and capacitor C1 into the RF switch circuit, the problem of insufficient isolation and ESD protection of the CMOS process RF switch circuit in a high-frequency environment is solved, and the high-frequency isolation and ESD capability are improved, and the system performance and safety are improved.
Patent Information
- Application Number
- CN202422334083.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2025-07-18
- Estimated Expiration
- 2034-09-24
AI Technical Summary
The existing RF switching circuit based on CMOS technology has poor isolation in high-frequency environments and insufficient ESD protection capabilities, resulting in signal interference and system performance degradation.
Using a radio frequency switching circuit design including the first, second, third and fourth switching branches, by introducing a series resonant structure of MOS tube M5 and capacitor C1 into the third and fourth switching branches, the size of inductor L1 and capacitor C1 is adjusted to improve high frequency isolation, and the parasitic transistor of MOS tube M5 is used to vent ESD charge.
The isolation and ESD protection capability of the RF switch circuit in high-frequency environments are improved, the isolation is improved by 6dB, the ESD capability is enhanced, signal interference is reduced, and system performance and safety are improved.
Smart Images
Figure CN223124870U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of radio frequency switches, and particularly relates to a radio frequency switch circuit for improving ESD protection ability and isolation degree. Background Technique
[0002] With the rapid development of 5G technology, the channel spectrum resources are tense, the interval between adjacent frequency bands is getting closer and closer, and at the same time, the requirement for the isolation degree of radio frequency switch chips is getting higher and higher. In addition, since the 5G network needs to process a large amount of data transmission, if the isolation degree of the radio frequency switch is not enough, signal interference will occur, affecting the data transmission efficiency. Therefore, improving the isolation degree of the radio frequency switch can not only improve the performance of the system, but also improve the security and energy efficiency of the system.
[0003] When the radio frequency switch chip is in use, the electrostatic discharge phenomenon will cause device damage and circuit function failure. Among them, the electrostatic discharge (ESD) phenomenon is that a large amount of charge transfer occurs when two objects with different potentials come into contact instantaneously, resulting in a transient large current pulse.
[0004] For radio frequency switch chips, the CMOS process with silicon as the substrate is still the mainstream manufacturing process for radio frequency switches. This process is widely used in wireless communication systems due to its ultra-low cost and excellent radio frequency performance (low insertion loss, high isolation, good linearity, and high integration).
[0005] The schematic diagram of the existing radio frequency switch circuit manufactured based on the CMOS process with silicon as the substrate is as Figure 1 shown, which includes a plurality of parallel main switch paths 1, and each main switch path 1 is provided with a slave switch path 2. MOS transistors for controlling the conduction or cutoff of the path are provided in the main switch path 1 and the slave switch path 2. The reception and transmission of signals are realized by controlling the on or off of the MOS transistors in the main switch path 1 and the slave switch path 2.
[0006] When the existing radio frequency switch circuit is used in a high-frequency environment, due to some parasitic effects of the MOS transistors, the high-frequency isolation degree will deteriorate sharply, and thus it cannot be used in high-frequency bands. For radio frequency switches, the slave switch path is used to improve the isolation degree and discharge ESD charges. If the size of the MOS transistor in the slave switch path is increased to enhance the ESD ability, the isolation degree will deteriorate.
[0007] For the above problems, the traditional method is to compromise and optimize the ESD ability and isolation degree of the radio frequency switch chip by the size and stacking number of the MOS transistors in the slave switch path, but the problem cannot be fundamentally solved, resulting in certain limitations of the radio frequency switch. Content of the Utility Model
[0008] In view of the shortcomings of the background technology, the utility model provides a radio frequency switch circuit with improved ESD protection capability and isolation. The technical problem to be solved is that the existing radio frequency switch circuit based on CMOS tube has poor isolation when applied to the high frequency field.
[0009] In order to solve the above technical problems, the utility model provides the following technical solutions: a radio frequency switch circuit for improving ESD protection capability and isolation, comprising a first switch branch, a second switch branch, a third switch branch and a fourth switch branch;
[0010] The first connection end of the first switch branch and the first connection end of the second switch branch are both electrically connected to the antenna, the second connection end of the first switch branch is electrically connected to the first connection end of the third switch branch, and the second connection end of the second switch branch is electrically connected to the first connection end of the fourth switch branch;
[0011] The second connection end of the third switch branch and the second connection end of the fourth switch branch are electrically connected to the MOS tube M5 and the capacitor C1 respectively, the gate of each MOS tube M5 is electrically connected to the resistor R5 respectively, the other end of each resistor R5 is electrically connected to the source of the corresponding MOS tube M5 and one end of the capacitor C1 respectively, and the source of each MOS tube M5 is grounded through the inductor L1 respectively.
[0012] In a certain embodiment, the first switch branch includes a plurality of MOS transistors M1 connected in series in sequence, wherein the source of each front-end MOS transistor M1 is electrically connected to the drain of the rear-end MOS transistor M1, the drain of the head-end MOS transistor M1 is the first connection end of the first switch branch, and the source of the tail-end MOS transistor M1 is the second connection end of the first switch branch.
[0013] In a certain implementation manner, the gate of each MOS tube M1 is electrically connected to a resistor R1 , and ends of all the resistors R1 that are away from the gate of the MOS tube M1 are electrically connected to each other.
[0014] In a certain embodiment, the second switch branch includes a plurality of MOS transistors M2 connected in series in sequence, wherein the source of each front-end MOS transistor M2 is electrically connected to the drain of the rear-end MOS transistor M2, the drain of the head-end MOS transistor M2 is the first connection end of the second switch branch, and the source of the tail-end MOS transistor M2 is the second connection end of the second switch branch.
[0015] In a certain implementation manner, the gate of each MOS transistor M2 is electrically connected to a resistor R2 , and ends of all the resistors R2 that are away from the gate of the MOS transistor M2 are electrically connected to each other.
[0016] In some embodiments, the third switch branch includes a plurality of MOS transistors M3 connected in series in sequence. The series connection is such that the source electrode of each front-end MOS transistor M3 is electrically connected to the drain electrode of the rear-end MOS transistor M3. The drain electrode of the first MOS transistor M3 at the head end is the first connection end of the third switch branch, and the source electrode of the last MOS transistor M3 at the tail end is the second connection end of the third switch branch.
[0017] In some embodiments, a resistor R3 is electrically connected to the gate of each MOS transistor M3 respectively, and one ends of all the resistors R3 facing away from the gates of the MOS transistors M3 are electrically connected to each other.
[0018] In some embodiments, the fourth switch branch includes a plurality of MOS transistors M4 connected in series in sequence. The series connection is such that the source electrode of each front-end MOS transistor M4 is electrically connected to the drain electrode of the rear-end MOS transistor M4. The drain electrode of the first MOS transistor M4 at the head end is the first connection end of the fourth switch branch, and the source electrode of the last MOS transistor M4 at the tail end is the second connection end of the fourth switch branch.
[0019] In some embodiments, a resistor R4 is electrically connected to the gate of each MOS transistor M4 respectively, and one ends of all the resistors R4 facing away from the gates of the MOS transistors M4 are electrically connected to each other.
[0020] In some embodiments, when the first switch branch is turned on, the second switch branch is turned off; when the first switch branch is turned off, the second switch branch is turned on.
[0021] The first switch branch and the fourth switch branch are turned on and off simultaneously, and the second switch branch and the third switch branch are turned on and off simultaneously.
[0022] The beneficial effects of the present utility model compared with the prior art are as follows: In actual use, first, the present utility model adds a MOS transistor M5 to the paths of the third switch branch and the fourth switch branch to the ground point, and the connection mode of the MOS transistor M5 makes the MOS transistor M5 in the off state. In this way, the capacitor C1 and the inductor L1 perform series resonance and are approximately short-circuited at the resonance center frequency, thereby improving the isolation degree at a specific frequency.
[0023] Secondly, the resonance frequency point can also be adjusted by adjusting the sizes of the inductor L1 and the capacitor C1.
[0024] In addition, since the capacitor C1 has the function of passing high frequencies and blocking low frequencies, the high-frequency isolation degree of the circuit will not be affected, and the high-frequency isolation degree can be improved through the series resonance of the inductor L1 and the capacitor C1.
[0025] Finally, the parasitic triode of the MOS transistor M5 can discharge the charge to the ground, thereby improving the ESD ability of the circuit. Description of the Drawings
[0026] Figure 1 It is a circuit diagram of an existing RF switch circuit;
[0027] Figure 2 is Figure 1 The insertion loss simulation diagram of the circuit;
[0028] Figure 3 is Figure 1 The isolation simulation diagram of the circuit;
[0029] Figure 4 It is the circuit diagram of the present utility model in the embodiment;
[0030] Figure 5 is Figure 4 The insertion loss simulation diagram of the circuit;
[0031] Figure 6 is Figure 5 The isolation simulation diagram of the circuit. Detailed implementation manner
[0032] Now, the present utility model will be further described in detail with reference to the accompanying drawings. These drawings are all simplified schematic diagrams, only illustrating the basic structure of the present utility model in a schematic manner, so they only show the components related to the present utility model.
[0033] For Figure 1 the existing RF switch circuit shown in the figure, insertion loss and isolation simulations are performed. The relevant simulation schematic diagrams are as shown in Figure 2 and Figure 3 shown. It can be obtained from Figure 2 and Figure 3 that in the case of 6 GHz, the isolation of the existing RF switch circuit is 35 dB.
[0034] In order to improve the isolation of the existing RF switch circuit, as shown in Figure 4 shown, this embodiment provides an RF switch circuit that improves ESD protection ability and isolation, including a first switch branch 1, a second switch branch 2, a third switch branch 3, and a fourth switch branch 4;
[0035] The first connection end of the first switch branch 1 and the first connection end of the second switch branch 2 are both electrically connected to the antenna ANT. The second connection end of the first switch branch 1 is electrically connected to the first connection end of the third switch branch 3, and the second connection end of the second switch branch 2 is electrically connected to the first connection end of the fourth switch 4 branch;
[0036] The second connection end of the third switch branch 3 and the second connection end of the fourth switch branch 4 are electrically connected to the MOS tube M5 and the capacitor C1 respectively, the gate of each MOS tube M5 is electrically connected to the resistor R5 respectively, the other end of each resistor R5 is electrically connected to the source of the corresponding MOS tube M5 and one end of the capacitor C1 respectively, and the source of each MOS tube M5 is grounded through the inductor L1 respectively.
[0037] In actual use, firstly, the utility model adds a MOS tube M5 on the path between the third switch branch 3 and the fourth switch branch 4 and the grounding point, and the connection mode of the MOS tube M5 makes the MOS tube M5 in the off state, so that the capacitor C1 and the inductor L1 are in series resonance, and are approximately short-circuited at the resonance center frequency, thereby improving the isolation of a specific frequency;
[0038] Secondly, the resonant frequency point can be adjusted by adjusting the size of the inductor L1 and the capacitor C1; specifically, the size of the inductor L1 can be adjusted by adjusting the length and thickness of the bonding wire;
[0039] In addition, since capacitor C1 has the function of passing high frequencies and blocking low frequencies, the high-frequency isolation of the circuit will not be affected, and the high-frequency isolation can be improved by the series resonance of inductor L1 and capacitor C1;
[0040] Finally, the MOS tube M5 adopts the GGNMOS connection method. The parasitic triode of the MOS tube M5 can discharge the charge to the ground, thereby improving the ESD capability of the circuit; specifically, when the ESD event begins, a large amount of positive charge gathers at the drain end of the MOS tube M5, and the positive charge is gathered at the body diode end through the reverse bias of the PN junction between the drain end and the body diode of the MOS tube M5. The positive charge turns on the PN junction at the source end, thereby turning on the parasitic triode of the MOS tube M5, and a large amount of positive charge is transferred to the source end of the MOS tube M5 through the drain end of the MOS tube M5, and is quickly discharged to the ground.
[0041] Specifically, Figure 4 As shown, in this embodiment, the first switch branch 1 includes a plurality of MOS tubes M1 connected in series in sequence, and the source of each front-end MOS tube M1 is electrically connected to the drain of the rear-end MOS tube M1, the drain of the head-end MOS tube M1 is the first connection end of the first switch branch, and the source of the tail-end MOS tube M1 is the second connection end of the first switch branch.
[0042] Furthermore, the gate of each MOS tube M1 is electrically connected to a resistor R1, and the ends of all resistors R1 away from the gate of the MOS tube M1 are electrically connected to each other for inputting a control voltage V1; when the control voltage V1 is at a high level, the first switch branch 1 is turned on, and when the control voltage V1 is at a low level, the first switch branch 1 is turned off.
[0043] In addition, during actual use, the number of MOS transistors M1 in the first switching branch 1 is selected according to actual needs, and there is no limitation here.
[0044] Specifically, as Figure 4 shown, in this embodiment, the second switching branch 2 includes a plurality of MOS transistors M2 connected in series in sequence. The series connection is such that the source electrode of each front-end MOS transistor M2 is electrically connected to the drain electrode of the rear-end MOS transistor M2. The drain electrode of the first MOS transistor M2 at the head end is the first connection end of the second switching branch, and the source electrode of the last MOS transistor M2 at the tail end is the second connection end of the second switching branch.
[0045] Furthermore, a resistor R2 is electrically connected to the gate of each MOS transistor M2 respectively. One ends of all the resistors R2 that are away from the gates of the MOS transistors M2 are electrically connected to each other for inputting a control voltage V2. When the control voltage V2 is at a high level, the second switching branch 2 is turned on, and when the control voltage V2 is at a low level, the second switching branch 2 is turned off.
[0046] In addition, during actual use, the number of MOS transistors M2 in the second switching branch 2 is selected according to actual needs, and there is no limitation here.
[0047] Specifically, as Figure 4 shown, in this embodiment, the third switching branch 3 includes a plurality of MOS transistors M3 connected in series in sequence. The series connection is such that the source electrode of each front-end MOS transistor M3 is electrically connected to the drain electrode of the rear-end MOS transistor M3. The drain electrode of the first MOS transistor M3 at the head end is the first connection end of the third switching branch 3, and the source electrode of the last MOS transistor M3 at the tail end is the second connection end of the third switching branch 3.
[0048] Furthermore, a resistor R3 is electrically connected to the gate of each MOS transistor M3 respectively. One ends of all the resistors R3 that are away from the gates of the MOS transistors M3 are electrically connected to each other for inputting a control voltage V2. When the control voltage V2 is at a high level, the third switching branch 3 is turned on, and when the control voltage V3 is at a low level, the third switching branch 3 is turned off.
[0049] In addition, during actual use, the number of MOS transistors M3 in the third switching branch 3 is selected according to actual needs, and there is no limitation here.
[0050] Specifically, as Figure 4 shown, in this embodiment, the fourth switching branch 4 includes a plurality of MOS transistors M4 connected in series in sequence. The series connection is such that the source electrode of each front-end MOS transistor M4 is electrically connected to the drain electrode of the rear-end MOS transistor M4. The drain electrode of the first MOS transistor M4 at the head end is the first connection end of the fourth switching branch 4, and the source electrode of the last MOS transistor M4 at the tail end is the second connection end of the fourth switching branch 4.
[0051] Furthermore, each gate of the MOS transistor M4 is electrically connected to a resistor R4, and one end of all the resistors R4 facing away from the gates of the MOS transistors M4 are electrically connected to each other for inputting a control voltage V1. When the control voltage V1 is at a high level, the fourth switch branch 4 is turned on, and when the control voltage V4 is at a low level, the fourth switch branch 4 is turned off.
[0052] In addition, in this embodiment, when the first switch branch 1 is turned on, the second switch branch 2 is turned off, and when the first switch branch 1 is turned off, the second switch branch 2 is turned on;
[0053] The first switch branch 1 and the fourth switch branch 4 are turned on and off simultaneously, and the second switch branch 2 and the third switch branch 3 are turned on and off simultaneously.
[0054] For Figure 4 the circuit shown, insertion loss and isolation simulation are performed. The relevant simulation schematic diagrams are as shown in Figure 5 and Figure 6 . It can be obtained from Figure 5 and Figure 6 that in the case of 6 GHz, the isolation of the RF switch circuit in this embodiment is 41 dB. Compared with the existing RF switch circuit, the isolation is increased by 6 dB, and the insertion loss is the same as that of the traditional RF switch circuit in the same frequency band.
[0055] Based on the inspiration of the present utility model, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of this utility model. The technical scope of this utility model is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.
Claims
1. A radio frequency switch circuit for improving ESD protection ability and isolation degree, characterized in that It includes a first switch branch, a second switch branch, a third switch branch, and a fourth switch branch; The first connection end of the first switch branch and the first connection end of the second switch branch are both electrically connected to the antenna. The second connection end of the first switch branch is electrically connected to the first connection end of the third switch branch, and the second connection end of the second switch branch is electrically connected to the first connection end of the fourth switch branch; The second connection end of the third switch branch and the second connection end of the fourth switch branch are respectively electrically connected to an MOS transistor M5 and a capacitor C1. The gate of each MOS transistor M5 is electrically connected to a resistor R5, and the other end of each resistor R5 is respectively electrically connected to the source of the corresponding MOS transistor M5 and one end of the capacitor C1. The source of each MOS transistor M5 is respectively grounded through an inductor L1.
2. The RF switch circuit for improving ESD protection ability and isolation degree according to claim 1, wherein The first switch branch includes a plurality of MOS transistors M1 connected in series in sequence. The series connection is such that the source of each front-end MOS transistor M1 is electrically connected to the drain of the rear-end MOS transistor M1. The drain of the first MOS transistor M1 at the head end is the first connection end of the first switch branch, and the source of the last MOS transistor M1 is the second connection end of the first switch branch.
3. The RF switch circuit for improving ESD protection ability and isolation degree according to claim 2, wherein The gate of each MOS transistor M1 is respectively electrically connected to a resistor R1, and one ends of all the resistors R1 facing away from the gates of the MOS transistors M1 are electrically connected to each other.
4. A radio frequency switch circuit for improving ESD protection ability and isolation degree according to claim 1, characterized in that, The second switch branch includes a plurality of MOS transistors M2 connected in series in sequence. The series connection is such that the source of each front-end MOS transistor M2 is electrically connected to the drain of the rear-end MOS transistor M2. The drain of the first MOS transistor M2 at the head end is the first connection end of the second switch branch, and the source of the last MOS transistor M2 is the second connection end of the second switch branch.
5. The RF switch circuit for improving ESD protection ability and isolation degree according to claim 4, wherein, The gate of each MOS transistor M2 is respectively electrically connected to a resistor R2, and one ends of all the resistors R2 facing away from the gates of the MOS transistors M2 are electrically connected to each other.
6. The radio frequency switch circuit for improving ESD protection ability and isolation degree according to claim 1, characterized in that The third switch branch includes a plurality of MOS transistors M3 connected in series in sequence. The series connection is such that the source of each front-end MOS transistor M3 is electrically connected to the drain of the rear-end MOS transistor M3. The drain of the first MOS transistor M3 at the head end is the first connection end of the third switch branch, and the source of the last MOS transistor M3 is the second connection end of the third switch branch.
7. The radio frequency switch circuit for improving ESD protection ability and isolation degree according to claim 6, characterized in that The gate of each MOS transistor M3 is respectively electrically connected to a resistor R3, and one ends of all the resistors R3 facing away from the gates of the MOS transistors M3 are electrically connected to each other.
8. The radio frequency switch circuit for improving ESD protection ability and isolation degree according to claim 1, wherein The fourth switch branch includes a plurality of MOS transistors M4 connected in series in sequence. The series connection is such that the source of each front-end MOS transistor M4 is electrically connected to the drain of the rear-end MOS transistor M4. The drain of the first MOS transistor M4 at the head end is the first connection end of the fourth switch branch, and the source of the last MOS transistor M4 is the second connection end of the fourth switch branch.
9. The RF switch circuit for improving ESD protection ability and isolation degree according to claim 8, wherein, The gate of each MOS transistor M4 is respectively electrically connected to a resistor R4, and one ends of all the resistors R4 facing away from the gates of the MOS transistors M4 are electrically connected to each other.
10. The radio frequency switch circuit for improving ESD protection ability and isolation degree according to claim 1, wherein When the first switch branch is turned on, the second switch branch is turned off. When the first switch branch is turned off, the second switch branch is turned on; The first switch branch and the fourth switch branch are turned on and off simultaneously, and the second switch branch and the third switch branch are turned on and off simultaneously.