Extensible direct current IRIG-B type time service coding and decoding device

Abstract

The utility model discloses an extensible direct-current IRIG-B type time service encoding and decoding device. The extensible direct-current IRIG-B type time service encoding and decoding device comprises an FPGA (Field Programmable Gate Array) programmable device, a crystal oscillator module, a storage module and a peripheral circuit, the FPGA programmable device is used for realizing data format conversion among the serial TOD time code, the pulse per second and the IRIG-B type code; the crystal oscillator module is used for providing a 50MHz standard clock frequency for the FPGA programmable device; and the storage module is used for programming and storing the program of the FPGA programmable device. According to the utility model, the mutual conversion of the IRIG-B type code (DC) and the serial TOD time code can be realized at the same time, and the device has the advantages of high decoding precision, strong transportability, strong working stability and easy expansion.

Description

Technical Field

[0001] The utility model relates to the technical field of time synchronization, and particularly relates to an expandable DC IRIG-B type time service encoding and decoding device. Background Art

[0002] With the rapid development of information technology, synchronous data transmission has become the basis of daily life and professional fields, and people's requirements for data transmission efficiency and reliability are getting higher and higher. The communication channel has inherent noise and fading characteristics. The signal will inevitably be interfered during the transmission process through the channel, resulting in signal distortion. At the same time, due to the large amount of original data, it is not conducive to storage and processing. Generally, source coding and channel coding are performed on the original data to improve the reliability of the data signal during the processing and transmission process.

[0003] The existing DC IRIG-B type (also known as IRIG-B type (DC) code) decoder based on a single-chip microcomputer has problems such as low decoding accuracy and poor working stability because the operating clock of the single-chip microcomputer is relatively low and it cannot process multiple data sources in parallel, and it cannot meet the accuracy requirements of synchronous time for current information transmission. At the same time, the DC IRIG-B type code encoder / decoder designed by the single-chip microcomputer needs to cooperate with a large number of peripheral circuits to be realized. Once the design is completed, it is difficult to modify the circuit, which does not conform to the development trend of electronic technology.

[0004] At present, domestic designs for encoding and decoding DC IRIG-B type codes using embedded system-on-chip chips have also emerged. In this design, the ARM microprocessor system on the chip realizes the encoding and decoding of DC IRIG-B type codes, and the FPGA programmable device realizes the modulation / demodulation function of DC IRIG-B type codes. However, this method has the following problems: 1) The problem of cumbersome function development process, which requires simultaneous completion of the development environment construction, code writing, and function debugging of the ARM microprocessor system and the FPGA programmable device, and the implementation period requirement is relatively long; 2) Using an embedded system-on-chip chip, compared with using a general FPGA programmable device, the cost is higher, the versatility is poor, and it is easy to cause waste of resources. Summary of the Utility Model

[0005] The purpose of the utility model is to provide an expandable DC IRIG-B type time service encoding and decoding device, which can simultaneously receive two different time service sources, namely IRIG-B type code (DC) and asynchronous serial TOD time code, realize the mutual conversion of IRIG-B type code (DC) and asynchronous serial TOD time code, provide high-precision and high-stability synchronous reference time information for time-using systems such as communication, navigation, and meteorology, so as to ensure the reliable transmission of information in time-using systems, and has the advantages of high decoding accuracy and strong portability.

[0006] In order to solve the above technical problems, the utility model adopts the following technical solutions:

[0007] An expandable DC IRIG-B time code encoding and decoding device, comprising a data format conversion module, a crystal oscillator module, a storage module and a peripheral circuit.

[0008] The reset signal and the clock frequency in the crystal oscillator module are respectively input into the data format conversion module. After the data format conversion between the serial TOD time code, the second pulse and the IRIG-B code, the serial TOD time code output, the second pulse pps output and the IRIG-B code output are obtained.

[0009] The storage module stores the program in the data format conversion module.

[0010] Furthermore, the data format conversion module is an FPGA programmable device.

[0011] Furthermore, the data format conversion module includes a global clock processing unit, a serial TOD time code conversion unit and an IRIG-B code conversion unit. The output end of the global clock processing unit is respectively connected to the input ends of the serial TOD time code conversion unit and the IRIG-B code conversion unit.

[0012] The reset signal and the clock frequency in the crystal oscillator module are respectively input into the global clock processing unit of the FPGA programmable device to obtain a clock signal, a pulse signal and a global rstn reset signal; the IRIG-B code input and the result output by the global clock processing unit are input into the serial TOD time code conversion unit to obtain a serial TOD time code output and a second pulse pps output; the serial TOD time code, the second pulse pps and the result output by the global clock processing unit are input into the IRIG-B code conversion unit to obtain an IRIG-B code output.

[0013] Furthermore, the serial TOD time code conversion unit includes an Irig_b receiving module, an Irig_b checking module, an Irig_b data processing module, an asynchronous serial data processing module and an asynchronous serial data sending module.

[0014] The Irig_b receiving module is used to decode the input signal into DC code to obtain symbol information, time information, and the second pulse signal pps, and output them to the Irig_b verification module; the Irig_b verification module is used to verify the received symbol information and output the correctly verified data to the Irig_b data processing module; the Irig_b data processing module is used to convert the received data into binary code and perform a second-plus-one algorithm processing on the received time information to form the current time information, and output the time information to the asynchronous serial data processing module; the asynchronous serial data processing module is used to byte-pack the time information binary code, convert it into tx_din[7:0] data, and send the bytes to the asynchronous serial data sending module in the order of the frame structure; the asynchronous serial data sending module is used to send asynchronous serial data bytes according to the standard asynchronous serial data protocol.

[0015] Further, the IRIG-B code conversion unit includes an asynchronous serial port receiving module, an asynchronous serial port data processing module, a B-type code data processing module, and a B-type code sending module.

[0016] The asynchronous serial port receiving module is used to perform serial-to-parallel conversion on the serial TOD time code byte by byte and output the converted parallel data to the asynchronous serial port data processing module; the asynchronous serial port data processing module is used to perform integrity judgment on the received parallel data byte by byte, organize and merge it according to the serial port time code frame format to form a serial TOD time code data frame and convert it into BCD code, perform data processing according to the asynchronous serial port frame format, and output the obtained standard time information to the B-type code data processing module; the B-type code data processing module is used to solve asynchronous clock data interaction, perform a second-plus-one processing on the received standard time information, and form the data into a format conforming to the IRIG-B code, and output the data to the B-type code sending module.

[0017] Further, the peripheral circuit includes a status indicator LED, a JTGA debugging interface, and a power supply module. The LED provides status indication, the JTGA debugging interface enables on-line debugging and program downloading, and the power supply module provides power input for the data format conversion module.

[0018] Compared with the prior art, the present utility model adopts the above technical solutions and has the following technical effects:

[0019] This device is based on a general FPGA programmable device, using a Clk clock with a frequency of 100 MHz. It can simultaneously receive two different time sources, namely IRIG-B code (DC) and serial TOD time code, and can simultaneously achieve the mutual conversion between IRIG-B code (DC) and serial TOD time code. It can be embedded in the whole machine equipment during use or separately extended into an independent DC code time service device. It has the advantages of high decoding accuracy, strong portability, strong working stability, and easy expansion. It can provide high-precision and high-stability synchronous reference time information for the time-using system to ensure the reliable transmission of information in the time-using system, and can be widely used in fields such as communication, navigation, and meteorology. Description of the Drawings

[0020] Figure 1 is the overall structure diagram of the present utility model.

[0021] Figure 2 is the functional module design block diagram of the present utility model based on the programmable device FPGA.

[0022] Figure 3 is the composition block diagram of the IRIG-B code (DC) conversion unit of the present utility model.

[0023] Figure 4 is the composition block diagram of the serial TOD time code conversion unit of the present utility model. Detailed Implementation Manner

[0024] The following further describes the present utility model in conjunction with the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present utility model and cannot be used to limit the protection scope of the present utility model.

[0025] There are two major categories of IRIG time standards: one is serial time code, which has six formats, namely A, B, D, E, G, and H; the other is parallel time code format. Since this type of code is in parallel format, the transmission distance is relatively short and it is binary, so it is far less widely used than the serial format. The main difference among the six formats in the serial time code is the frame rate of the time code. The B code (also known as IRIG-B code), its time frame rate is 1 frame / s and it can transmit 100 bits of information. The B code is divided into two types: direct current (DC) and alternating current (AC). The unmodulated one is usually called IRIG-B code (DC), and the modulated B code is usually called IRIG-B code (AC).

[0026] The three basic coding form pulse signals of IRIG-B code (DC) have a frequency of 100 MHz. Among them, the first one is a pulse with a high level of 2 ms and a low level of 8 ms (representing logic "0"); the second one is a pulse with both high and low levels of 5 ms (representing logic "1"); the third one is a pulse with a high level of 8 ms and a low level of 2 ms (used as a position identification flag and reference symbol).

[0027] To achieve the above object, the present utility model proposes an expandable DC IRIG-B type time service encoding and decoding device, as Figure 1 shown, the specific content is as follows:

[0028] This device realizes the simultaneous reception of two different time service sources, namely IRIG-B code (DC) and asynchronous serial TOD time code, through a general-purpose FPGA programmable device, and realizes the mutual conversion between IRIG-B code (DC) and asynchronous serial TOD time code, providing a stable time signal for the time service system equipment (time-consuming equipment).

[0029] This device includes a general-purpose FPGA programmable device, a crystal oscillator module, a storage module, and peripheral circuits. Among them, the FPGA chip of the EP3C25E144C8N model is selected to implement the data format conversion between serial TOD time code, second pulse, and IRIG-B code (DC) using the hardware description language Verilog; the SN74LVC2T45 level conversion chip is selected to convert the 5V level of the input IRIG-B code (DC) signal to 3.3V level and input it to the FPGA chip; the SN74LVC8T245PW level conversion chip is selected to convert the 3.3V level of the IRIG-B code (DC) signal to 5V level and output it to the time-consuming system / equipment; the storage module chip model is the EPCS4SI8N Flash chip, which is used for the programming and storage of the FPGA program; a 50M crystal oscillator is selected to provide a 50MHz standard clock frequency for the FPGA; the peripheral circuits include status indicator LEDs, JTGA debugging interfaces, and 3.3V / 2.5V / 1.2V power supply modules. The LEDs provide status indicators for the device (such as faults and normality), the JTGA debugging interfaces are used for on-line debugging and program downloading, and the 3.3V / 2.5V / 1.2V power supply modules provide power input for the FPGA chip to ensure the normal operation of the FPGA chip.

[0030] The general-purpose FPGA programmable device includes a global clock processing unit, a serial TOD time code conversion unit, and an IRIG-B code (DC) conversion unit, as Figure 2 shown.

[0031] Among them, the global clock processing unit uses a PLL (Phase Locked Loop) to implement a frequency multiplication method to provide the required frequency for realizing the system synchronization function, so as to synchronize the phase of the external signal pulse and the provided standard clock pulse, thereby realizing the automatic tracking of the input signal frequency to the standard signal frequency. Input Clk_50M and Rst_n into the global clock processing unit, and output Clk_100M, bclk, and PClk_Lock. Clk_50M represents the external input clock of the FPGA, which is provided by the crystal oscillator module, and Rst_n represents the external reset signal of the FPGA. Clk_100M is used for the transceiver and encoding / decoding of IRIG-B code (DC), bclk is used for the transceiver and encoding / decoding of serial TOD time code, and PClk_Lock is the global rstn reset signal. Clk_100M can also be expressed as a 100MHz pulse signal or a 100MHz clock; bclk can also be represented by 16×9600Hz, which is mainly used for the baud rate of 9600 for asynchronous serial port transmission.

[0032] As Figure 3 shown, the IRIG-B code (DC) conversion unit includes an asynchronous serial port receiving module, an asynchronous serial port data processing module, a B-type code data processing module, and a B-type code sending module. The asynchronous serial port receiving module receives the input TOD time code data, performs serial-to-parallel conversion by byte, and then outputs the converted parallel data to the asynchronous serial port data processing module; the asynchronous serial port data processing module performs integrity judgment on the received parallel data by byte, sorts and combines it according to the serial port time code frame format, forms a complete serial TOD time code data frame and converts it into BCD code, and then outputs the standard time information processed according to the asynchronous serial port frame format to the B-type code data processing module. The B-type code data processing module is used to solve the asynchronous clock data interaction between bclk and Clk_100M, perform a second increment processing on the received standard time information, and form the data into a format conforming to IRIG-B code (DC), which is convenient for being sent by the B-type code sending module after the next second pulse arrives. The B-type code sending module completes the generation of the IRIG-B code (DC) format, starts with the rising edge of the second pulse input by pps, and expands the received data conforming to the IRIG-B code format into multiple time service data according to requirements for use by the time-consuming system. The specific content is as follows:

[0033] 1. Asynchronous serial port receiving module

[0034] The asynchronous serial port receiving module is used to receive the standard serial port time information input externally, convert the serial byte data (8 bits) received by a single FPGA I / O pin within one frequency beat, and output the converted parallel data to the asynchronous serial port data processing module through the register rx_dout[7:0] (a register in the FPGA logic) and rx_vld. The conversion here refers to serial-to-parallel conversion: serial means receiving one data bit within one frequency beat, and parallel means receiving 8 data bits within one beat.

[0035] Among them, bclk and rstn are the unified clock and reset signals of the global clock processing unit; rxd is the serial data input externally according to the standard protocol; rx_vld represents the module output data valid signal, which is at a high level when valid and at a low level when invalid; rx_dout[7:0] represents the valid data output by the module and is used in cooperation with rx_vld for output.

[0036] 2. Asynchronous serial port data processing module

[0037] The asynchronous serial port data processing module is used to judge the integrity of the received parallel data byte by byte. After the judgment is complete, it is sorted and merged according to the serial port time code frame format to form a complete serial TOD time code data frame. It judges the validity of the data frame, extracts the time information in the valid data frame and converts it into BCD code, and processes the data according to the asynchronous serial port frame format to obtain the standard time information, and outputs this information to the B-type code data processing module through dout[59:0].

[0038] Among them, din_vld represents the input data valid signal, which is at a high level when valid and at a low level when invalid; din[7:0] represents the input serial port data; dout_vld represents the module output data valid signal, which is at a high level when valid and at a low level when invalid; dout[59:0] represents the valid data output by the module and is used in cooperation with dout_vld for output.

[0039] 3. B-type code data processing module

[0040] The B-type code data processing module is used to solve the asynchronous clock data interaction between bclk and Clk_100M, perform a one-second increment processing on the received standard time information, and form the data into a format conforming to IRIG-B type code (DC), which is convenient for being sent by the B-type code sending module after the next second pulse arrives. The content of the one-second increment processing is: perform a one-second increment on the received standard time information and carry over according to the time format. For example, if the received time is 59 seconds of a certain minute, the second data is cleared and the minute data is incremented by 1. The purpose of the one-second increment is to ensure the correctness of the time.

[0041] Among them, Clk_100M is the unified clock signal of the global clock processing unit; din[59:0] represents the input standard time information.

[0042] 4. B-Type Code Sending Module

[0043] The B-type code sending module completes the generation of the IRIG-B type code (DC) format. Starting from the rising edge of the second pulse input with pps, it expands the received data conforming to the IRIG-B type code format into multiple-channel serial data (b_code) according to requirements for use by the time-using system. The B-type code sending module adds flag bits such as the frame start flag bit and position identification flag to the received standard time BCD code, converting the BCD format time information into the IRIG-B format code.

[0044] Among them, pps represents the second pulse signal, and the high-level starting edge represents the start of the second; b_code represents the output IRIG-B type code (DC).

[0045] Such as Figure 4 shown, the serial TOD time code conversion unit mainly includes: Irig_b(DC) receiving module, Irig_b(DC) verification module, Irig_b(DC) data processing module, asynchronous serial data processing module, and asynchronous serial data sending module.

[0046] The Irig_b(DC) receiving module is used to decode the DC code of the input IRIG-B type code (DC) signal to obtain the code element information, time information, and the second pulse signal pps, and output the received code element information to the Irig_b(DC) verification module; the Irig_b(DC) verification module verifies the 100-bit bit information in the code element information, and when the verification result is correct, it outputs the data to the Irig_b(DC) data processing module; the Irig_b(DC) data processing module processes the received Irig_b(DC) data, including converting the BCD code into a binary code and performing a second-plus-1 algorithm processing on the received time information to form the current time information, and outputting the time information to the asynchronous serial data processing module. The asynchronous serial data processing module performs byte packing processing on the binary code of the input data, converts the din[59:0] input data into tx_din[7:0] data available for the asynchronous serial data sending module, that is, converts it into an asynchronous serial time code frame structure, and sends the bytes to the asynchronous serial data sending module in the order of the frame structure. The asynchronous serial data sending module is used to complete the sending of the asynchronous serial data bytes, and sends the input tx_din[7:0] combined with the second pulse signal pps generated by the Irig_b(DC) receiving module according to the standard asynchronous serial data protocol for easy reception by the time-using system.

[0047] The specific content is:

[0048] 1. Irig_b(DC) Receiver Module

[0049] The Irig_b(DC) receiver module uses a 100 MHz clock signal to sample the IRIG-B type code (DC) signal in order to extract the code element information, time information, and the second pulse signal pps. Selecting a 100 MHz clock signal can prevent the three code elements from overlapping and avoid time errors during the adoption process. When the rising edge of the IRIG-B type code (DC) signal arrives, the counter starts counting, and when the falling edge arrives, it stops counting. The corresponding code element is determined by sampling the counting value range, thereby decoding the DC code. It should be noted that since the high-level width of each code element is fixed values of "2", "8", "5", the 100 MHz clock is also fixed, and the corresponding code element can be calculated through the value range. At the same time, when the frame start flag bit is detected, the second pulse signal pps is output. Thus, it can be seen that the Irig_b(DC) receiver module mainly realizes two functions: ① Decode the DC code of the sampled IRIG-B type code (DC) signal, combine the 100-bit IRIG-B type code (DC) according to the standard IRIG-B type (DC) code protocol format to form the corresponding code element information rx_dout[99:0], time information uart_send[59:0], and the corresponding valid signals rx_vld and uart_send_en; ② Receive the IRIG-B type code (DC) data, start from the start flag of the IRIG-B type code (DC), and generate the second pulse signal pps.

[0050] Among them, b_rx represents the input of the IRIG-B type (DC) code; rx_vld represents the rx data valid signal, which is high level when valid and low level when invalid; uart_send_en represents that it can be sent to the Irig_b(DC) data processing module; rx_dout[99:0] represents the 100-bit IRIG-B type (DC) code bit received, and uart_send[59:0] represents the 60-bit IRIG-B type (DC) code time information received.

[0051] 2. Irig_b(DC) Verification Module

[0052] The Irig_b(DC) verification module also uses a unified 100MHz clock to verify the 100-bit information in the IRIG-B code (DC). For the 100-bit IRIG-B code (DC) bit information, the first 60 bits represent time data, the 75th bit represents the verification bit, and the 81st to 98th bits represent the total seconds of the currently received time information. The specific functions that the Irig_b(DC) verification module can achieve include: ① By performing exclusive OR inversion on the data rx_dout[59:0], the result is compared with the 75th verification bit of the data rx_dout[99:0]. If the comparison is consistent, a logical "1" is output to indicate that the data is valid, otherwise a "0" is output to indicate invalidity, so as to judge whether there are errors in the 100 data during transmission; ② Calculate the total seconds sbs (from the 81st bit to the 98th bit) of the received data rx_dout[99:0], and the calculation result is sbs[16:0], so as to judge whether the received IRIG-B (DC) code time information is correct; ③ Perform an AND operation on the verification result checkin_bit obtained after verification and the uart_send_en output by the Irig_b(DC) receiving module. The calculation result is used as the valid judgment basis for the input of the Irig_b(DC) data processing module. If the calculation result is logical "1", it means that the data is correct and valid, otherwise it means that the data is invalid. If the verification result is correct, the output checkin_bit is "1", and then an "AND" operation is performed with the uart_send_en in the Irig_b(DC) receiving module, and the final received verification result is output to the Irig_b(DC) data processing module.

[0053] Among them, both dvld and din[99:0] are the data output by the Irig_b(DC) receiving module; checkin_bit represents the verification result of the Irig_b(DC) verification module.

[0054] 3. Asynchronous serial data processing module

[0055] In the asynchronous serial data processing module, tx_ack is used to obtain the data transmission status of the asynchronous serial data sending module. A high level indicates the start of data transmission, and a low level indicates the completion of data transmission; tx_req represents the output data valid signal, which is high level when valid and low level when invalid; tx_din[7:0] represents the output data.

[0056] 4. Asynchronous serial data sending module

[0057] In the asynchronous serial data sending module, tx_ack is used to interact with the asynchronous serial data processing module and corresponds to the tx_ack in the asynchronous serial data processing module; txd represents the asynchronous serial data output.

[0058] The serial TOD time code output by the asynchronous serial data sending module in the serial TOD time code conversion unit can be sent to the using system starting 30 ms after the start of the second pulse signal pps generated by the Irig_b(DC) receiving module.

[0059] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. An expandable DC IRIG-B time code encoding and decoding device, characterized in that, It includes a data format conversion module, a crystal oscillator module, a storage module and a peripheral circuit; The reset signal and the clock frequency in the crystal oscillator module are respectively input into the data format conversion module. After the data format conversion among the serial TOD time code, the second pulse and the IRIG-B code, the serial TOD time code output, the second pulse pps output and the IRIG-B code output are obtained; The storage module stores the program in the data format conversion module.

2. The scalable DC IRIG-B time code encoding and decoding device according to claim 1, wherein, The data format conversion module is an FPGA programmable device.

3. The scalable DC IRIG-B time code encoding and decoding device according to claim 1, wherein The data format conversion module includes a global clock processing unit, a serial TOD time code conversion unit and an IRIG-B code conversion unit; The output end of the global clock processing unit is respectively connected to the input ends of the serial TOD time code conversion unit and the IRIG-B code conversion unit; The reset signal and the clock frequency in the crystal oscillator module are respectively input into the global clock processing unit of the FPGA programmable device to obtain a clock signal, a pulse signal and a global rstn reset signal; The IRIG-B code input and the result output by the global clock processing unit are input into the serial TOD time code conversion unit to obtain the serial TOD time code output and the second pulse pps output; the serial TOD time code, the second pulse pps and the result output by the global clock processing unit are input into the IRIG-B code conversion unit to obtain the IRIG-B code output.

4. The scalable DC IRIG-B time code encoding and decoding device according to claim 3, wherein The serial TOD time code conversion unit includes an Irig_b receiving module, an Irig_b checking module, an Irig_b data processing module, an asynchronous serial data processing module and an asynchronous serial data sending module; The Irig_b receiving module decodes the input signal to obtain symbol information, time information and a second pulse signal, and outputs them to the Irig_b checking module; The Irig_b checking module checks the received symbol information and outputs the correctly checked data to the Irig_b data processing module; The Irig_b data processing module converts the received data into binary code, performs a second plus 1 algorithm processing on the received time information to form the current time information, and outputs the time information to the asynchronous serial data processing module; The asynchronous serial data processing module packs the time information binary code into bytes, converts it into tx_din[7:0] data, and sends the bytes to the asynchronous serial data sending module in the order of the frame structure; The asynchronous serial data sending module sends the asynchronous serial data bytes according to the standard asynchronous serial data protocol.

5. The expandable DC IRIG-B time code encoding and decoding device according to claim 3, characterized in that The IRIG-B code conversion unit includes an asynchronous serial port receiving module, an asynchronous serial port data processing module, a B-type code data processing module and a B-type code sending module; The asynchronous serial port receiving module performs serial-to-parallel conversion on the serial TOD time code byte by byte, and outputs the converted parallel data to the asynchronous serial port data processing module; The asynchronous serial port data processing module performs integrity judgment on the received parallel data byte by byte, arranges and merges them according to the serial port time code frame format to form a serial TOD time code data frame and converts it into BCD code, performs data processing according to the asynchronous serial port frame format to obtain the standard time information, and outputs the information to the B-type code data processing module; The B-type code data processing module performs a second increment operation on the received information, forms the data into a format conforming to the IRIG-B type code, and outputs it to the B-type code sending module; The B-type code sending module sends the received data to the time-using system.

6. The scalable DC IRIG-B time code encoding and decoding device according to claim 1, wherein The peripheral circuit includes a status indicator LED, a JTGA debugging interface, and a power supply module. The LED provides status indication. The JTGA debugging interface enables on-line debugging and program downloading. The power supply module provides power input for the data format conversion module.

Images