Power semiconductor device
By setting a partition layer with a band gap greater than the P-type cap layer in the gallium nitride high electron mobility transistor, the gate breakdown problem is solved, and the breakdown voltage and reliability of the device are improved.
Patent Information
- Application Number
- CN202422233760.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2025-07-18
- Estimated Expiration
- 2034-09-12
AI Technical Summary
Existing GaN high electron mobility transistors are prone to gate breakdown due to spike electric fields when the gate is positively compressed, which affects the reliability and breakdown voltage of the device.
A partition layer is provided at both sides of the P-type cap layer below the gate metal layer. The partition layer is composed of a material with an energy band gap greater than the P-type cap layer, and the critical electric field is greater than the critical electric field of the P-type cap layer to reduce the formation of a spike electric field.
It improves the gate breakdown voltage and reliability of the device, reduces drain-gate leakage current, and improves the reliability performance under high temperature reverse bias voltage.
Smart Images
Figure CN223125208U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a power semiconductor device, especially a power semiconductor device. Background Art
[0002] Gallium nitride high electron mobility transistors are common power devices and are widely used in high-frequency application fields such as radio frequency and microwave. Compared with silicon materials, they have a larger bandgap, higher electron mobility, saturation electron velocity, and breakdown electric field.
[0003] Figure 1 As shown in a conventional gallium nitride high electron mobility transistor structure, in order to reduce the chance of the enhancement-mode device being accidentally turned on, the threshold voltage needs to reach a sufficiently high value. To achieve a higher threshold voltage, the P-type cap layer 104 generally requires a higher doping concentration to enhance its ability to deplete the two-dimensional electron gas located below it. However, the depletion region formed on the surface of the P-type cap layer 104 with a higher doping concentration is shallower when the gate is forward-biased, and the formed electric field is also higher. Additionally, due to the edge effect of the electric field, a peak electric field will be formed at the corner position 110 on the surface of the P-type cap layer 104 under the gate metal layer 106. When the above peak electric field reaches the critical electric field of the P-type cap layer 104, the gate of the device will be broken down. Summary of the Utility Model
[0004] To overcome the above-mentioned problems, the utility model provides a power semiconductor device. The device includes a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a P-type cap layer above the barrier layer, a gate metal layer above the P-type cap layer and a spacer layer, a source metal layer on one side of the gate metal layer, and a drain metal layer on the other side. The channel layer and the barrier layer form a heterojunction and a two-dimensional electron gas is formed on the surface of the channel layer below the heterojunction. The P-type cap layer depletes the two-dimensional electron gas on the surface of the channel layer below it when the device is turned off to form an enhancement-mode device. The P-type cap layer and the gate metal layer above it form a Schottky contact. Spacer layers are provided at both side edge positions above the P-type cap layer. The critical electric field of the spacer layer is greater than the critical electric field of the P-type cap layer below it, and the bandgap of the spacer layer is greater than the bandgap of the P-type cap layer.
[0005] Further, the boundaries of the spacer layers on both sides are the same as those of the gate metal layer, and this boundary is within the P-type cap layer.
[0006] Further, the boundaries of the spacer layers on both sides are the same as those of the P-type cap layer, and the boundary of the gate metal layer is within the spacer layer.
[0007] Furthermore, the width of the spacer layer closer to the drain metal layer is larger than that closer to the source metal layer.
[0008] In the present utility model, spacer layers are provided at both edge positions below the gate metal layer and above the P-type capping layer. The spacer layer is composed of a material or a combination thereof with a bandgap greater than that of the P-type capping layer, and the critical electric field of the spacer layer is greater than that of the P-type capping layer. When the gate is positively biased, a peak electric field will be formed at the corner position on the surface of the spacer layer below the gate metal layer. Since the critical electric field of the spacer layer is greater than that of the P-type capping layer, the gate breakdown voltage and reliability of the device are improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 FIG. is a schematic cross-sectional view of a conventional high electron mobility transistor structure.
[0010] Figure 2 FIG. is a schematic cross-sectional view of the device structure according to an embodiment of the present utility model.
[0011] Figure 3 FIG. is a schematic cross-sectional view of the device structure according to another embodiment of the present utility model.
[0012] Figure 4 FIG. is a schematic cross-sectional view of the device structure according to another embodiment of the present utility model.
[0013] Figure 5 FIG. is a schematic cross-sectional view of the device structure according to another embodiment of the present utility model.
[0014] Figures 6 - 11 FIG. is an embodiment of the manufacturing method of the device structure of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0015] The present utility model will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that the corresponding position words such as "upper", "lower", "left", "right", "front", "rear", "vertical", and "horizontal" described in this document are relative positions corresponding to the reference drawings, and the specific implementation does not limit the fixed direction. The devices in the drawings are not necessarily drawn to scale. The straight lines shown at the boundaries of the doped regions and trenches in the drawings, and the sharp corners formed by these boundaries, are generally not straight lines and precise angles in actual applications.
[0016] Embodiment 1
[0017] Referring to Figure 2A cross-sectional schematic diagram of the device structure according to the first embodiment of the present invention is shown in Figure 2a. The structure includes: a substrate layer 200 at the bottom; a buffer layer 201 above the substrate layer 200; a channel layer 202 above the buffer layer 201; a barrier layer 203 above the channel layer 202; a P-type capping layer 104 above the barrier layer 203; spacer layers 205 at both side edge positions above the P-type capping layer 104; a gate metal layer 106 above the P-type capping layer 104 and the spacer layers 205; a source metal layer 207 to the left of the gate metal layer 106 and a drain metal layer 208 to the right of the gate metal layer 106.
[0018] In the above structure, the channel layer 202 and the barrier layer 203 form a heterojunction, and a two-dimensional electron gas (2DEG) is formed on the surface of the channel layer 202 below the heterojunction. When the device is turned on, a current channel is formed between the source metal layer 207 and the drain metal layer 208.
[0019] In the above structure, the P-type capping layer 104 depletes the two-dimensional electron gas on the surface of the channel layer 202 below it when the device is turned off, forming an enhancement-mode device.
[0020] In the above structure, the P-type capping layer 104 forms a Schottky contact with the gate metal layer 106 above it, reducing the gate current when the gate is positively biased.
[0021] In the above structure, the doping material of the P-type capping layer 104 includes magnesium (Mg) or other suitable P-type doping elements.
[0022] In the above structure, the critical electric field of the spacer layer 205 is greater than that of the P-type capping layer 104 below it. When the gate is positively biased, peak electric fields will be formed at the corner positions 210 on both sides of the surface of the spacer layer 205 below the gate metal layer 106. Since the critical electric field of the spacer layer 205 is greater than that of the P-type capping layer 104, the gate breakdown voltage of the device will be increased.
[0023] In the above structure, the spacer layer 205 may include materials such as gallium oxide (GaO), gallium oxynitride (GaON), aluminum nitride (AlN), etc., or combinations thereof, whose band gaps are greater than the band gap of the P-type capping layer 104.
[0024] Embodiment 2
[0025] A variant device embodiment of the present invention is as Figure 3 shown, and Figure 2 the difference from the embodiment is that the widths of the gate metal layer 106 and the spacer layer 205 are the same and smaller than the width of the P-type capping layer 104. The gate metal layer 106 and the spacer layer 205 are formed by one lithography using the same photomask, while the P-type capping layer 104 is formed by lithography using an independent photomask.
[0026] In the above structure, the sidewalls of the P-type capping layer 104 are formed by etching, and there are many defects on the etched surfaces of the sidewalls. Since the widths of the gate metal layer 106 and the spacer layer 205 are smaller than the width of the P-type capping layer 104, the peak electric fields at the corner positions on both sides of the surface of the spacer layer 205 under the gate metal layer 106 are at a relatively large distance from the defects on the sidewalls of the P-type capping layer 104. Therefore, the gate leakage current of the device is small and the gate breakdown voltage is high.
[0027] Embodiment 3
[0028] A variant device embodiment of the present utility model is as Figure 4 shown, and Figure 3 the difference from the embodiment is that the widths of the spacer layer 205 and the P-type capping layer 104 are the same and are larger than the width of the gate metal layer 106. The spacer layer 205 and the P-type capping layer 104 are formed by a single photolithography using the same photomask, while the gate metal layer 106 is formed by photolithography using an independent photomask.
[0029] Figure 3 In the embodiment, the P-type capping layer 104 becomes the etch stop layer for the spacer layer 205, and defects will be formed on the surface of the P-type capping layer 104 after the etching of the spacer layer 205 is completed. Figure 4 In the embodiment, the spacer layer 205 becomes the etch stop layer for the gate metal layer 106, and defects will be formed on the surface of the spacer layer 205 after the etching of the gate metal layer 106 is completed. Since the etching selectivity between the spacer layer 205 and the gate metal layer 106 is better than the etching selectivity between the P-type capping layer 104 and the spacer layer 205, fewer defects are formed on the surface of the spacer layer 205 after the etching of the gate metal layer 106 is completed. Therefore, compared with Figure 3 the embodiment Figure 4 the gate leakage current of this embodiment is small and the gate breakdown voltage is high.
[0030] Embodiment 4
[0031] A variant device embodiment of the present utility model is as Figure 5 shown, and Figure 4 the difference from the embodiment is that the widths of the left and right parts of the spacer layer 205 are different. Generally, the width d1 of the right part of the spacer layer 205 near the drain metal layer 208 is larger than the width d2 of the left part of the spacer layer 205 near the source metal layer 207. When the gate is positively biased, the peak electric field on the surface of the spacer layer 205 under the gate metal layer 106 is at a relatively large distance from the defects on the sidewalls of the P-type capping layer 104, reducing the drain-gate leakage current and improving the reliability performance of the device under high-temperature reverse bias (HTRB).
[0032] Those skilled in the art should know that the structural features mentioned in each of the above-mentioned embodiments of the present utility model can be combined with each other to form more device structures of the embodiments of the present utility model.
[0033] Embodiment 5
[0034] According to the structural features of the above-mentioned embodiments of the present utility model, combined with the existing manufacturing process of gallium nitride high electron mobility transistors, various formation methods of the embodiments of the present utility model devices can be obtained. An exemplary formation method of the embodiments of the present utility model devices is as Figures 6 - 11 shown:
[0035] In the first step, a buffer layer 201 is formed on the substrate layer 200, then a channel layer 202 is formed on the buffer layer 201, and then a barrier layer 203 is formed on the channel layer 202, as Figure 6 shown.
[0036] The material of the substrate layer 200 is usually silicon (Si), and may also be other suitable materials such as gallium nitride (GaN), silicon carbide (SiC), sapphire, etc.
[0037] The buffer layer 201 may include one material or a combination of multiple materials such as aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium nitride (GaN), etc. The one material or the combination of multiple materials may include doping elements such as carbon (C), iron (Fe), etc., which is beneficial to reducing leakage current.
[0038] The material of the channel layer 202 is usually gallium nitride (GaN), and may also be other materials, and its energy band gap is smaller than that of the material of the barrier layer 203 located above it.
[0039] The material of the barrier layer 203 is usually aluminum gallium nitride (AlGaN), and may also be other materials, and its energy band gap is larger than that of the material of the channel layer 202 located below it.
[0040] The above structure can be formed by processes such as chemical vapor deposition, physical vapor deposition, epitaxial growth, etc.
[0041] In the second step, a preliminary P-type capping layer 194 is formed above the barrier layer 203, and then a preliminary spacer layer 295 is formed above the preliminary P-type capping layer 194, as Figure 7 shown.
[0042] The material of the preliminary P-type capping layer 194 is usually doped gallium nitride (GaN), and may also be doped aluminum gallium nitride (AlGaN) or other materials. The doped material contains magnesium (Mg) or other suitable P-type doping elements.
[0043] The preliminary separation layer 295 may include materials such as gallium oxide (GaO), gallium oxynitride (GaON), aluminum nitride (AlN), etc., or combinations thereof, whose band gaps are greater than the band gap of the preliminary p-type capping layer 194.
[0044] The above structure can be formed by processes such as chemical vapor deposition, physical vapor deposition, epitaxial growth, etc.
[0045] In the third step, processes such as photolithography, dry etching, and wet etching are performed on the surface of the preliminary separation layer 295 to form a patterned two-step separation layer 285, as Figure 8 shown.
[0046] In the fourth step, a preliminary gate metal layer 196 is formed on the surface of the two-step separation layer 285, as Figure 9 shown.
[0047] The preliminary gate metal layer 196 may be formed by processes such as evaporation plating and sputtering plating. The constituent materials may include, but are not limited to, metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), etc., their alloys, their compounds, or other suitable materials.
[0048] Generally, the preliminary gate metal layer 196 forms a Schottky contact with the preliminary p-type capping layer 194 located below it.
[0049] In the fifth step, processes such as photolithography, dry etching, and wet etching are performed on the preliminary gate metal layer 196, the two-step separation layer 285, and the preliminary p-type capping layer 194 to form a patterned gate metal layer 106, a patterned separation layer 205, and a patterned p-type capping layer 104, respectively, as Figure 10 shown.
[0050] In the sixth step, a source metal layer 207 is formed on the left side of the gate metal layer 106 and a drain metal layer 208 is formed on the right side, as Figure 11 shown.
[0051] The source metal layer 207 and the drain metal layer 208 may be formed by processes such as evaporation plating and sputtering plating. The constituent materials may include, but are not limited to, metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), etc., their alloys, their compounds, or other suitable materials.
[0052] The method of forming the patterned source metal layer 207 and the drain metal layer 208 may include processes such as photolithography, dry etching, and wet etching.
[0053] Generally, the source metal layer 207 and the drain metal layer 208 form an ohmic contact with the channel layer 202 located below them.
[0054] Those skilled in the art should know that the above manufacturing steps only list the key steps and do not show the complete steps for forming the device. The specific detailed manufacturing steps can be obtained according to the common manufacturing process steps in the art and general knowledge, and appropriate additions, deletions, and changes can be made to them.
Claims
1. A power semiconductor device, the device comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a P-type cap layer above the barrier layer, a gate metal layer above the P-type cap layer and a spacer layer, a source metal layer on one side of the gate metal layer and a drain metal layer on the other side, the channel layer and the barrier layer form a heterojunction and a two-dimensional electron gas is formed on the surface of the channel layer located below the heterojunction, characterized in that, The described P-type capping layer is used to deplete the two-dimensional electron gas on the surface of the channel layer below it when the device is turned off to form an enhancement-mode device. The P-type capping layer forms a Schottky contact with the gate metal layer above it. On both sides of the upper edge of the P-type capping layer, there are spacer layers with a bandgap greater than that of the P-type capping layer and a critical electric field greater than the critical electric field of the P-type capping layer.
2. The power semiconductor device according to claim 1, characterized in that, The boundaries of the spacer layers on both sides are the same as those of the gate metal layer, and this boundary is within the P-type capping layer.
3. The power semiconductor device according to claim 1, wherein, The boundaries of the spacer layers on both sides are the same as those of the P-type capping layer, and the boundary of the gate metal layer is within the spacer layer.
4. The power semiconductor device according to claim 3, characterized in that, The width of the spacer layer on the side close to the drain metal layer is larger than the width of the spacer layer on the side close to the source metal layer.