Field effect transistor drain-source current verification circuit

Abstract

The utility model relates to a drain-source current verification circuit of a field effect transistor. The drain-source current verification circuit is mainly composed of an external power supply, the field effect transistor, an operational amplifier, a resistor, a capacitor, a voltage stabilizing diode, an external instrument and other core components. According to the drain-source current verification circuit of the field-effect transistor, a field-effect transistor verification circuit structure capable of controlling the drain electrode voltage based on an operational amplifier is adopted, the operational amplifier is connected in series with the grid electrode of the field-effect transistor, the drain electrode voltage and the grid electrode voltage of the field-effect transistor are connected into a feedback loop, and the drain electrode voltage of the field-effect transistor is sampled by the circuit; closed-loop control is formed by comparing an operational amplifier with a reference voltage, so that setting of a drain voltage is realized by controlling a grid driving voltage of the field-effect tube, and a drain-source current verification circuit with a controllable drain voltage of the field-effect tube is formed.

Description

Technical Field

[0001] The utility model belongs to the technical field of drain-source verification of field effect transistors, and particularly relates to a drain-source current verification circuit for field effect transistors. Background Art

[0002] The drain-source current verification circuit of a field effect transistor generally consists of an external power supply, a field effect transistor, a voltmeter, and an ammeter. The function of the drain-source current verification circuit of a field effect transistor is to verify the magnitude of the current between the drain and source electrodes of the field effect transistor under different drain voltage conditions and different external environments, ensuring that it meets the system selection requirements and conforms to the product characteristics.

[0003] The existing drain-source current verification circuits of field effect transistors mainly focus on fixed drain voltage verification and manual current acquisition. It is difficult to adjust the circuit structure. The circuit structure needs to be adjusted according to different field effect transistors, and external instruments need to be connected. Moreover, the response effect is poor, the drain voltage is difficult to control, the control stability is poor, and external circuit components need to be combined according to the specific application environment. Summary of the Invention

[0004] In order to solve the deficiencies of the existing drain-source current verification circuits of field effect transistors, the present invention provides a drain-source current verification circuit for field effect transistors.

[0005] The drain-source current verification circuit for field effect transistors according to the utility model includes an amplifier IC1. The negative input terminal of the amplifier IC1 is electrically connected to the output terminal of the amplifier IC1 through a capacitor C1. The negative input terminal of the amplifier IC1 is electrically connected to one end of a resistor R6. The other end of the resistor R6 is electrically connected to the output terminal of the amplifier IC1 through a capacitor C2. The other end of the resistor R6 is electrically connected to the ground terminal through a resistor R4. The other end of the resistor R6 is electrically connected to the drain of the field effect transistor T1 to be verified through a resistor R5. The positive input terminal of the amplifier IC1 is electrically connected to one end of a resistor R1. The other end of the resistor R1 is electrically connected to the +12V power input terminal through a resistor R3. The other end of the resistor R1 is electrically connected to the negative electrode of a voltage stabilizing diode D2. The positive electrode of the voltage stabilizing diode D2 is electrically connected to the ground terminal. The output terminal of the amplifier IC1 is electrically connected to the gate of the field effect transistor T1 to be verified through a resistor R2. The gate of the field effect transistor T1 to be verified is electrically connected to the negative electrode of a voltage stabilizing diode D1. The positive electrode of the voltage stabilizing diode D1 is electrically connected to the ground terminal. The drain of the field effect transistor T1 to be verified is electrically connected to the positive electrode of a power supply DC through a resistor R7. The negative electrode of the power supply DC is electrically connected to the ground terminal.

[0006] Further, the model of the amplifier IC1 is OP42AJ.

[0007] Further, the model of the power supply DC is ES1-040-030A.

[0008] Further, the model of the field effect transistor T1 to be verified is RCS7464ET2.

[0009] The drain-source current verification circuit of the field effect transistor provided by the present utility model adopts a field effect transistor verification circuit structure with a controllable drain voltage based on an operational amplifier. An operational amplifier is connected in series to the gate of the field effect transistor, and the drain voltage and gate voltage of the field effect transistor are connected to the feedback loop. The circuit samples the drain voltage of the field effect transistor, compares it with a reference voltage through the operational amplifier to form a closed-loop control, and thus realizes the adjustment of the drain voltage by controlling the gate drive voltage of the field effect transistor, forming a drain-source current verification circuit with a controllable drain voltage of the field effect transistor.

[0010] The following will further elaborate on the present utility model in detail with reference to the accompanying drawings. Description of the Drawings

[0011] Figure 1 is a schematic diagram of the drain-source current verification circuit of the field effect transistor. Specific Embodiments

[0012] To further elaborate on the technical means and effects adopted by the present utility model to achieve the predetermined purpose, the specific embodiments, structural features, and their effects of the present utility model are described in detail as follows with reference to the accompanying drawings and embodiments.

[0013] The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0014] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "aligned", "overlapped", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present utility model.

[0015] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features; in the description of the present utility model, unless otherwise specified, the meaning of "a plurality" is two or more.

[0016] Embodiment 1

[0017] To address the deficiencies existing in the existing drain-source current verification circuit for field effect transistors, the present invention provides a drain-source current verification circuit for field effect transistors.

[0018] A drain-source current verification circuit for a field effect transistor as described in the present utility model, such as Figure 1 shown, includes an amplifier IC1. The negative input terminal of the amplifier IC1 is electrically connected to the output terminal of the amplifier IC1 through a capacitor C1. The negative input terminal of the amplifier IC1 is electrically connected to one end of a resistor R6. The other end of the resistor R6 is electrically connected to the output terminal of the amplifier IC1 through a capacitor C2. The other end of the resistor R6 is electrically connected to the ground terminal through a resistor R4. The other end of the resistor R6 is electrically connected to the drain of the field effect transistor T1 to be verified through a resistor R5. The positive input terminal of the amplifier IC1 is electrically connected to one end of a resistor R1. The other end of the resistor R1 is electrically connected to the +12V power supply input terminal through a resistor R3. The other end of the resistor R1 is electrically connected to the negative electrode of a zener diode D2. The positive electrode of the zener diode D2 is electrically connected to the ground terminal. The output terminal of the amplifier IC1 is electrically connected to the gate of the field effect transistor T1 to be verified through a resistor R2. The gate of the field effect transistor T1 to be verified is electrically connected to the negative electrode of a zener diode D1. The positive electrode of the zener diode D1 is electrically connected to the ground terminal. The drain of the field effect transistor T1 to be verified is electrically connected to the positive electrode of a power supply DC through a resistor R7. The negative electrode of the power supply DC is electrically connected to the ground terminal.

[0019] Further, the model of the amplifier IC1 is OP42AJ.

[0020] Further, the model of the power supply DC is ES1-040-030A.

[0021] Further, the model of the field effect transistor T1 to be verified is RCS7464ET2.

[0022] The power supply DC applies a DC high voltage, and a reference voltage signal is set through the zener diode D2, thereby completing the setting of the drain voltage of the field effect transistor T1 to be verified. The real-time monitoring of the drain voltage and drain-source current is completed through an external instrument.

[0023] The drain-source current verification circuit of the field effect transistor adopts a field effect transistor verification circuit structure with a controllable drain voltage implemented based on an operational amplifier. An operational amplifier is connected in series to the gate of the field effect transistor, and the drain voltage and gate voltage of the field effect transistor are connected to the feedback loop. The circuit samples the drain voltage of the field effect transistor, forms a closed-loop control by comparing it with a reference voltage through the operational amplifier, and thus realizes the adjustment of the drain voltage by controlling the gate drive voltage of the field effect transistor, forming a drain-source current verification circuit with a controllable drain voltage of the field effect transistor.

[0024] In addition, it should be noted that the drain-source current verification circuit of the field effect transistor is not limited to verifying the field effect transistor T1 to be verified with the model RCS7464ET2, and other models of field effect transistors can also be verified. In this embodiment, the field effect transistor with the model RCS7464ET2 is used as the field effect transistor to be verified mainly to illustrate the integrity of the circuit.

[0025] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A drain-source current verification circuit for a field effect transistor, characterized in that: It includes an amplifier IC1. The negative input terminal of the amplifier IC1 is electrically connected to the output terminal of the amplifier IC1 through a capacitor C1. The negative input terminal of the amplifier IC1 is electrically connected to one end of a resistor R6. The other end of the resistor R6 is electrically connected to the output terminal of the amplifier IC1 through a capacitor C2. The other end of the resistor R6 is electrically connected to the ground terminal through a resistor R4. The other end of the resistor R6 is electrically connected to the drain of the field effect transistor T1 to be verified through a resistor R5. The positive input terminal of the amplifier IC1 is electrically connected to one end of a resistor R1. The other end of the resistor R1 is electrically connected to the +12V power input terminal through a resistor R3. The other end of the resistor R1 is electrically connected to the negative electrode of a voltage stabilizing diode D2. The positive electrode of the voltage stabilizing diode D2 is electrically connected to the ground terminal. The output terminal of the amplifier IC1 is electrically connected to the gate of the field effect transistor T1 to be verified through a resistor R2. The gate of the field effect transistor T1 to be verified is electrically connected to the negative electrode of a voltage stabilizing diode D1. The positive electrode of the voltage stabilizing diode D1 is electrically connected to the ground terminal. The drain of the field effect transistor T1 to be verified is electrically connected to the positive electrode of a power supply DC through a resistor R7. The negative electrode of the power supply DC is electrically connected to the ground terminal.

2. The drain-source current verification circuit of a field effect transistor according to claim 1, characterized in that: The model of the amplifier IC1 is OP42AJ.

3. The drain-source current verification circuit of a field effect transistor according to claim 1, characterized in that: The model of the power supply DC is ES1-040-030A.

4. The drain-source current verification circuit of a field effect transistor according to claim 1, characterized in that: The model of the field effect transistor T1 to be verified is RCS7464ET2.

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