Optical device

Abstract

An optical device includes a first active layer of a first optical element, a first metallization layer over the first active layer, a first capacitance within the first metallization layer, a first bonding layer over the first metallization layer, and a first semiconductor device bonded to the first bonding layer.

Description

Technical Field

[0001] The present disclosure relates to an optical device, and more particularly to an optical device having a metallization layer. Background Art

[0002] Electrical communication and processing is a technology for signal transmission and processing. In recent years, optical communication and processing have been used in more and more applications, especially because of the use of fiber optic related applications for signal transmission.

[0003] Optical communication and processing are usually combined with electrical communication and processing to provide mature applications. For example, optical fibers can be used for long-distance signal transmission, while electrical signals can be used for short-distance signal transmission and processing and control. Therefore, a device integrating long-distance optical components and short-distance electronic components is formed for converting optical signals and electrical signals and processing optical signals and electrical signals. Therefore, the package can include both optical (photonic) dies (which include optical devices) and electronic dies (which include electronic devices). Summary of the Utility Model

[0004] The purpose of the embodiments of the present disclosure is to provide an optical device to solve at least one of the above problems.

[0005] The embodiments of the present disclosure provide an optical device, including: a first active layer of a first optical element; a first metallization layer located above the first active layer; a first capacitor located within the first metallization layer; a first bonding layer located above the first metallization layer; and a first semiconductor device bonded to the first bonding layer.

[0006] According to one embodiment of the embodiments of the present disclosure, the first optical element includes: a plurality of active optical devices; and a silicon waveguide.

[0007] According to one embodiment of the embodiments of the present disclosure, it further includes a second bonding layer electrically connected to the dielectric via hole.

[0008] The embodiments of the present disclosure provide an optical device, including: a first semiconductor device bonded to the first bonding layer; a first metallization layer located on the side opposite to the first bonding layer and the first semiconductor device; a first active layer of a first optical element located on the side opposite to the first metallization layer and the first bonding layer; a first capacitor located on the side opposite to the first active layer and the first metallization layer.

[0009] According to one embodiment of the embodiments of the present disclosure, the first capacitor is a multi-layer metal-insulator-metal structure.

[0010] Embodiments of the present disclosure provide an optical device, comprising: an interposer structure, the interposer structure comprising: a semiconductor substrate; a deep trench capacitor extending into the semiconductor substrate; and a metallization layer located above the semiconductor substrate, the metallization layer comprising a first optical element; a first optical structure bonded to the interposer structure, the first optical structure comprising: a first semiconductor device; a first active layer of the first optical element; a first metallization layer located between the first semiconductor device and the first active layer; and a first capacitor located between the first semiconductor device and the interposer structure; and a second optical structure bonded to the interposer structure, the second optical structure comprising: a second semiconductor device; a second active layer of the second optical element; a second metallization layer located between the second semiconductor device and the second active layer; and a second capacitor located between the second semiconductor device and the interposer structure.

[0011] According to one embodiment of the present disclosure, the interposer structure does not have a capacitor and includes a metal trace and an optical waveguide.

[0012] According to one embodiment of the present disclosure, the interposer structure includes a capacitor.

[0013] According to one embodiment of the present disclosure, the deep trench capacitor is located between the second active layer and the interposer structure. Description of the Drawings

[0014] The manner of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of various components can be arbitrarily enlarged or reduced.

[0015] Figure 1A A first optical package with an embedded capacitor is shown according to some embodiments.

[0016] Figure 1B A first optical package with an optional silicon nitride waveguide is shown according to some embodiments.

[0017] Figure 2A A second optical package with an embedded capacitor is shown according to some embodiments.

[0018] Figure 2B A second optical package with an optional silicon nitride waveguide is shown according to some embodiments.

[0019] Figure 3 A third optical package with a capacitor located within the substrate is shown according to some embodiments.

[0020] Figure 4AShows a fourth optical package having a capacitor located within a second substrate, according to some embodiments.

[0021] Figure 4B Shows a fourth optical package having an optional silicon nitride waveguide, according to some embodiments.

[0022] Figure 5 Shows bonding a plurality of optical packages to a capacitor structure, according to some embodiments.

[0023] The reference numerals are as follows:

[0024] 100: First optical device

[0025] 101: First active layer

[0026] 103: First optical element

[0027] 104: Lower metal layer

[0028] 105: Second insulating layer

[0029] 106: Upper metal layer

[0030] 107: First metallization layer

[0031] 108: Dielectric layer

[0032] 109: First capacitor

[0033] 110: PIC

[0034] 111: First bonding layer

[0035] 113: First dielectric material

[0036] 115: First bonding pad

[0037] 120: First semiconductor device

[0038] 121: Semiconductor substrate

[0039] 123: Active device / active layer

[0040] 125: Interconnect structure

[0041] 127: Second bonding layer

[0042] 129: Second bonding pad

[0043] 131: First passive layer

[0044] 133: Fourth optical element

[0045] 135: First TDV

[0046] 137: Third bonding pad

[0047] 139: Second dielectric material

[0048] 141: Third bonding layer

[0049] 143: Second optical element

[0050] 201: Capacitor layer

[0051] 203: Second capacitor

[0052] 205: First capacitor plate

[0053] 207: Second capacitor plate

[0054] 209: Third capacitor plate

[0055] 211: Fourth capacitor plate

[0056] 213: First capacitor dielectric

[0057] 215: Second capacitor dielectric

[0058] 217: Third capacitor dielectric

[0059] 219: Fourth capacitor dielectric

[0060] 301: Third capacitor

[0061] 303: Second substrate

[0062] 305: Contact

[0063] 307: Third metallization layer

[0064] 308: Third dielectric material

[0065] 309: Second TDV

[0066] 311: Fourth bonding pad

[0067] 313: Fourth bonding layer

[0068] 315: Fourth dielectric material

[0069] 400: Capacitor structure

[0070] 401: Fifth bonding layer

[0071] 403: Fifth dielectric material

[0072] 405: Fifth bonding pad

[0073] 500: Interposer structure

[0074] 501: Conductive wire

[0075] 502: The sixth bonding layer

[0076] 503: The third substrate

[0077] 505: The second contact

[0078] 507: The fourth metallization layer

[0079] 509: The third TDV

[0080] 511: The fifth bonding pad

[0081] 513: The laser die

[0082] 515: The sealant

[0083] 517: The optical fiber

[0084] 519: The third optical device

[0085] 521: The external connector

[0086] 523: The first optical structure

[0087] 525: The second optical structure

[0088] 527: The third optical structure Detailed implementation manners

[0089] The following disclosure provides many embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present disclosure. For example, if it is mentioned in the description that the first element is formed on the second element, it may include embodiments where the first and second elements are in direct contact, and may also include embodiments where additional elements are formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference to numerical values and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to represent the relationship between the different embodiments and / or configurations discussed.

[0090] Furthermore, relative spatial terms may be used, such as "under", "below", "lower", "above", "upper", etc., for the purpose of facilitating the description of the relationship between one (or some) component(s) or feature(s) and another (or some) component(s) or feature(s) in the drawings. Relative spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the relative spatial adjectives used therein will also be interpreted according to the turned orientation. Unless otherwise clearly stated, each element with the same reference symbol is assumed to have the same material composition and a thickness within the same thickness range.

[0091] Embodiments will now be discussed with reference to some embodiments in which one or more capacitors are integrated with optical devices within a photonic integrated circuit (PIC). However, the embodiments presented in this disclosure are intended to illustrate rather than limit the embodiments to the precise descriptions discussed. Instead, the discussed embodiments can be incorporated into a wide variety of implementations, and all such implementations are intended to be included within the scope of the embodiments.

[0092] Now referring to Figure 1A , according to some embodiments, a first optical device 100 is shown. The first optical device 100 includes a PIC 110 and a first semiconductor device 120. In Figure 1A the specific embodiment shown, the PIC 100 includes a first active layer 101 of a first optical element 103. In some embodiments, the first active layer 101 of the first optical element 103 may include, for example, optical waveguides (such as ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), couplers (such as grating couplers, edge couplers, etc.), directional couplers, optical modulators (such as Mach-Zehnder silicon-photonics switches, microelectromechanical switches, micro-ring resonators, etc.), amplifiers, multiplexers, demultiplexers, optoelectronic converters (such as P-N junctions), electro-optic converters, lasers, combinations thereof, or similar elements. However, any suitable first optical element 103 can be used.

[0093] The second insulating layer 105 surrounds and / or covers the first optical element 103 and provides additional cladding material. In one embodiment, the second insulating layer 105 can be a dielectric layer that separates the various elements of the first active layer 101 from each other and from the overlying structure and can act as another part of the cladding material surrounding the first optical element 103. In one embodiment, the second insulating layer 105 can be silicon oxide, silicon nitride, germanium oxide, germanium nitride, a combination thereof, or the like. However, any suitable materials and manufacturing methods can be used.

[0094] Figure 1A Also shown is a first metallization layer 107 that electrically connects the first active layer 101 of the first optical element 103 to a control circuit, to each other, and to an attached device. In one embodiment, the first metallization layer 107 is an alternating film layer of dielectric and conductive materials. In a particular embodiment, there can be multiple metallization layers, such as approximately six metal layers, for interconnecting the various first optical elements 103, but the exact number of metallization layers 107 depends on the design of the PIC 110.

[0095] In some embodiments, the first metallization layer 107 can also include one or more first capacitors 109 that are located within the first metallization layer 107 and are electrically connected to the conductive portions of the first metallization layer 107. In one embodiment, the first capacitor 109 can be a metal-insulator-metal (MIM) capacitor, a super high performance MIM (SHP-MIM) capacitor, a deep trench capacitor (DTC), a stacked-capacitor (STC), a combination thereof, or the like. In a particular embodiment where the first capacitor 109 is a MIM capacitor, each first capacitor 109 includes a lower metal layer 104, an upper metal layer 106 (such as a copper layer), and a dielectric layer 108 (such as a high-k dielectric layer) between the metal layers. However, any suitable structure can be used.

[0096] The lower metal layer 104 of the first capacitor 109 can be electrically coupled to the conductive components of the first metallization layer 107, for example, through vias extending from the lower metal layer 104 of the first capacitor 109 to the conductive components of the first metallization layer 107. Additionally, multiple first capacitors 109 can be electrically coupled in parallel to provide a large capacitance value. For example, the upper metal layers 106 of the first capacitors 109 can be electrically coupled together, and the lower metal layers 104 of the first capacitors 109 can be electrically coupled together.

[0097] The first bonding layer 111 is located above the first metallization layer 107. In one embodiment, the first bonding layer 111 can be used for dielectric-to-dielectric and metal-to-metal bonding. According to some embodiments, the first bonding layer 111 includes a first dielectric material 113, such as silicon oxide, silicon nitride, or the like. However, any suitable material can be used.

[0098] The first bonding pad 115 is located within the first bonding layer 111. In one embodiment, the first bonding pad 115 includes a seed layer and a plate metal, where the seed layer can include a copper layer, and the plate metal can include copper, a copper alloy, or the like. A barrier layer (not shown separately) can be located along the position of the first dielectric material 113 and the seed layer. The barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. In some embodiments, bonding pad vias can also be used to connect the first bonding pad 115 to the underlying conductive structure and connect the first bonding pad 115 to the first metallization layer 107 through the underlying conductive portion.

[0099] Additionally, the first bonding layer 111 can optionally include one or more third optical elements (not shown separately), which are incorporated within the first bonding layer 111. In such an embodiment, the one or more third optical elements can be of a material similar to the one or more first optical elements (as described above), such as being waveguides and other structures. However, any suitable structure and material can be used.

[0100] The first semiconductor device 120 is bonded to the PIC 110. In some embodiments, the first semiconductor device 120 is an electronic integrated circuit (EIC) (e.g., a device without optical devices), and can have a semiconductor substrate 121, a film layer of active devices 123, an overlying interconnect structure 125, a second bonding layer 127, and an associated second bonding pad 129. In one embodiment, the semiconductor substrate 121 can be a semiconductor material, such as silicon or silicon germanium; the active layer 123 can be a transistor, capacitor, resistor, or the like formed above the semiconductor substrate 121; the interconnect structure 125 can be similar to the first metallization layer 107 (without optical elements but having between approximately 1 to 14 metal layers); the second bonding layer 127 can be similar to the first bonding layer 111; and the second bonding pad 129 can be similar to the first bonding pad 115. However, any suitable device can be used.

[0101] In one embodiment, the first semiconductor device 120 can be configured to work with the PIC 110 to achieve the desired functions. In some embodiments, the first semiconductor device 120 can be a high bandwidth memory (HBM), xPU, logic die, three-dimensional integrated circuit (3DIC), central processing unit, graphics processing unit (GPU), system on chip (SoC), microelectromechanical system (MEMs), combinations thereof, or the like. Any suitable device with any suitable function can be used, and all such devices are intended to be included within the scope of the embodiments.

[0102] (three-dmientional integrated circuit; 3DIC), central processing unit, graphics processing unit (GPU), system on chip (SoC), microelectromechanical system (MEMs), combinations thereof, or the like. Any suitable device with any suitable function can be used, and all such devices are intended to be included within the scope of the embodiments.

[0103] The first semiconductor device 120 is bonded to the PIC 110 using, for example, dielectric-to-dielectric and metal-to-metal bonding. In such an embodiment, the first semiconductor device 120 is bonded to the first bonding layer 111 of the PIC 110 by bonding the first bonding pad 115 to the second bonding pad 129 and by bonding the dielectric within the first bonding layer 111 to the dielectric within the second bonding layer 127. However, while the above description describes dielectric-to-dielectric and metal-to-metal bonding, this is intended to be illustrative and not limiting. In still other embodiments, the PIC 110 can be bonded to the first semiconductor 120 by metal-to-metal bonding. For example, the first semiconductor device 120 and the PIC 110 can be bonded by metal-to-metal bonding. Any suitable bonding can be used, and all such bondings are fully intended to be included within the scope of the embodiments.

[0104] Figure 1A The first passive layer 131 of the fourth optical element 133 located above the backside of the first active layer 101 is additionally shown. In one embodiment, the first passive layer 131 of the fourth optical element 133 can use a structure and material similar to that of the second optical element of the first metallization layer 107. For example, the first passive layer 131 of the fourth optical element 133 can be an alternating film layer of a cladding material (such as silicon oxide) and a core material (such as silicon nitride in structures such as waveguides and the like). In a particular embodiment, the fourth optical element 133 includes a plurality of silicon nitride waveguides surrounded by a cladding material such as silicon oxide. However, any suitable structure and any suitable material can be used.

[0105] Figure 1AAdditionally shown is a first through dielectric via (TDV) 135 and a third bonding pad 137. In one embodiment, the first TDV 135 extends through the first passive layer 131 and the first active layer 101 to provide a fast path for power, data, and ground through the PIC 110. The first TDV 135 electrically connects the first metallization layer 107, the first capacitor 109, and the first semiconductor device 120 to the opposite side of the device.

[0106] In one embodiment, the first TDV 135 includes a liner layer, a barrier layer, and a first conductive material. The liner layer can be formed, for example, from tetraethylorthosilicate (TEOS) oxide or silicon nitride, although any suitable dielectric material can be used. The barrier layer (not shown separately) is adjacent to the liner layer, and the first conductive material can include copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, or the like can be used.

[0107] Optionally, in some embodiments, a second metallization layer (not shown separately in Figure 1A FIG.) can be located at a position electrically connected to the first TDV 135. In one embodiment, the second metallization layer can be as described above with reference to the first metallization layer 107, for example, an alternating film layer of dielectric and conductive materials. However, any suitable structure can be used.

[0108] The third bonding pad 137 can be located within the second dielectric material 139 of the third bonding layer 141 and provides a conductive region for contact between the first TDV 135 or between the second metallization layer and other external devices. In one embodiment, the third bonding layer 141, the second dielectric material 139, and the third bonding pad 139 can be similar to the first bonding layer 111, the first dielectric material 113, and the first bonding pad 115 described above. However, any suitable methods and materials can be used.

[0109] Optionally, although not specifically shown in Figure 1A FIG., the third bonding pad 139 can be connected to additional external connectors for electrical connection to other devices. For example, dielectric-to-dielectric and metal-to-metal bonding can be used to bond the third bonding pad 137 to a microbump, a ball grid array, combinations thereof, or the like. However, any suitable physical and electrical connectors can be used.

[0110] By using the first capacitor 109 as described above, the EIC process can be used to integrate the first capacitor 109 within the first metallization layer 107, which helps to improve the power integrity of the first semiconductor device 120 and thus improve the overall performance. Therefore, the first capacitor 109 can be located close to the first semiconductor device 120, having a small equivalent series resistance (ESR) and a small equivalent series inductance (ESL), and a capacitance density between about 20 nF / mm 2 to about 100 nF / mm 2 of capacitance density.

[0111] Figure 1B An alternative embodiment is shown in which one or more second optical elements 143 are included as part of the first metallization layer 107. In some embodiments, the second optical elements 143 of the first metallization layer 107 may include, for example, couplers for connecting external signals (such as edge couplers, grating couplers, etc.), optical waveguides (such as ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), optical modulators (such as Mach-Zehnder silicon-photonic switches, microelectromechanical switches, microring resonators, etc.), amplifiers, multiplexers, demultiplexers, optoelectronic converters (such as PN junctions), electro-optic converters, lasers, combinations thereof, or similar elements. In a particular embodiment, one or more second optical elements 143 are silicon nitride waveguides optically connected to the underlying first optical element 103. However, any suitable optical element can be used for the one or more second optical elements 143.

[0112] Figure 2A Another embodiment is shown in which the PIC 110 is bonded to the first semiconductor device 120. In this embodiment, however, the first capacitor 109 is not formed within the first metallization layer 107 (as described above with reference to Figure 1A ), but is formed within a capacitor layer 201 located on the side opposite to the first active layer 101 and the first semiconductor device 120. In this embodiment, the first semiconductor device 120, the first active layer 101, the first metallization layer 107 (with or without the first capacitor 109), and the first passive layer 131 can all be as described above with reference to Figure 1A . However, any suitable structure can be used.

[0113] In this embodiment, however, the capacitor layer 201 is adjacent to the first passive layer 131 and may include one or more second capacitors 203. In one embodiment, the one or more second capacitors 203 may include super high performance metal-insulator-metal (SHP-MIM) capacitors, MIM capacitors, deep trench capacitors, combinations thereof, or the like. However, any suitable type of capacitor may be used.

[0114] In a particular embodiment where the second capacitor 203 is an SHP-MIM capacitor, the second capacitor 203 includes a plurality of plates that are separately separated by a plurality of film layers of a capacitor dielectric. In a particular embodiment, the second capacitor 203 may include a first capacitor plate 205, a second capacitor plate 207, a third capacitor plate 209, and a fourth capacitor plate 211, where at least a portion of the first capacitor plate 205, at least a portion of the second capacitor plate 207, at least a portion of the third capacitor plate 209, and at least a portion of the fourth capacitor plate 211 overlap each other. In this embodiment, the first capacitor plate 205, the second capacitor plate 207, the third capacitor plate 209, and the fourth capacitor plate 211 may include a conductive material such as titanium nitride, tantalum nitride, titanium aluminum, combinations thereof, or the like. However, any suitable material may be used.

[0115] Additionally, in this embodiment, the first capacitor plate 205, the second capacitor plate 207, the third capacitor plate 209, and the fourth capacitor plate 211 are separated from each other by at least a first capacitor dielectric 213, at least a second capacitor dielectric 215, at least a third capacitor dielectric 217, and at least a fourth capacitor dielectric 219. In one embodiment, the first capacitor dielectric 213, the second capacitor dielectric 215, the third capacitor dielectric 217, and the fourth capacitor dielectric 219 may be one or more layers of high dielectric constant materials such as zirconium oxide, aluminum oxide, hafnium oxide, combinations thereof, or the like. One or more second capacitors 203 having all of the film layers may have a thickness between approximately and approximately . However, any suitable material may be used.

[0116] In this embodiment, the TDV 135 extends through one or more second capacitors 203 located within the capacitor layer 201. The TDV 135 electrically connects individual ones of the first capacitor plate 205, the second capacitor plate 207, the third capacitor plate 209, and the fourth capacitor plate 211 to each other, to the first metallization layer 107, to the first semiconductor device 120, and to the third bonding pad for an external connection. In one embodiment, the TDV 135 may be as described above with reference to Figure 1Aas described. However, any suitable connection structure may be used.

[0117] In addition, a third bonding layer 141 having a second dielectric material 139 and a third bonding pad 137 are located above the capacitor layer 201 and are electrically connected to the TDV 135. Accordingly, the third bonding pad 137 provides an electrical connection to the second capacitor 203.

[0118] Optionally, although not shown in Figure 2A , the third bonding layer 137 may be connected to additional external connectors for electrical connection to other devices. For example, the third bonding pad 137 may be connected to microbumps, ball grid arrays, combinations thereof, or the like using dielectric-to-dielectric and metal-to-metal bonding. However, any suitable physical and electrical connectors.

[0119] By using the second capacitor 203 within the capacitor layer 201 as described above, the second capacitor 203 (e.g., SHP-MIM) can be integrated into the backside of the PIC 110 using a 3nm node process and / or a 2nm node process. Accordingly, the capacitance density (e.g., 33 nF / mm 2 , 66 nF / mm 2 , 100 nF / mm 2 ) can be flexibly selected without requiring a large-scale redesign. Accordingly, greater flexibility of the device can be obtained.

[0120] Figure 2B shows an alternative embodiment of the structure shown in Figure 2A above, but it includes one or more optional second optical elements 143 within the first metallization layer 107. In a particular embodiment, the one or more second optical elements 143 may include silicon nitride waveguides. However, any suitable elements may be used.

[0121] Figure 3 shows another embodiment in which the PIC 110 is bonded to a first semiconductor device 120 having a capacitor. In this embodiment, however, the third capacitor 301 is not located within the capacitor layer 201 (as described above with reference to Figure 2A ) or within the first metallization layer 107 (as described above with reference to Figure 1A ), but is located within a second substrate 303, which is located on the side opposite the first active layer and the first semiconductor device 120. In one embodiment, the second substrate 303 may be a semiconductor material, such as silicon or silicon germanium, a dielectric material, such as glass, or any other suitable material that allows for structural support of the device above.

[0122] The third capacitor 301 may be formed on or at least partially within the second substrate 303. In some embodiments, the third capacitor 301 may be a deep trench capacitor, a MIM capacitor, a SHP-MIM capacitor, a combination thereof, or the like. However, any suitable capacitor may be used.

[0123] In an embodiment where the third capacitor 301 is a deep trench capacitor, the third capacitor 301 extends into the second substrate 303 and includes multiple film layers of conductive material (also not shown separately in Figure 3 ) alternating with a film layer of dielectric material (also not shown separately in Figure 3 ). The third capacitors 301 may be interconnected in a parallel configuration, and the thickness of the third capacitor may be between approximately 5 μm and approximately 8 μm.

[0124] A liner layer may be used to separate the material of the third capacitor 301 from the second substrate 303, and the deep trench capacitor may include a series of alternating film layers of conductive and dielectric materials. In one embodiment, the liner layer may be a dielectric material, such as silicon oxide, the conductive material may be a conductive material such as titanium nitride, and the dielectric material may be one or more layers of high dielectric constant materials, such as zirconium oxide, aluminum oxide, hafnium oxide, a combination thereof, or the like. In a particular embodiment, there are four layers of conductive material and three layers of dielectric material. However, any suitable materials and any suitable number of alternating film layers may be used.

[0125] A third metallization layer 307 with contacts 305 is located above the third capacitor 301 to provide an electrical connection, such as between the third capacitor 301 and the TDV 135. In one embodiment, the third metallization layer 307 and the contacts 305 may be similar to the first metallization layer 107 (with or without optical devices), for example, by using one or more alternating layers of a third dielectric material 308 and a conductive material to form the contacts 305 and any other desired conductive connections. However, any suitable materials may be used to form the third metallization layer 307 with contacts 305.

[0126] In a particular embodiment, the second substrate 303, the third dielectric material 308, and the raw material for the first optical element 103 may be formed as part of a silicon-on-insulator (SOI) substrate. In other embodiments, the second substrate 303, the third dielectric material 308, and the raw material for the first optical element 103 are not part of an SOI substrate and may be subsequently formed above the second substrate 303. Any suitable structure may be used.

[0127] In this embodiment, the second TDV 309 extends through the second substrate 303, the third metallization layer 307, the first active layer 101, and extends to the first metallization layer 107, and the contact 305 is used to electrically connect to the third capacitor 301. The second TDV 309 electrically connects the contact 305 and one of the third capacitors 301 to the first metallization layer 107, to the first semiconductor device 120, and to the third bonding pad 137 for the external connection. In one embodiment, the second TDV 309 can be similar to the TDV 135 referred to above Figure 1A as described. However, any suitable connection structure can be used.

[0128] In addition, a fourth bonding layer having a fourth bonding pad 311 located in the fourth dielectric material 315 is electrically connected to the second TDV 309 to provide an external connection. In one embodiment, the fourth bonding layer 313, the fourth dielectric material 315, and the fourth bonding pad 311 can be similar to the third bonding pad 141, the second dielectric material 139, and the third bonding pad 137 referred to above Figure 1A as described. However, any suitable connection structure can be used.

[0129] Optionally, although Figure 3 not specifically shown in, the fourth bonding pad 311 can be connected to additional external connectors for electrically connecting to other devices. For example, dielectric-to-dielectric and metal-to-metal bonding can be used to connect the fourth bonding pad 311 to microbumps, ball grid arrays, combinations thereof, or the like. However, any suitable physical connector and electrical connector.

[0130] By using the third capacitor 301 within the second substrate 303 as described above, the third capacitor 301 can be integrated into the SOI carrier of the PIC 110 using, for example, a chip on wafer on substrate (CoWoS) integrated capacitor (iCAP) process. Therefore, the capacitance density can be increased to approximately 1100 nF / mm 2 . Therefore, greater flexibility of the device can be obtained.

[0131] Figure 4A Another embodiment is shown in which the capacitor is integrated on the side opposite the first active layer 101 and the first semiconductor device 120. In this embodiment, however, the third capacitor 301 is not within the first metallization layer 107 (as referred to above Figure 1A as described), or adjacent to the first passive layer 131 (as referred to above Figure 2A as described), or within the second substrate 303 without the first passive layer 131 (as referred to above Figure 3Rather, it is located within the separated capacitive structure 400, which includes a second substrate 303 and is adjacent to the first passive layer 131.

[0132] In this embodiment, the PIC 110 and the first semiconductor device 120 may be as described above with reference to Figure 1A However, the first capacitor 109 is not formed within the first metal layer 107. In particular, the first passive layer 131, the first TDV 135, and the third bonding pad 137 are present within the PIC 110, while the third capacitor 301 within the second substrate 303 is not present within the PIC 110.

[0133] Conversely, the third capacitor 301 within the second substrate 303, the third metallization layer 307 with contacts 305, the second TDV 309, and the fourth bonding pad 311 are separated from the PIC 110. In this embodiment, the third capacitor 301 within the second substrate 303, the third metallization layer 307 with contacts 305, the second TDV 309, and the fourth bonding pad 311 are separated from the PIC 110 and are bonded to the PIC 110 using, for example, a fifth bonding layer. In one embodiment, the fifth bonding layer 401 may include a fifth dielectric material 403 and a fifth bonding pad 405, and the fifth bonding layer 401, the fifth dielectric material 403, and the fifth bonding pad 405 may be similar to the fourth bonding layer 313, the fourth dielectric material 315, and the fourth bonding pad 311. Additionally, the fifth bonding layer 401 may be bonded to the PIC 110 using, for example, dielectric-to-dielectric and metal-to-metal bonding, although any suitable bonding may be used.

[0134] Optionally, although not specifically shown in Figure 4A the fourth bonding pad 311 may be connected to additional external connectors for electrical connection to other devices. For example, the fourth bonding pad 311 may be connected to microbumps, ball grid arrays, combinations thereof, or the like using dielectric-to-dielectric and metal-to-metal bonding. However, any suitable physical and electrical connectors may be used.

[0135] By using the third capacitor 301 within the second substrate 303 that is bonded to the PIC 110 rather than being integrated as part of the PIC 110, the third capacitor 301 (e.g., a deep trench capacitor) can be integrated within the capacitive structure 400 and then the capacitive structure 400 can be bonded to this structure. Thus, the capacitance density can be increased to approximately 1100 nF / mm 2 while still improving design and process flexibility. Therefore, greater flexibility of the device can be obtained.

[0136] Figure 4B is shown above Figure 4AAn alternative embodiment of the structure shown, but which includes one or more optional second optical elements 143 within the first metallization layer 107. In a particular embodiment, the one or more optional second optical elements 143 may include silicon nitride waveguides. However, any suitable element may be used.

[0137] Figure 5 An embodiment is shown in which a plurality of the first optical devices 100 are bonded to a separate interposer structure 500, the interposer structure 500 being a composite interposer. In Figure 5 the embodiment shown, the interposer structure 500 includes a third substrate 503 (similar to the second substrate 303), a third capacitor 301 formed within the third substrate 503, a fifth bonding pad 511 (similar to the fourth bonding pad 311), a sixth bonding layer 502 (similar to the fifth bonding layer 401), and a third TDV 509 (similar to the second TDV 309). Additionally, the fourth metallization layer 507 (similar to the third metallization layer 307) includes not only a second contact 505 (similar to the contact 305), but also additionally includes a conductive line 501 and a third optical device 519.

[0138] Additionally, in this embodiment, an external connection 521 may be placed over the fifth bonding pad 511. In one embodiment, the external connection 521 may be a bump, such as a solder ball, a microbump, or a ball grid array. However, any suitable external connection may be used, such as a copper pillar.

[0139] In this embodiment, several of the first optical devices 100, such as a first optical structure 523, a second optical structure 525, and a third optical structure 527, are bonded to the sixth bonding layer 502. Each of the first optical structure 523, the second optical structure 525, and the third optical structure 527 may be any one of the first optical devices 100 described above with reference to FIGS. 1-4, and the first semiconductor devices 120 within each of the first optical structure 523, the second optical structure 525, and the third optical structure 527 may have different functions that work together. For example, the first semiconductor device 120 within the first optical structure 523 may be a GPU, the first semiconductor device 120 within the second optical structure 525 may be a CPU, and the first semiconductor device 120 within the third optical structure 527 may be a memory device. However, any suitable function may be used.

[0140] The first optical structure 523, the second optical structure 525, and the third optical structure 527 are bonded to the sixth bonding layer 502 of the interposer structure 500. In one embodiment, the first optical structure 523, the second optical structure 525, and the third optical structure 527 are bonded using dielectric-to-dielectric and metal-to-metal bonding. However, any suitable bonding can be used, such as by using microbumps, ball grid arrays, or the like.

[0141] Additionally, in this embodiment, the laser die 513 can also be bonded to the interposer structure 500. In some embodiments, the laser die 513 can be used to generate light to power other optical elements (such as the first optical element 103, the second optical element 143, the third optical element, etc. located within the first optical structure 523, the second optical structure 525, the third optical structure 527, etc.), and can include a light generating structure, such as one or more laser diodes (not shown separately). In a particular embodiment, the laser diode can be a Fabry - Perot diode, and can be based on group III - V materials, group II - VI materials, or any other suitable material group.

[0142] In a particular embodiment, the laser die 513 can include a first contact, a first buffer layer, a first active diode layer including multiple quantum wells (MQWs), a second buffer layer, and a second contact to generate the desired light. Additionally, the generated light can be output from the laser die 513 through, for example, the first contact and into the fourth metallization layer 507. However, any suitable structure can be used to form the laser die 513 and generate the desired light.

[0143] The laser die 513 can be bonded to the interposer structure 500. In one embodiment, dielectric-to-dielectric and metal-to-metal bonding can be used to bond the laser die 513. However, any suitable bonding can be used.

[0144] Additionally, the first optical structure 523, the second optical structure 525, the third optical structure 527, and the laser die 513 are sealed by a sealant 515. In one embodiment, the sealant 515 can be a molding compound, an epoxy resin, or the like, and can have or not have a top surface coplanar with the top surfaces of the first optical structure 523, the second optical structure 525, the third optical structure 527, and the laser die 513.

[0145] Use an optical fiber 517 as the input / output port of the interposer structure 500. In one embodiment, the optical fiber 517 is placed to optically couple the optical fiber 517 to an optical input end (such as an edge coupler that is part of a third optical device 519 within a fourth metallization layer 507). By positioning the optical fiber 517 in this way, the optical signal leaving the optical fiber 517 is directed to, for example, the third optical device 519 within the fourth metallization layer 507 and reaches the first optical structure 523, the second optical structure 525, the third optical structure 527, and reaches between the first optical structure 523, the second optical structure 525, and the third optical structure 527. Similarly, the optical fiber 517 is positioned so that the optical signal leaving the third optical device 519 in the fourth metallization layer 507 is directed into the optical fiber 517 for transmission. However, any suitable location can be used.

[0146] For example, an optical glue (not shown separately in Figure 5 ) can be used to fix the optical fiber 517 in place. In some embodiments, the optical glue includes a polymer material, such as epoxy-acrylate oligomers, and can have a refractive index between approximately 1 and approximately 3. However, any suitable material can be used.

[0147] In one embodiment, a semiconductor device includes: a first active layer of a first optical element; a first metallization layer located above the first active layer; a first capacitor located within the first metallization layer; a first bonding layer located above the first metallization layer; and a first semiconductor device bonded to the first bonding layer. In one embodiment, the first capacitor is a metal-insulator-metal capacitor. In one embodiment, this semiconductor device further includes a second active layer of a second optical element located on the side opposite to the first active layer and the first metallization layer. In one embodiment, this semiconductor device further includes a through device via that extends through the second active layer and the first active layer. In one embodiment, this semiconductor device further includes a second bonding layer electrically connected to the through device via. In one embodiment, the first semiconductor device is bonded to the first bonding layer using dielectric-to-dielectric and metal-to-metal bonding. In one embodiment, the capacitance density of the first capacitor is approximately 20 nF / mm 2 and approximately 100 nF / mm 2 .

[0148] In another embodiment, a semiconductor device includes: a first semiconductor device bonded to a first bonding layer; a first metallization layer located on a side opposite to the first bonding layer and the first semiconductor device; a first active layer of a first optical element located on a side opposite to the first metallization layer and the first bonding layer; and a first capacitor located on a side opposite to the first active layer and the first metallization layer. In one embodiment, the first capacitor is an ultra-high performance metal-insulator-metal capacitor. In one embodiment, the semiconductor device further includes a second bonding layer located on a side opposite to the first capacitor and the first active layer. In one embodiment, the first capacitor is a deep trench capacitor located within a semiconductor substrate. In one embodiment, the semiconductor device further includes a second bonding layer located between the first capacitor and the first active layer. In one embodiment, the semiconductor device further includes a second active layer of a second optical element located between the first capacitor and the first active layer. In one embodiment, the semiconductor device further includes a device via extending through the semiconductor substrate and the first active layer and at least partially into the first metallization layer.

[0149] In yet another embodiment, a semiconductor device includes: a capacitor structure including: a semiconductor substrate; a deep trench capacitor extending into the semiconductor substrate; and a metallization layer located above the semiconductor substrate, the metallization layer including a first optical element; a first optical structure bonded to the capacitor structure, the first optical structure including: a first semiconductor device; a first active layer of a first optical element; a first metallization layer located between the first semiconductor device and the first active layer; and a first capacitor located between the first semiconductor device and the capacitor structure; and a second optical structure bonded to the capacitor structure, the second optical structure including: a second semiconductor device; a second active layer of a second optical element; a second metallization layer located between the second semiconductor device and the second active layer; and a second capacitor located between the second semiconductor device and the capacitor structure. In one embodiment, the first semiconductor device is a GPU and the second semiconductor device is a CPU. In one embodiment, the first semiconductor device further includes a laser die bonded to the capacitor structure. In one embodiment, the laser die, the first optical device, and the second optical device are sealed by a sealant. In one embodiment, the first semiconductor device further includes an optical fiber for an edge coupler located within the metallization layer. In one embodiment, the second capacitor is located between the second active layer and the capacitor structure.

[0150] The foregoing outlines components of several embodiments so that those skilled in the art of the present disclosure can more readily understand the concepts of the present disclosure. Those skilled in the art of the present disclosure should understand that they can, based on the disclosure, design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art of the present disclosure should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present disclosure.

Claims

1. An optical device, characterized in that, Comprising: A first active layer of a plurality of first optical elements; A first metallization layer located above the first active layer; A first capacitor located within the first metallization layer; A first bonding layer located above the first metallization layer; And A first semiconductor device bonded to the first bonding layer.

2. The optical device according to claim 1, wherein, The first optical element comprises: A plurality of active optical devices; and A silicon waveguide.

3. The optical device according to claim 1 or 2, characterized in that, It further includes a second bonding layer electrically connected to a dielectric via hole.

4. An optical device, characterized in that, Comprising: A first semiconductor device bonded to a first bonding layer; A first metallization layer located on the side opposite to the first bonding layer and the first semiconductor device; A first active layer of a plurality of first optical elements located on the side opposite to the first metallization layer and the first bonding layer; A first capacitor located on the side opposite to the first active layer and the first metallization layer.

5. The optical device according to claim 4, wherein, The first active layer of the first optical element comprises: A plurality of active optical devices; and At least one silicon waveguide.

6. The optical device according to claim 4, wherein The first capacitor is a multi-layer metal-insulator-metal structure.

7. An optical device, characterized in that, Comprising: An interposer structure, the interposer structure comprising: A semiconductor substrate; A deep trench capacitor extending into the semiconductor substrate; and A metallization layer located above the semiconductor substrate, the metallization layer including a plurality of first optical elements; A first optical structure bonded to the interposer structure, the first optical structure comprising: A first semiconductor device; A first active layer of a plurality of first optical elements; A first metallization layer located between the first semiconductor device and the first active layer; and A first capacitor located between the first semiconductor device and the interposer structure; and A second optical structure bonded to the interposer structure, the second optical structure comprising: A second semiconductor device; A second active layer of a plurality of second optical elements; A second metallization layer located between the second semiconductor device and the second active layer; and A second capacitor located between the second semiconductor device and the interposer structure.

8. The optical device according to claim 7, wherein The interposer structure does not have a capacitor and includes a metal trace and an optical waveguide.

9. The optical device according to claim 7, wherein The interposer structure includes a capacitor.

10. The optical device according to claim 7, wherein, The deep trench capacitor is located between the second active layer and the interposer structure.

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