Clock burr fault injector
By designing a clock glitch fault injector, using the status adjustment of the BP port and the GATE port to realize arbitrary glitch injection of the clock signal, solving the problem that the existing technology cannot add glitches in the safety analysis process, and improving the effectiveness of integrated circuit safety analysis.
Patent Information
- Application Number
- CN202422408212.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2034-09-30
AI Technical Summary
The prior art cannot add arbitrarily to the clock signal during the safety analysis process, which affects the effectiveness of the analysis of integrated circuit safety.
A clock glitch fault injector is designed, and any glitch injection to the clock signal is realized through the circuit path composed of the main clock port, the glitch port, the BP port, the first relay, the second relay and the GATE port.
It improves the effectiveness of safety analysis of integrated circuit operating clocks, can generate clock signals with arbitrary glitches, and enhances the accuracy of safety analysis.
Smart Images
Figure CN223141897U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the fields of integrated circuits and information security, and particularly to a clock glitch fault injector. Background Art
[0002] Integrated circuits are carriers of data and play a crucial role in ensuring the security of information systems. Various technical methods are often used to analyze the security of integrated circuits.
[0003] For digital integrated circuits, the clock is an essential condition for their normal operation. Therefore, there is a possibility of affecting the security of integrated circuits by manipulating the working clock. In the prior art, the methods for analyzing the security of manipulating the working clock can only analyze the clock security by changing the amplitude, frequency, and duty cycle of the clock signal.
[0004] However, in actual work, the clock signal often has glitches due to clock source switching, and the existing injection methods cannot arbitrarily add glitches to the clock signal during the security analysis process. Therefore, how to provide a device that can arbitrarily add glitches to the clock signal to improve the effectiveness of the security analysis of the working clock has become an urgent problem to be solved. Summary of the Utility Model
[0005] The utility model provides a clock glitch fault injector to solve the problem that glitches cannot be arbitrarily added to the clock signal during the security analysis process in the prior art.
[0006] To achieve the above object, the technical solution of the utility model provides a clock glitch fault injector, which includes: a substrate, a main clock port, a glitch port, a first relay, a second relay, a BP port, and a GATE port. The main clock port, the glitch port, the BP port, the first relay, the GATE port, the first switching end of the second relay, and the common end of the second relay form a clock glitch fault injection circuit path.
[0007] As a preference of the above technical solution, preferably, the BP port is connected to the switching head of the first relay, and the GATE port is connected to the switching head of the second relay; the common end of the first relay is connected in series with the first switching end of the second relay; the main clock port and the glitch port are respectively connected to the first switching end and the second switching end of the first relay.
[0008] As a preference of the above technical solution, preferably, the switching head of the first relay connects the first switching end and the common end or the second switching end and the common end inside it according to the action of the BP port.
[0009] Preferably, as an optimization of the above technical solution, the second switching end of the second relay is left floating.
[0010] Preferably, as an optimization of the above technical solution, the switching head of the second relay connects the first switch therein to its common terminal or opens the second relay according to the action of the GATE port.
[0011] Preferably, as an optimization of the above technical solution, the first relay and the second relay are arranged at the center of the substrate, and the remaining electronic components are arranged around the first relay and the second relay.
[0012] The technical solution of the present utility model provides a clock glitch fault injector. The master clock port, the glitch port, the BP port, the first relay, the GATE port, the first switching end of the second relay, and the common terminal of the second relay form a clock glitch fault injection circuit path. By adjusting the respective output states of the BP port and / or the GATE port, the purpose of arbitrarily adding glitches to the clock signal is achieved, and the effectiveness of performing safety analysis by manipulating the working clock is improved. Description of the Drawings
[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0014] Figure 1 It is an external structure diagram of a clock glitch fault injector provided by the present utility model.
[0015] Figure 2 It is a signal schematic diagram of the BP port in a clock glitch fault injector provided by the present utility model.
[0016] Figure 3 It is a signal schematic diagram of the GATE port in a clock glitch fault injector provided by the present utility model.
[0017] Figure 4 It is a circuit switching structure schematic diagram of two relays in a clock glitch fault injector provided by the present utility model. Detailed Embodiments
[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present utility model clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present utility model with reference to the accompanying drawings in the embodiments of the present utility model. Apparently, the described embodiments are some, but not all, of the embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts fall within the scope of protection of the present utility model.
[0019] The present utility model provides a clock glitch fault injector, which includes: a substrate 101, a power switch 102, a communication interface 103, a BP port 104, a main clock port 105, a glitch port 106, a first relay 120, a second relay 130, a GATE port 107, a counting port 108, an indicator light port 109, and an output port 110.
[0020] The substrate 101 is used to carry all the electronic components of the clock glitch fault injector provided by the present utility model and the connecting wires between the components. As Figure 1 shown: The first relay 120 and the second relay 130 are arranged in the center of the substrate 101, and the remaining electronic components are installed on the edge of the upper surface of the substrate 101 around the first relay 120 and the second relay 130.
[0021] The first relay 120 has a first switching end S1a, a second switching end S2a, a common end C1, and a switching head S3a.
[0022] The second relay 130 has a first switching end S1b, a second switching end S2b, a common end C2, and a switching head S3b.
[0023] Specifically, the main clock port 105, the glitch port 106, the BP port 104, the first relay 120, the GATE port 107, the first switching end S1b of the second relay 130, and the common end C2 of the second relay 130 form a clock glitch fault injection circuit path.
[0024] For the first relay 120, the BP port 104 is connected to the switching head S3a, the main clock port 105 is connected to the first switching end S1a, and the glitch port is connected to the second switching end S1b.
[0025] For the second relay 130, the GATE port 107 is connected to the switching head S3b, its first switching end S1b is connected in series with the common end S3a of the first relay 120, its second switching end S2b is left floating, and its common end C2 is connected to the output port 110.
[0026] The switching head S3b of the second relay 130 connects the first switching end S1b therein to its common end S3b or opens the second relay 130 following the action of the GATE port 107. When the first relay 120 and the second relay 130 form a series connection path, the switching head S3a of the first relay 120 connects the first switching end S1a therein to its common end C1 or the second switching end S2a therein to its common end C1 following the action of the BP port 104.
[0027] The technical solution of the present utility model will be further described as follows:
[0028] The power switch 102 (model: for example, DS-13C1A3QN) is used to connect or disconnect the power supply of the clock glitch injector. The communication interface 103 (model: for example, 670689000) is the interface for the clock glitch injector to communicate with the application end (peripheral device). At the same time, the clock glitch injector uses the 5V power supply provided by the communication interface 103 as the power supply and powers on or off through the power switch 102.
[0029] The BP port 104 (model: for example, SMB-KWE) is used to receive the control signal from the peripheral device. The main clock port 105 receives the main clock signal sent by the main clock of the peripheral device. The glitch port 106 is used to receive the glitch signal. The GATE port 107 receives the gating signal. The counter port 108 is used to generate the counting signal.
[0030] Specifically, for the BP port 104, it has two states, as Figure 2 shown, the INJ state and the Normal state. When the control signal of the BP port 104 is in the Normal state, the output port 110 of the control clock glitch injector generates the output clock signal. When the control signal of the BP port 104 is in the INJ state, the output port 110 of the control clock glitch injector generates the output glitch signal. Among them, the state of the BP port 104 is changed according to the operation of the staff.
[0031] For the main clock port 105 (model: for example, SMB-KWE) and the glitch port 106 (model: for example, SMB-KWE), the two signals output by the two ports are independent of each other and can be signals of types such as sine, square wave, and triangular wave. Therefore, the present utility model can arbitrarily add glitches to the clock signal during implementation.
[0032] For the GATE port 107 (model: for example, SMB-KWE), it is used to control the output signal of the output port 110 to be synchronized with the working state of the target integrated circuit to be safely analyzed. Figure 3The signal of the GATE port is shown, which includes two states: the ON state and the OFF state. When the gating signal of the GATE port 107 is in the ON state, the output port 110 has a signal output, and the present invention can be connected to the target integrated circuit; when the gating signal of the GATE port is in the OFF state, the output port 110 is in a high-impedance state, and the clock glitch fault injector of the present invention disconnects the connection with the target integrated circuit.
[0033] The counter port 108 (model: such as SMB-KWE) is used to generate a counting signal, which is convenient for the staff to count the effective number of clock glitch fault injections and is convenient for safety analysis.
[0034] The indicator light 109 is an LED indicator light, which is used to indicate the ongoing and effective clock glitch fault injection and is convenient for safety analysis.
[0035] The first relay 120 (model: such as G6K-2F) is used to switch between different signal paths according to the control signal of the BP port 104. The common terminal C1 is the output, the first switching terminal S1a is connected to the main clock signal, and the second switching terminal S2a is connected to the glitch signal.
[0036] The second relay 130 (model: such as G6K-2F) is used to set the output state of the present invention according to the gating signal of the GATE port 107. The common terminal C2 is the output, the first switching terminal S1b is connected to the common terminal C1 of the first relay 120, and the second switching terminal S2b is in a floating state.
[0037] Through the cooperation of the BP port 104, the main clock port 105, the glitch port 106, and the GATE port 107, the output port 110 can generate a clock signal with arbitrary glitches, which can be used to manipulate the working clock of the integrated circuit and improve the effectiveness of manipulating the working clock for safety analysis.
[0038] Among them, the RF connector with the model of SMB-KWE can be configured by the staff to be ports for different purposes according to actual needs.
[0039] Now, the technical solution of the present invention will be described in combination with the specific implementation process. Figure 4 As shown below:
[0040] When in use, turn on the power switch 102 and connect the communication interface 103 to the test peripheral, and the present fault injector is powered on.
[0041] Start the external main clock signal source and input it to the first switching terminal S1a of the first relay 120 through the main clock port 105; start the external glitch signal source and input it to the first switching terminal S2a of the first relay 120 through the glitch port 106.
[0042] When the control signal of the BP port 104 by the staff is in the Normal state, the first relay 120 connects the first switching end S1a - common end C1 path, and the common end C1 of the first relay 120 outputs the main clock signal; when the control signal of the BP port 104 by the staff is in the INJ state, the first relay 120 connects the second switching end S2a - common end C1 path, and the common end C1 of the first relay 120 outputs the glitch signal. Thus, when the staff continuously switches the state of the BP port 104, the purpose of adding any glitch signal to the clock signal can be achieved through the mutual cooperation of the first switching end S1a, the second switching end S2a, and the switching head S3a.
[0043] When the gating signal of the GATE port 107 is in the ON state, the second relay 130 connects the first switching end S1b - common end C2 path. At this time, the second switching end S2b of the second relay 130 is disconnected, and the common end C2 of the second relay 130 is connected to the output port 110 of the present invention, and the output port 110 generates a clock signal with any glitch; when the gating signal of the GATE port 107 is in the OFF state, the second relay 130 connects the second switching end S2b - common end C2 path, the second switching end S2b is connected to a resistor, and the output port 110 is in a floating state and in a high-impedance state, so that the injector disconnects from the target integrated circuit and no longer affects the target integrated circuit. Further, the state switching of the GATE port 107 is determined by the staff.
[0044] In summary, the present invention realizes generating a clock signal with any glitch in the circuit by switching the circuit connection modes in the two relays, which can be used to manipulate the working clock of the integrated circuit and improve the effectiveness of performing security analysis by manipulating the working clock.
[0045] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A clock glitch fault injector, characterized in that, It includes: a substrate, a main clock port, a glitch port, a first relay, a second relay, a BP port, and a GATE port The main clock port, the glitch port, the BP port, the first relay, the GATE port, the first switching end of the second relay, and the common end of the second relay form a clock glitch fault injection circuit path.
2. The clock glitch fault injector according to claim 1, wherein the BP port is connected to the switching head of the first relay, and the GATE port is connected to the switching head of the second relay; the common end of the first relay is connected in series with the first switching end of the second relay; the main clock port and the glitch port are respectively connected to the first switching end and the second switching end of the first relay.
3. The clock glitch fault injector according to claim 2, characterized in that, The switching head of the first relay connects the first switching end therein to the common end or the second switching end to the common end according to the action of the BP port.
4. The clock glitch fault injector according to claim 2, wherein The second switching end of the second relay is left floating.
5. The clock glitch fault injector according to claim 4, characterized in that, The switching head of the second relay connects the first switch therein to its common end according to the action of the GATE port, or opens the second relay.
6. The clock glitch fault injector according to claim 1, wherein The first relay and the second relay are arranged in the center of the substrate, and the remaining electronic components are arranged around the first relay and the second relay.