Switching circuit capable of adjusting voltage rising and falling time

Abstract

The utility model discloses a switching circuit capable of adjusting voltage rising and falling time, which comprises a capacitor charging circuit, a capacitor discharging circuit and a switching circuit, and is characterized in that the capacitor charging circuit comprises a mirror current source circuit consisting of an NPN type triode Q2, an NPN type triode Q3 and a resistor R5; the capacitor discharge circuit comprises a mirror current source circuit composed of a PNP type triode Q4, a PNP type triode Q5 and a resistor R3. In the circuit, the output voltage delay and rise time of an MOSFET can be adjusted by adjusting the capacitance value of C1 and the resistance value of R5. In the circuit, the output voltage delay and fall time of the MOSFET can be adjusted by adjusting the capacitance value of the C1 and the resistance value of the R3.

Description

Technical Field

[0001] The utility model belongs to the technical field of automotive electronics, and particularly relates to a switching circuit capable of adjusting the voltage rise and fall time. Background Art

[0002] The rapid conduction of the MOSFET tube in the switching circuit causes the output voltage rise time to be short, which is not easy to meet the requirements of the power supply voltage change rate of the subsequent chip. When the output of the MOSFET is a capacitive load, a large inrush current is caused, which is easy to burn out the MOSFET and the circuit. When the capacitance between the G and S poles of the MOSFET is large, the MOSFET turn-off delay is large. Summary of the Utility Model

[0003] The purpose of the utility model is to overcome the disadvantages in the prior art that the output voltage rise time of the switch cannot be adjusted and the inrush current cannot be suppressed, and to overcome the problem that the fall time of the output voltage of the switch cannot be adjusted in the prior art, so as to provide a technology that can adjust the rise and fall time of the output voltage of the switch and effectively suppress the inrush current. The technical solution of the utility model is as follows: the circuit includes a capacitor charging circuit, a capacitor discharging circuit and a switching circuit. The capacitor charging circuit includes a mirror current source circuit composed of an NPN transistor Q2, an NPN transistor Q3 and a resistor R5.

[0004] As an improvement of the utility model, the capacitor discharging circuit includes a mirror current source circuit composed of a PNP transistor Q4, a PNP transistor Q5 and a resistor R3, and a mirror current source circuit composed of Q2, Q3 and R5.

[0005] As an improvement of the utility model, when SW_VCC_EN reaches a high level, after Q1 conducts, Q2, Q3 and R5 start to work. A constant current passes through R5, the base of Q2 and the emitter of Q2, and at the same time, Q3 flows through the same current value as Q2 to form a mirror current source. The collector current of Q3 charges the C1 capacitor. Because the charging current is constant, the voltage across C1 will rise linearly. After the voltage difference between the G and S poles of Q6 reaches the turn-on threshold, Q6 will conduct slowly.

[0006] As an improvement of the utility model, the capacitor discharging circuit is a mirror current source circuit composed of Q4, Q5 and R3. When the network level of SW_VCC_EN is low, Q1 disconnects the circuit composed of Q2, Q3 and R5. A constant current passes through the emitter of Q5, the base of Q5, R3 and then to the ground. At the same time, the emitter and collector of Q4 flow through the mirror current, and Q4 conducts to release the stored charge of C1. The voltage difference between the G and S poles of Q6 gradually drops below the turn-on voltage, and finally Q6 turns off.

[0007] As an improvement of the present utility model, the switching circuit includes a P-type MOSFET Q6 as the switching device of the circuit.

[0008] Compared with the prior art, the beneficial effects of the present utility model are as follows: in the circuit, the output voltage delay and rise time of the MOSFET can be adjusted by adjusting the capacitance value of C1 and the resistance value of R5; in the circuit, the output voltage delay and fall time of the MOSFET can be adjusted by adjusting the capacitance value of C1 and the resistance value of R3. Description of the Drawings

[0009] Figure 1 It is the switching circuit diagram in this embodiment;

[0010] Figure 2 It is the schematic diagram of the circuit capacitor charging and discharging in this embodiment;

[0011] Figure 3 It is the schematic diagram of the circuit charging and discharging in this embodiment;

[0012] Figure 4 It is the waveform diagram of the circuit switching voltage timing in this embodiment;

[0013] Figure 5 It is the circuit structure designed with an N-type MOSFET in this embodiment. Specific Embodiments

[0014] The following further clarifies the present utility model in conjunction with the drawings and specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present utility model and not to limit the scope of the present utility model.

[0015] Embodiment: As Figure 1 shown, the technical solution of the present utility model is as follows: The circuit includes a capacitor charging circuit, a capacitor discharging circuit, and a switching circuit. The capacitor charging circuit includes a mirror current source circuit composed of an NPN-type triode Q2, an NPN-type triode Q3, and a resistor R5.

[0016] Furthermore, the capacitor discharging circuit includes a mirror current source circuit composed of a PNP-type triode Q4, a PNP-type triode Q5, and a resistor R3, and a mirror current source circuit composed of Q2, Q3, and R5.

[0017] Furthermore, when SW_VCC_EN reaches a high level, after Q1 conducts, Q2, Q3, and R5 start to work. A constant current passes through R5, the base of Q2, and the emitter of Q2, and at the same time, Q3 flows through the same current value as Q2 to form a mirror current source. The collector current of Q3 will charge the C1 capacitor ( Figure 2The arrow ① indicates the charging current. Since the charging current is constant, the voltage across C1 will increase linearly. After the voltage difference between the G and S poles of Q6 reaches the turn-on threshold, Q6 will conduct slowly.

[0018] Furthermore, the capacitor discharge circuit consists of a mirror current source circuit formed by Q4, Q5, and R3. When the SW_VCC_EN network level is low, Q1 disconnects the circuit formed by Q2, Q3, and R5. A constant current passes through the emitter, base of Q5, and R3 and then to the ground. At the same time, the emitter and collector of Q4 flow through the mirror current ( Figure 2 The arrow ② indicates the discharge current). When Q4 conducts, the stored charge of C1 is released. The voltage difference between the G and S poles of Q6 gradually drops below the turn-on voltage, and finally Q6 turns off.

[0019] Furthermore, the switch circuit includes a P-type MOSFET Q6 as the switching device of the circuit.

[0020] Furthermore, as Figure 3 the charge-discharge schematic diagram and Figure 4 the voltage switching process timing diagram show, Q2 and Q3 are NPN-type triodes. The resistance value of R5 can set the charging current ① of C1 to adjust the SW_VCC turn-on time T1. Q4 and Q5 are PNP-type triodes. The resistance value of R3 can set the discharge current ② of C1 to adjust the SW_VCC turn-off time T2. The embodiment is described in detail with a P-type MOSFET. If an N-type MOSFET is used for design, the Figure 5 circuit structure can be used.

[0021] It should be noted that the above content only illustrates the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. For those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements all fall within the protection scope of the claims of the present invention.

Claims

1. A switching circuit capable of adjusting the voltage rise and fall times, characterized in that, The circuit includes a capacitor charging circuit, a capacitor discharging circuit, and a switching circuit. The capacitor charging circuit includes a mirror current source circuit composed of an NPN transistor Q2, an NPN transistor Q3, and a resistor R5. The capacitor discharging circuit includes a mirror current source circuit composed of a PNP transistor Q4, a PNP transistor Q5, and a resistor R3. In the capacitor charging circuit, the collector of the NPN transistor Q2 is connected to one end of the resistor R5. The base of the NPN transistor Q2 is connected to the base of the NPN transistor Q3. The emitter of the NPN transistor Q2 is grounded. The collector of the NPN transistor Q3 is connected to the collector of the PNP transistor Q4. The emitter of the NPN transistor Q3 is connected to the collector of the transistor Q1. The base of the PNP transistor Q4 is connected to the base of the PNP transistor Q5. The collector of the PNP transistor Q5 is connected to one end of the resistor R3. The other end of the resistor R3 is connected to the resistor R1. The other end of the resistor R5, the emitter of the PNP transistor Q4, and the emitter of the PNP transistor Q5 are connected together.

2. The switching circuit capable of adjusting the voltage rise and fall time according to claim 1, wherein, In the capacitor charging circuit, when SW_VCC_EN reaches a high level, after Q1 conducts, the NPN transistor Q2, the NPN transistor Q3, and the resistor R5 start to work. A constant current passes through the resistor R5, the base of the NPN transistor Q2, and the emitter of the NPN transistor Q2. At the same time, the NPN transistor Q3 flows through the same current value as the NPN transistor Q2 to form a mirror current source.

3. The switching circuit capable of adjusting the voltage rise and fall time according to claim 2, characterized in that, In the capacitor charging circuit, the collector current of the NPN transistor Q3 charges the C1 capacitor. Because the charging current is constant, the voltage across C1 will increase linearly. When the voltage difference between the G and S poles of the P-type MOSFET Q6 reaches the turn-on threshold, the P-type MOSFET Q6 will slowly conduct.

4. A switching circuit capable of adjusting the voltage rise and fall time according to claim 1, characterized in that When the network level of SW_VCC_EN is low, Q1 disconnects the circuit composed of the NPN transistor Q2, the NPN transistor Q3, and the resistor R5. A constant current passes through the emitter of the PNP transistor Q5, the base of the PNP transistor Q5, and the resistor R3 and then to the ground. At the same time, the emitter and collector of the PNP transistor Q4 flow through the mirror current, and the PNP transistor Q4 conducts to release the stored charge of C1.

5. The switching circuit capable of adjusting the voltage rise and fall time according to claim 4, characterized in that The voltage difference between the G and S poles of the P-type MOSFET Q6 gradually drops below the turn-on voltage, and finally the P-type MOSFET Q6 turns off.

6. The switching circuit capable of adjusting the voltage rise and fall time according to claim 1, wherein, The switching circuit includes a P-type MOSFET Q6 as the switching device of the circuit.

Images