Variable-doping high-reliability planar gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor)

Abstract

The utility model provides a varied doping high-reliability planar gate silicon carbide VDMOS. The varied doping high-reliability planar gate silicon carbide VDMOS is characterized in that a drift layer is connected to a silicon carbide substrate; the first N-type region is connected to the drift layer; the second N-type region is connected to the drift layer; the third N-type region is connected to the drift layer; the outer side surface of the second N-type region is connected to the inner side surface of the first N-type region; the inner side surface of the second N-type region is connected to the outer side surface of the third N-type region; the lower side surface of the P-type well region is connected to the second N-type region, the outer side surface of the P-type well region is connected to the inner side surface of the first N-type region, and the inner side surface of the P-type well region is connected to the outer side surface of the third N-type region; an N-type source region is arranged on the P-type well region; the gate dielectric layer is respectively connected with the P-type well region, the N-type source region and the third N-type region; the source metal layer is respectively connected with the first N-type region, the P-type well region and the N-type source region; the gate metal layer is connected to the gate dielectric layer; the drain metal layer is connected to the lower side surface of the silicon carbide substrate, so that current is uniformly distributed in the device, heat concentration is avoided, and the reliability of the device is improved.

Description

Technical Field

[0001] The utility model relates to a variable-doping high-reliability planar-gate silicon carbide VDMOS. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion.

[0003] In applications such as motor control systems or load switches, when the motor or load is short-circuited, the VDMOS will be directly connected to the bus voltage. Since the VDMOS is in the on state at this time, an instantaneous short-circuit current of hundreds of amperes will be generated, resulting in a very large internal transient temperature rise. Therefore, it is urgent to provide a silicon carbide power VDMOS to ensure that its on-resistance is low enough and the heat is not concentrated. Summary of the Utility Model

[0004] The technical problem to be solved by the utility model is to provide a variable-doping high-reliability planar-gate silicon carbide VDMOS, accurately controlling the lateral layout of the on-resistance of the device, making the current evenly distributed inside the device, avoiding heat concentration, and improving the reliability of the device.

[0005] In a first aspect, the utility model provides a variable-doping high-reliability planar-gate silicon carbide VDMOS, comprising:

[0006] A silicon carbide substrate,

[0007] A drift layer, the lower side of the drift layer being connected to the upper side of the silicon carbide substrate;

[0008] A first N-type region, the lower side of the first N-type region being connected to the upper side of the drift layer;

[0009] A second N-type region, the lower side of the second N-type region being connected to the upper side of the drift layer;

[0010] A third N-type region, the lower side of the third N-type region being connected to the upper side of the drift layer; the outer side of the second N-type region is connected to the inner side of the first N-type region, and the inner side of the second N-type region is connected to the outer side of the third N-type region;

[0011] A P-type well region, the lower side of the P-type well region being connected to the second N-type region, the outer side of the P-type well region being connected to the inner side of the first N-type region, and the inner side of the P-type well region being connected to the outer side of the third N-type region; an N-type source region is provided on the P-type well region;

[0012] A gate dielectric layer, the lower side of the gate dielectric layer being respectively connected to the upper side of the P-type well region, the upper side of the N-type source region, and the upper side of the third N-type region;

[0013] A source metal layer, which is respectively connected to a first N-type region, a P-type well region, and an N-type source region;

[0014] A gate metal layer, which is connected to a gate dielectric layer;

[0015] And a drain metal layer, which is connected to the lower side surface of the silicon carbide substrate.

[0016] The advantages of the present utility model are as follows:

[0017] First, a Schottky diode is constructed inside the device of the present utility model, which can effectively reduce the forward conduction voltage drop of the device, improve the reverse recovery speed of the device, and reduce the conduction loss and switching loss of the device;

[0018] Second, the present utility model constructs a first N-type region, a second N-type region, and a third N-type region with variable doping on the left and right sides and below the P-type well region of the device. The doping concentration relationship of the three regions is the first N-type region > the second N-type region > the third N-type region, realizing relatively uniform lateral distribution of the body resistance from below the gate of the device to the drain, thereby achieving uniform current distribution inside the device, avoiding current concentration and the resulting concentrated heat distribution inside the device, and improving the reliability of the device;

[0019] Third, by setting the third N-type region and the second N-type region, the present utility model can effectively shield the parasitic capacitance from the gate to the drain, that is, can reduce the Miller capacitance of the device and improve the switching speed of the device. Description of the Drawings

[0020] The following further describes the present utility model with reference to the drawings in conjunction with embodiments.

[0021] Figure 1 It is a schematic diagram of a variable-doping high-reliability planar-gate silicon carbide VDMOS of the present utility model.

[0022] Figure 2 It is a process cross-section of a variable-doping high-reliability planar-gate silicon carbide VDMOS of the present utility model Figure 1 。

[0023] Figure 3 It is a process cross-section of a variable-doping high-reliability planar-gate silicon carbide VDMOS of the present utility model Figure 2 。

[0024] Figure 4 It is a process cross-section of a variable-doping high-reliability planar-gate silicon carbide VDMOS of the present utility model Figure 3 。

[0025] Figure 5 It is a process cross-section of a variable-doping high-reliability planar-gate silicon carbide VDMOS of the present utility model Figure 4 。

[0026] Figure 6 Process cross-section of a variable-doping high-reliability planar-gate silicon carbide VDMOS according to the present utility model Figure 5 。

[0027] Figure 7 Process cross-section of a variable-doping high-reliability planar-gate silicon carbide VDMOS according to the present utility model Figure 6 。

[0028] Figure 8 Process cross-section of a variable-doping high-reliability planar-gate silicon carbide VDMOS according to the present utility model Figure 7 。

[0029] Figure 9 Process cross-section of a variable-doping high-reliability planar-gate silicon carbide VDMOS according to the present utility model Figure 8 。

[0030] Figure 10 Process cross-section of a variable-doping high-reliability planar-gate silicon carbide VDMOS according to the present utility model Figure 9 。 Specific embodiments

[0031] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0033] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "in contact with", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0034] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0035] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0036] As Figure 1 shown, an embodiment of the present application provides a variable-doped highly reliable planar-gate silicon carbide VDMOS, including:

[0037] a silicon carbide substrate 101,

[0038] Drift layer 102, the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101;

[0039] First N-type region 103, the lower side of the first N-type region 103 is connected to the upper side of the drift layer 102;

[0040] Second N-type region 104, the lower side of the second N-type region 104 is connected to the upper side of the drift layer 102;

[0041] Third N-type region 105, the lower side of the third N-type region 105 is connected to the upper side of the drift layer 102; the outer side of the second N-type region 104 is connected to the inner side of the first N-type region 103, and the inner side of the second N-type region 104 is connected to the outer side of the third N-type region 105;

[0042] P-type well region 106, the lower side of the P-type well region 106 is connected to the second N-type region 104, the outer side of the P-type well region 106 is connected to the inner side of the first N-type region 103, and the inner side of the P-type well region 106 is connected to the outer side of the third N-type region 105; an N-type source region 1061 is provided on the P-type well region 106;

[0043] Gate dielectric layer 107, the lower side of the gate dielectric layer 107 is respectively connected to the upper side of the P-type well region 106, the upper side of the N-type source region 1061, and the upper side of the third N-type region 105;

[0044] Source metal layer 108, the source metal layer 108 is respectively connected to the first N-type region 103, the P-type well region 106, and the N-type source region 1061;

[0045] Gate metal layer 109, the gate metal layer 109 is connected to the gate dielectric layer 107;

[0046] And a drain metal layer 110, the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101.

[0047] As Figures 1 to 10 shown, the preparation method of the above silicon carbide VDMOS includes the following steps:

[0048] Step 1, deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110; epitaxially grow on the upper side of the silicon carbide substrate 101 to form a drift layer 102;

[0049] Step 2, form a barrier layer 111 above the drift layer 102, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer 102 to form a first N-type region 103, and the ion implantation energy is 10 - 270 kev;

[0050] Step 3: Remove the original barrier layer 111, reform the barrier layer 111, etch the barrier layer 111 to form a through hole, perform ion implantation on the drift layer 102 to form a second N-type region 104, and the ion implantation energy is 170 - 270 kev;

[0051] Step 4: Remove the original barrier layer 111, reform the barrier layer 111, etch the barrier layer 111 to form a through hole, perform ion implantation on the drift layer 102 to form a P-type well region 106, and the ion implantation energy is 10 - 170 kev;

[0052] Step 5: Remove the original barrier layer 111, reform the barrier layer 111, etch the barrier layer 111 to form a through hole, perform ion implantation on the P-type well region 106 to form an N-type source region 1061, and the ion implantation energy is 10 - 70 kev;

[0053] Step 6: Remove the original barrier layer 111, reform the barrier layer 111, etch the barrier layer 111 to form a through hole, perform ion implantation on the drift layer 102 to form a third N-type region 105, and the ion implantation energy is 10 - 270 kev;

[0054] Step 7: Remove the original barrier layer 111, reform the barrier layer 111, etch the barrier layer 111 to form a through hole, and deposit to form a gate dielectric layer 107;

[0055] Step 8: Remove the original barrier layer 111, reform the barrier layer 111, etch the barrier layer 111 to form a through hole, deposit metal to form a gate metal layer 109;

[0056] Step 9: Remove the original barrier layer 111, reform the barrier layer 111, etch the barrier layer 111 to form a through hole, deposit metal to form a source metal layer 108, and remove the barrier layer 111 to complete the preparation.

[0057] Preferably in this embodiment, the doping concentration of the first N-type region 103 is greater than that of the second N-type region 104, the doping concentration of the second N-type region 104 is greater than that of the third N-type region 105; the doping concentration of the drift layer 102 is less than that of the third N-type region 105; the thickness of the first N-type region 103 is equal to that of the third N-type region 105; the thickness of the first N-type region 103 is greater than that of the second N-type region 104.

[0058] The silicon carbide substrate 101 is N-type, and its doping concentration is 2 - 8e18 cm -3 ; the drift layer 102 is N-type, and its doping concentration is 2 - 8e15 cm -3 ; the doping concentration of the first N-type region 103 is 5 - 8e17 cm -3 and the doping concentration of the second N-type region 104 is 1 - 5e17 cm-3 , the doping concentration of the third N-type region 105 is 5 - 8e16 cm -3 , the doping concentration of the P-type well region 106 is 5e17 cm -3 , the gate dielectric layer 107 is silicon dioxide, and the doping concentration of the N-type source region 1061 is 2e18 cm -3 ;

[0059] The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 110, reduce the overall on-resistance of the device. The doping concentration of the N-type drift layer 102 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. The doping concentrations of the first N-type region 103, the second N-type region 104, and the third N-type region 105 and their relationships are to achieve a relatively uniform lateral distribution of the bulk resistance in the device from the drain to the region directly below the device gate, so as to redistribute the electrons from the N-type source region 1061 through the second N-type region 104 below the P-type well region 106, making the current distribution more uniform in the device, thereby reducing the overall on-resistance of the device, avoiding current concentration, and improving the thermal reliability of the device; the doping concentration of the first N-type region 103 is also to form a Schottky contact rather than an ohmic contact with the source metal layer 108 to construct the parasitic Schottky diode of the device, and the doping concentration of the N-type source region 1061 is to form an ohmic contact with the source metal layer 108 and reduce the contact resistance.

[0060] The thickness of the N-type silicon carbide substrate 101 of the device of the present utility model is 1 μm, the thickness of the N-type drift layer 102 is 20 - 40 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the second N-type region 104 is 300 nm, the thickness of the first N-type region 103 is 800 nm, the thickness of the third N-type region 105 is 800 nm, the thickness of the N-type source region 1061 is 200 nm, the thickness of the P-type well region 106 below the N-type source region 1061 is 300 nm, and the thickness in the contact region with the source metal layer 108 is 500 nm; the width of the contact region between the first N-type region 103 and the source metal layer 108 is 300 - 600 nm, which can be designed separately according to the freewheeling ability of the body diode, and the thickness of the insulating dielectric is 50 nm;

[0061] The source metal layer 108 and the first N-type region 103 construct a Schottky diode, which can effectively reduce the forward on-voltage drop of the device, improve the reverse recovery speed of the device, and reduce the conduction loss and switching loss of the device;

[0062] The first N-type region 103, the second N-type region 104, and the third N-type region 105 with variable doping are constructed on the left and right sides and below the P-type well region 106 of the device, so as to achieve relatively uniform lateral distribution of the bulk resistance from below the gate of the device to the drain, thereby realizing uniform current distribution inside the device, avoiding current concentration and the resulting concentrated heat distribution inside the device, and improving the reliability of the device;

[0063] The N-type doping of the second N-type region 104 and the third N-type region 105 can effectively shield the parasitic capacitance from the gate to the drain, that is, it can reduce the Miller capacitance of the device and improve the switching speed of the device.

[0064] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A variable-doped high-reliability planar-gate silicon carbide VDMOS, characterized in that: Comprising: A silicon carbide substrate, A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; A first N-type region, the lower side of which is connected to the upper side of the drift layer; A second N-type region, the lower side of which is connected to the upper side of the drift layer; A third N-type region, the lower side of which is connected to the upper side of the drift layer; the outer side of the second N-type region is connected to the inner side of the first N-type region, and the inner side of the second N-type region is connected to the outer side of the third N-type region; A P-type well region, the lower side of which is connected to the second N-type region, the outer side of which is connected to the inner side of the first N-type region, and the inner side of which is connected to the outer side of the third N-type region; an N-type source region is provided on the P-type well region; A gate dielectric layer, the lower side of which is respectively connected to the upper side of the P-type well region, the upper side of the N-type source region, and the upper side of the third N-type region; A source metal layer, which is respectively connected to the first N-type region, the P-type well region, and the N-type source region; A gate metal layer, which is connected to the gate dielectric layer; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

2. The variable-doped high-reliability planar-gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the first N-type region is greater than that of the second N-type region, and the doping concentration of the second N-type region is greater than that of the third N-type region.

3. The variable-doping highly reliable planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the drift layer is less than that of the third N-type region.

4. A variable-doping high-reliability planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the first N-type region is equal to that of the third N-type region; the thickness of the first N-type region is greater than that of the second N-type region.

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