Semiconductor stack structure

Abstract

The utility model provides a semiconductor stacking structure comprising a first tube core and a second tube core jointed with the first tube core. The first die has a first region and a second region surrounded by the first region. The first die includes a first metallization structure having a first sealing ring structure and a first bonding structure having a first dummy pad over the first sealing ring structure. The second die includes a second metallization structure having a second sealing ring structure and a second bonding structure having a second dummy pad over the second sealing ring structure. The first die and the second die are bonded by the bonding of the first bonding structure and the second bonding structure. The first seal ring structure and the second seal ring structure are substantially aligned in a vertical direction, and the first dummy pads are respectively engaged with the second dummy pads.

Description

Technical Field

[0001] Embodiments of the present utility model relate to a semiconductor stacked structure. Background Art

[0002] Packaging technology involves packaging and combining different types of stacked semiconductor dies having integrated circuits (ICs) and electronic devices. Durable integration through reliable electrical interconnection between the semiconductor die and other devices is important for packaging. Summary of the Utility Model

[0003] Embodiments of the present utility model provide a semiconductor stacked structure, which includes a first die and a second die stacked on and bonded to the first die. The first die has a first region and a second region surrounded by the first region. The first die includes a first metallization structure embedded in a first insulating material and a first bonding structure located above the first insulating material and the first metallization structure. In the first region, the first metallization structure includes a first seal ring structure, and the first bonding structure includes a first dummy pad located above the first seal ring structure. The second die includes a second metallization structure embedded in a second insulating material and a second bonding structure located above the second insulating material and the second metallization structure. The second metallization structure includes a second seal ring structure, and the second bonding structure includes a second dummy pad located above the second seal ring structure. The first die and the second die are bonded by the bonding of the first bonding structure and the second bonding structure. The first seal ring structure and the second seal ring structure are generally aligned in the vertical direction, and the first dummy pads are respectively bonded to the second dummy pads.

[0004] An embodiment of the present utility model provides a semiconductor stack structure. The stack structure includes a first die, a second die stacked on and bonded to the first die, and a filling material located above the first die. The first die has a first region and a second region surrounded by the first region. The first die includes a first metallization structure embedded in a first insulating material and a first bonding structure located above the first insulating material and the first metallization structure. In the first region, the first metallization structure includes a first seal ring structure, and the first bonding structure includes a first dummy pad located above the first seal ring structure. The second die includes a second metallization structure embedded in a second insulating material and a second bonding structure located above the second insulating material and the second metallization structure. The second metallization structure includes a second seal ring structure, and the second bonding structure includes a second dummy pad located above the second seal ring structure. The filling material is disposed on the first die and around the second die. The second bonding structure is bonded to the first bonding structure, the second seal ring structure is partially aligned with the first seal ring structure, and the second dummy pads are respectively bonded to the first dummy pads in the first region.

[0005] To make the above features and advantages of the present utility model more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic top view of an exemplary packaged component having multiple semiconductor dies in accordance with some embodiments of the present disclosure.

[0008] Figures 2 to 9 is a schematic cross-sectional view and top view showing the various stages of a manufacturing method for forming a semiconductor stack structure in accordance with some embodiments of the present disclosure.

[0009] Figure 10 、 Figure 11 and Figure 12 show cross-sectional views of an exemplary stack structure in accordance with some embodiments of the present disclosure.

[0010] Figure 13 、 Figure 14 and Figure 15 show schematic cross-sectional views of some portions of an exemplary stack structure in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a second feature on or over a first feature may include embodiments in which the second feature and the first feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the second feature and the first feature such that the second feature and the first feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "on", "above", "upper", and similar terms may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0013] It should be understood that the following embodiments of the present disclosure provide applicable concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative and relate to three-dimensional (3D) integrated structures or assemblies and do not limit the scope of the present disclosure. Embodiments of the present disclosure illustrate exemplary manufacturing processes for 3D stacked structures and 3D stacked structures fabricated by the exemplary manufacturing processes. Some embodiments of the present disclosure relate to 3D stacked structures formed from wafer bonding structures and stacked wafers and / or dies. Other embodiments relate to 3D integrated structures or assemblies including post-passivation interconnect (PPI) structures or interposers having other electrical connection components, including wafer-to-wafer assembly structures, die-to-wafer assembly structures, package-on-package (POP) assembly structures, die-to-die assembly structures, and die-to-substrate assembly structures. The wafers or dies may include one or more types of integrated circuits or electronic devices located on a bulk semiconductor substrate or a silicon / germanium-on-insulator substrate. These embodiments are intended to provide further illustration but do not limit the scope of the present disclosure.

[0014] Figure 1 is a schematic top view of an exemplary packaged component having multiple semiconductor die in accordance with some embodiments of the present disclosure.

[0015] In Figure 1 , a packaged component is provided, and the packaged component can be used to form a stacked structure or a packaged structure in a packaging process. In some embodiments, the packaged component is wafer 100, and multiple semiconductor die 10D are defined or formed within wafer 100. In some embodiments, wafer 100 is a semiconductor bulk wafer in which active devices are formed and passive devices are formed as needed. In some embodiments, wafer 100 can be a reconstructed wafer. As Figure 1 shown, the dashed line indicates dicing lane DL, and wafer 100 will be diced along dicing lane DL in a subsequent singulation process to obtain semiconductor die 10D separated from each other by the singulation process. In some embodiments, semiconductor die 10D have the same design and perform the same function. In some embodiments, the semiconductor die of wafer 100 have different designs and perform different functions.

[0016] Figures 2 to 9 is a schematic cross-sectional view and a top view showing the various stages of a manufacturing method for forming a semiconductor stacked structure in accordance with some embodiments of the present disclosure. The same reference numerals can be used in the figures to label the same devices or components having similar or identical structural configurations.

[0017] Figure 2 is a schematic cross-sectional view showing an intermediate stage of a manufacturing method for forming a semiconductor stacked structure in accordance with some embodiments of the present disclosure. Figure 3 shows a schematic top view of an exemplary arrangement of a first bonding structure relative to the underlying component. In Figure 2Among them, in some embodiments, a wafer 100 is provided, and the wafer 100 is similar to the wafer 100 described in the previous paragraphs. In some embodiments, the wafer 100 is a semiconductor wafer, and the wafer 100 includes a semiconductor substrate 102 having a device layer 103, a metallization structure 104 formed on the semiconductor substrate 102 and the device layer 103, and a first bonding structure 106 formed on the metallization structure 104 and above the semiconductor substrate 102. In some embodiments, the wafer 100 is a silicon wafer or a bulk wafer made of other semiconductor materials such as III-V semiconductor materials (e.g., gallium nitride (GaN) or gallium arsenide (GaAs)). In some embodiments, the substrate 102 can be a single-crystal semiconductor substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon-germanium on insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In certain embodiments, the device layer 103 includes semiconductor devices formed in or on the semiconductor substrate 102 of the wafer 100 during the front-end-of-line (FEOL). In certain embodiments, the semiconductor device is or includes a transistor, a memory, or a power device, or other devices such as a capacitor, a resistor, a diode, a photodiode, a sensor, an inductor, or a fuse. In an exemplary embodiment, some of the semiconductor devices in the semiconductor device can be electrically connected to the metallization structure 104.

[0018] In some embodiments, before dicing or singulating, the wafer 100 can be regarded as having a plurality of semiconductor dies 10D. In Figure 2 Among them, the position of the dicing lane DL shows a part of the wafer 100 including at least two die units. In some embodiments, each die unit includes a first region R1 and a second region R2. In some embodiments, the second region R2 is or includes a main region where devices are formed, and the first region R1 is or includes a peripheral region where no active or passive devices are formed. In one embodiment, the first region R1 surrounds the second region R2. In one embodiment, the first region R1 includes structural features or components but does not have electro-functional components. It should be understood that the number of the semiconductor dies 10D is only exemplary, and the semiconductor dies 10D can include dies of the same type or dies with the same function.

[0019] As Figure 2As shown, in some embodiments, the metallization structure 104 is embedded in the insulating material 105 formed on the semiconductor substrate 102. In some embodiments, the metallization structure 104 includes multiple metallization layers of inline structure (including interconnected metal lines, vias, and contact pads) (detailed configurations and interlayers are omitted and represented by ellipsis). In some embodiments, in the second region R2, the metallization structure 104 includes a contact pad 1042 formed on the top metal line 1044, a bottom metal line 1046 electrically connected to the device layer 103, and a through-semiconductor via (TSV) 1048 connected to the bottom metal line 1046. In an exemplary embodiment, the semiconductor devices in the device layer 103 are electrically connected to the bottom metal line 1046 and the metallization structure 104, and some of the semiconductor devices in the semiconductor devices can be electrically interconnected via the bottom metal line 1046 and the metallization structure 104. In some embodiments, the metallization structure 104 electrically connects the semiconductor devices of the device layer 103 to the above first bonding structure 106.

[0020] In some embodiments, in the first region R1, the metallization structure 104 includes a stacked seal ring structure 1043. In some embodiments, the stacked seal ring structure 1043 is electrically floating, but it can be stacked on top of each other and connected to each other. In some embodiments, the seal ring structure 1043 serves as a structural component to strengthen the structural strength and stiffness of the die unit in a later dicing process or singulation process. As Figure 2 shown, the seal ring structure 1043 is located beside and near the dicing lane DL.

[0021] As Figure 2 and Figure 3 shown, in some embodiments, the first bonding structure 106 is formed on the insulating material 105 and the metallization structure 104. In an exemplary embodiment, the first bonding structure 106 includes an interface bonding structure, and the first bonding structure 106 includes a dielectric material 1061, bonding pads embedded in the dielectric material 1061, dummy bonding pads 1064, and dummy pads 1066. In some embodiments, the bonding pads 1062, dummy bonding pads 1064, and dummy pads 1066 that penetrate the dielectric material 1061 are exposed for contacting other metallic bonding pads, which serves as a metal-to-metal bonding. In some embodiments, the dielectric material 1061 of the first bonding structure 106 can contact other dielectric materials and serves as a dielectric-to-dielectric bonding. In an exemplary embodiment, the first bonding structure 106 serves as a hybrid bonding structure.

[0022] Referring to Figure 2 andFigure 3 , in some embodiments, the first bonding structure 106 includes dummy pads 1066 that assist in interface bonding but do not have electrical functions, and the dummy pads 1066 are arranged in the first region R1 and are located above the sealing ring structure 1043. Taking a quadrilateral die unit or a rectangular die unit as an example, the dicing streets DL are defined by the four sides of the die unit, and the sealing ring structure 1043 can be formed to have a continuous annular structure or be formed into multiple segments, and are arranged in a ring shape along and by the dicing streets DL (represented by the double dashed lines in Figure 3 ), and some dummy pads 1066 are arranged along the annular structure of the sealing ring structure 1043. In some embodiments, some dummy pads 1066 are located directly above the sealing ring structure 1043. In some embodiments, within the second region R2, the first bonding structure 106 also includes bonding pads 1062 that are electrically connected to the underlying metallization structure 104 or to other bonding pads of another die or packaging component, and dummy bonding pads 1064 that assist in interface bonding but do not have electrical functions. That is, the dummy pads 1066 in the first region R1 and the dummy bonding pads 1064 in the second region R2 are neither part of the electrical signal path nor part of the power path of the die or the stacked structure. In some embodiments, some bonding pads 1062 are electrically connected to the contact pads 1042 or the top metal lines 1044 through vias 1045.

[0023] In certain embodiments, the material of the metallization structure 104 includes aluminum (Al), aluminum alloy, copper (Cu), copper alloy, titanium (Ti), nickel (Ni), tungsten (W), or a combination thereof. The metallization structure 104 shown herein is for illustrative purposes only, and the metallization structure 104 may include other configurations and may include one or more vias and / or damascene structures. In some embodiments, the contact pads 1042 include aluminum pads, and the sealing ring 1043 is formed by the same process as the bottom metal lines 1046, the top metal lines 1044, the vias 1045, and the metallic material layer formed between the metal lines 1046, the top metal lines 1044, and the vias 1045 and is made of the same metal material as the bottom metal lines 1046, the top metal lines 1044, the vias 1045, and the metallic material layer formed between the metal lines 1046, the top metal lines 1044, and the vias 1045. In some embodiments, the insulating material 105 includes one or more low dielectric constant (low-k) dielectric layers. In some embodiments, the insulating material 105 includes silicon oxide, spin-on dielectric material, low dielectric constant dielectric material, or a combination thereof.

[0024] As Figure 2As shown, in some embodiments, within the second region R2, the metallization structure 104 includes contact pads 1042 formed over the top metal lines 1044, and the contact pads 1042 are, for example, input / output (I / O) pads or aluminum pads. In an exemplary embodiment, no contact pads are formed above the seal ring structure 1043 in the first region R1, and only dummy pads 1066 are formed above the seal ring structure 1043. That is, within the first region R1, there is a padless or aluminum-padless region DB1 of the insulating material 105 directly above the seal ring structure 1043, and the padless or aluminum-padless region DB1 is sandwiched between the dummy pads 1066 and the top of the seal ring structure 1043. In some embodiments, such a padless region DB1 of the insulating material 105 is regarded as a metal-free dielectric buffer block, which helps isolate the contact pads in the second regions of different die units. Since such a metal-free dielectric block is located next to and on opposite sides of the dicing lane DL, better buffering and less stress are provided, and thus rupture or splitting of the dielectric film above the seal ring structure 1043 in the peripheral region of the die unit is avoided. In addition, the arrangement of the dummy pads 1066 in the first region R1 (above the seal ring structure 1043) helps with the uniform layout of the pads and improves the consistency of the bonding interface, thereby resulting in better bonding reliability.

[0025] In some embodiments, the bonding pads 1062, the dummy bonding pads 1064, and the dummy pads 1066 are formed by the same process and made of the same metallic material. For example, the metallic material includes copper, copper alloy, titanium (Ti), titanium nitride, nickel (Ni), or a combination thereof. In some embodiments, the dielectric material 1061 includes one or more oxide dielectric layers. In some embodiments, the dielectric material 1061 includes silicon oxide, silicon nitride, spin-on dielectric materials such as undoped silicate glass materials, low dielectric constant dielectric materials, or a combination thereof. In some embodiments, the dielectric material 1061 includes silicon oxide formed by chemical vapor deposition (CVD) using tetraethoxysilane (TEOS).

[0026] Figure 4 is a schematic cross-sectional view showing an intermediate stage of a manufacturing method for forming a semiconductor stacked structure according to some embodiments of the present disclosure. Figure 5 A schematic top view showing an exemplary arrangement of the bonding structure relative to the underlying components. Referring to Figure 4 , in some embodiments, a second die 200 (only one is shown) and a third die 300 (only one is shown) are provided, and the second die 200 and the third die 300 are stacked on the wafer 100. For example, as Figure 5As shown, a plurality of second dies 200 and a plurality of third dies 300 are arranged side by side on the top surface of the wafer 100. In some embodiments, depending on the product design, at least one second die 200 and at least one third die are included in one packaging unit.

[0027] In certain embodiments, each second die 200 includes a second semiconductor substrate 202, a second metallization structure 204 embedded in an insulating material 205 formed on the second semiconductor substrate 202, and a second bonding structure 206 formed on the second metallization structure 204 (in Figure 4 it, when the second die 200 is face - down, includes the above - mentioned structures from top to bottom). In an embodiment, each second die 200 includes semiconductor devices 201 and isolation structures (not shown) formed in the semiconductor substrate 202. In certain embodiments, the second metallization structure 204 includes a stacked sealing ring 2043, semiconductor vias 2048, and interconnected metal lines and vias (detailed configurations and interlayers are omitted and represented by ellipses). In some embodiments, the second bonding structure 206 includes a dielectric material 2061, bonding pads 2062 electrically connected to the second metallization structure 204 and semiconductor devices 201, and dummy bonding pads 2066 that are electrically floating and not electrically connected to the semiconductor devices 201.

[0028] In some embodiments, the second die 200 is made of a semiconductor wafer configured similar to the die unit of the wafer 100. In some embodiments, the second die 200 includes a main region in which semiconductor devices 201 and aluminum pads 2042 are formed. In some embodiments, the second die 200 includes a peripheral region in which no active or passive devices are formed but has a stacked sealing ring 2043 and dummy pads 2066 formed directly below the stacked sealing ring 2043. Additionally, in Figure 4 it, there is a pad - free or aluminum - pad - free region DB2 directly below the sealing ring 2043 (in Figure 4 it, the second die 200 is face - down), and the pad - free or aluminum - pad - free region DB2 is sandwiched between the dummy pad 2066 and the top of the sealing ring 2043. Similarly, when the stacked sealing ring 2043 is formed in a ring shape, the pad - free region DB2 can be in a ring shape. In some embodiments, such a pad - free region DB2 of the insulating material 205 is regarded as a metal - free dielectric buffer block.

[0029] In certain embodiments, each third die 300 includes a third semiconductor substrate 302, a third metallization structure 304 embedded in an insulating material 305 formed on the third semiconductor substrate 302, and a third bonding structure 306 formed on the third metallization structure 304 (in Figure 4In [the figure], when the third die 300 faces downward, it includes the above structures from top to bottom). In an embodiment, each third die 300 includes a semiconductor device 301 and an isolation structure (not shown) formed in a semiconductor substrate 302. In certain embodiments, the third metallization structure 304 includes a stacked sealing ring 3043, semiconductor vias 3048, and interconnected metal lines and vias (detailed configurations and interlayers are omitted and represented by ellipses). In some embodiments, the third bonding structure 306 includes a dielectric material 3061, bonding pads 3062 electrically connected to the third metallization structure 304 and the semiconductor device 301, and electrically floating dummy bonding pads 3066.

[0030] In some embodiments, the third die 300 is fabricated from a semiconductor wafer configured and designed to be similar to the die units of the wafer 100. In some embodiments, the third die 300 includes a main region in which a semiconductor device 301 and aluminum pads 3042 are formed. In some embodiments, the third die 300 includes a peripheral region in which no active or passive devices are formed but which has a stacked sealing ring 3043 and dummy pads 3066 formed directly below the stacked sealing ring 3043 (in Figure 4 [the figure], the third die 300 faces upward). Additionally, there is a padless or aluminum-padless region DB3 directly below the sealing ring 3043, and the padless or aluminum-padless region DB3 is sandwiched between the dummy pad 3066 and the top of the sealing ring 3043. Similarly, when the stacked sealing ring 3043 is formed in a ring shape, the padless region DB3 can be in a ring shape. In some embodiments, such a padless region DB3 of the insulating material 305 is regarded as a metal-free dielectric buffer block.

[0031] In certain embodiments, the material of the second metallization structure 204 or the third metallization structure 304 can be similar to or the same as the material of the first metallization structure 104. In certain embodiments, the dielectric material and the material of the pads of the second bonding structure 206 or the third bonding structure 306 can be similar to or the same as the dielectric material and the material of the pads of the first bonding structure 106.

[0032] During the placement of the second die 200 and the third die 300, the second die 200 and the third die 300 are arranged to align the second bonding structure 206 and the third bonding structure 306 with the corresponding first bonding structure 106 respectively, such that the bonding pads and the dummy pads of each die are generally vertically aligned (along the thickness direction) with the bonding pads and the dummy pads of the wafer 100. In some embodiments, once the second die 200 and the third die 300 are placed on the wafer 100, the second bonding structure 206 and the third bonding structure 306 directly contact the corresponding first bonding structure 106.

[0033] Then, in some embodiments, as Figure 4 shown, a bonding process is performed to bond the first bonding structure 106, the second bonding structure 206, and the third bonding structure 306 to each other, thereby bonding the second die 200 and the third die 300 to the die unit (semiconductor die 10D) of the wafer 100. In some embodiments, the bonding process is or includes a hybrid bonding process. In one embodiment, during the application of the hybrid bonding technique, a low-temperature heating process is performed at a temperature of about 100 degrees Celsius to about 200 degrees Celsius to heat and bond the dielectric materials 1061, 2061, 3061 (dielectric-to-dielectric bonding), and a high-temperature heating process is performed at a temperature of about 200 degrees Celsius to about 300 degrees Celsius to bond the metallic pads 1062, 1064, 1066, 2062, 2066, 3062, 3066 (metal-to-metal bonding). In some embodiments, the second die 200 and the third die 300 are bonded to the wafer 100 by hybrid interface bonding to form a die-stacked-on-wafer structure.

[0034] Referring to Figure 4 and Figure 5 , after stacking the second die 200 and the third die 300 on the wafer 100, the second bonding structure 206 and the third bonding structure 306 are aligned with and bonded to the first bonding structure 106. There is a hybrid bonding interface between the first bonding structure 106 and the second bonding structure 206 and the third bonding structure 306. In some embodiments, the dummy pads 2066 of the second bonding structure 206 and the dummy pads 3066 of the third bonding structure 306 are aligned with and bonded to the dummy pads 1066 of the first bonding structure 106 by alignment. In some embodiments, the bonding pads 2062 of the second bonding structure 206 and the bonding pads 3062 of the third bonding structure 306 are aligned with and bonded to the bonding pads 1062 of the first bonding structure 106 by alignment. The second die 200 and the third die 300 are electrically connected to the underlying die unit (or semiconductor die 10D) of the wafer 100 via the bonding pads 1062, 2062, 3062.

[0035] As Figure 4As shown, after bonding, the stacked sealing ring 2043 within the first region R1 is generally vertically aligned (i.e., the positions partially overlap) with the underlying sealing ring structure 1043, and the non-pad region DB2 within the first region R1 is generally vertically aligned with the non-pad region DB1. After bonding, the bonded dummy pads 1066 and 2066 and the aligned non-pad regions DB1 and DB2 are located beside and near the scribe line DL. Additionally, the stacked sealing ring 3043 within the first region R1 is generally vertically aligned with the underlying sealing ring structure 1043, and after bonding, the non-pad region DB3 within the first region R1 is generally vertically aligned with the non-pad region DB1. In some embodiments, after bonding, the bonded dummy pads 1066, 3066 and the aligned non-pad regions DB1 and DB3 are located beside and near the scribe line DL. Due to the presence of the buffer dielectric blocks in the metal-free regions DB1, DB2 and DB3 near the scribe line DL, better interface bonding is established via the bonded dummy pads 1066, 2066 and 3066 and there is little occurrence of cracking or delamination.

[0036] In some embodiments, as Figure 4 and Figure 5 shown, the area / size of the second die 200 or the third die 300 is less than the area / size of one die unit of the wafer 100 (which is diced into semiconductor dies 10D), and the area / size of the second die 200 is greater than the area / size of the third die 300. It should be understood that the number of the second die 200 or the third die 300 is merely exemplary. In some embodiments, the second die 200 and the third die are dies of a different type from the semiconductor die 10D. In some embodiments, the second die 200 or the third die 300 may be a die of the same type as the semiconductor die 10D but having an area or pitch different from the area or pitch of the semiconductor die 10D. In some embodiments, due to the size difference, some of the dummy pads 1066 and some of the dummy bonding pads 1064 are exposed and not covered by the mounted second die 200 or third die 300.

[0037] In some embodiments, the semiconductor die 10D, the second die 200, and the third die 300 have different functions. In some embodiments, the semiconductor die 10D has the same function as the second die 200 or the third die 300, but has a different size. In some embodiments, the semiconductor die 10D includes a logic die, such as a central processing unit (CPU) die, a graphic processing unit (GPU) die, a micro control unit (MCU) die, a baseband (BB) die, or an application processor (AP) die. In some embodiments, the third die 300 includes a memory die, such as a high bandwidth memory (HBM) die, a dynamic random access memory (DRAM) die, or a static random access memory (SRAM) die. In some embodiments, the second die 200 includes an application-specific integrated circuit (ASIC) die, an analog die, a sensor die, a wireless application die (including a Bluetooth chip and / or a radio frequency chip), or a voltage regulator die.

[0038] Figures 6 to 9 is a schematic cross-sectional view showing various stages of a manufacturing method for forming a semiconductor stack structure according to some embodiments of the present disclosure. Next, refer to Figure 4 and Figure 6, a filling material 220 is formed on top of the die structures stacked on the wafer. The filling material 220 particularly fills the gap between the second die 200 and the third die 300 on the wafer 100 to form a molded structure 230. In one embodiment, the molded structure 230 is a reconstructed wafer structure. In some embodiments, the filling material 220 is an insulating material. In one embodiment, the filling material 220 is formed by chemical vapor deposition (CVD), spin coating, or molding. In some embodiments, the filling material 220 completely covers the second die 200 and the third die 300 bonded to the wafer 100. In some embodiments, the filling material 220 covers the top surface of the wafer 100, fills the gap between the second die 200 and the third die 300, and covers the top surfaces and sidewalls of the second die 200 and the third die 300. In addition, the filling material 220 covers the uncovered bonding structure 106 on the wafer 100, and covers the exposed dummy pads 1066 and dummy bonding pads 1064. In some embodiments, the pads are not arranged symmetrically with respect to the bonding interface, and some of the dummy pads and / or some of the dummy bonding pads are in direct contact with the filling material. As Figure 6 shown, the thickness of the filling material 220 is large enough to be higher than the top of the second die 200 or the third die 300. In some embodiments, the material of the filling material 220 includes silicon oxide, silicon nitride, epoxy resin, phenolic resin, or silicone resin.

[0039] In some embodiments, referring to Figure 7 , a planarization process is performed to partially remove the filling material 220 and parts of the second die 200 and the third die 300, thereby forming a planarized molded structure 232. For example, the planarization process includes performing a grinding process or a polishing process, such as a chemical mechanical polishing process. After planarization, the back sides of the second die 200 and the third die are polished until the TSVs 2048 and 3048 are exposed. In some embodiments, the planarized filling material 220 laterally covers at least the sidewalls of the second die 200 and the third die 300 mounted on the wafer 100. In some embodiments, as Figure 7As shown, the top surface 220T of the planarized fill material 220 is flush and coplanar with the backside 200B of the second die 200 and the backside 300B of the third die 300. Since the fill material 220 is directly formed on the exposed bonding structure 106 of the wafer 100, there is a dielectric-to-dielectric bond between the exposed dielectric material 1061 and the fill material 220. In one embodiment, the dummy pads 1066 and the dummy bonding pads 1064 located below the fill material 220 are electrically floating pads. In some embodiments, these floating pads are not electrically connected to any semiconductor device and can assist in heat dissipation.

[0040] Referring Figure 8 , in some embodiments, a redistribution layer (RDL) 240 is formed over the planarized molding structure 232 and on the planarized fill material 220 and on the second die 200 and the third die 300. The redistribution layer (RDL) 240 is electrically connected to the second die 200 and the third die 300 at least via the TSVs 2048 and 3048 of the second die 200 and the third die 300. In some embodiments, the RDL 240 includes a redistribution metal pattern 242 embedded in a dielectric material layer 241. The configuration of the redistribution metal pattern is not limited by this disclosure, and the dielectric material layer may include more than one layer of dielectric material. For example, the redistribution metal pattern 242 includes a wiring metal pattern, vias, and metal pads. In certain embodiments, the dielectric material layer 241 exposes some of the underlying redistribution metal pattern 242 of the underlying redistribution metal pattern 242, and conductive terminals 250 are formed on the exposed metal pattern 242. In some embodiments, the conductive terminals 250 include metal posts 251 and bumps 252. In some embodiments, the material of the dielectric material layer 241 includes silicon oxide, silicon nitride, low-k dielectric material, benzocyclobutene (BCB), epoxy resin, polyimide (PI), or polybenzoxazole (PBO). In some embodiments, the material of the metal posts 251 includes copper or a copper alloy, and the material of the bumps 252 includes solder. In one embodiment, the metal posts 251 and the bumps 252 located on the metal posts 251 constitute micro-bumps. In some embodiments, the conductive terminals 250 include copper pillar bumps.

[0041] Later, in some embodiments, referring Figure 8 and Figure 9, a singulation process is performed to cut the planarized molded structure 232 into individual three-dimensional (3D) stacked structures 30 along the dicing lanes DL. In an exemplary embodiment, referring to the exemplary arrangement shown in Figure 5 wherein at least one second die 200 and at least one third die are included within one package unit, after singulation, each of the singulated 3D stacked structures 30 includes at least one second die 200 and at least one third die 300 stacked on the semiconductor die 10D, and a filler material 220 surrounding the second die 200 and the third die 300. In some embodiments, the singulation process includes a wafer dicing process or a sawing process. Due to the layout arrangement, as viewed from the cross-sectional view shown in Figure 9 , one of the two 3D stacked structures 30 is shown to include the second die 200, while the other 3D stacked structure 30 is shown to include the third die 300; however, it should be understood that each stacked structure (package unit) includes at least one second die 200 and one third die 300.

[0042] In some embodiments, electrical connection paths are established between the semiconductor dies 10D, 200, and 300 of the stacked structure 30 via the metallization structures 104, 204, 304 and the hybrid bonding structures 106, 206, 306. On the other hand, the seal ring structures 1043, 2043, 3043 and the bonded dummy pads 1066, 2066, 3066 are electrically floating and are not part of the electrical connection paths.

[0043] Although the steps of the method are shown and described as a series of acts or events, it should be understood that the shown order of such acts or events should not be construed in a limiting sense. Additionally, one or more embodiments of the present disclosure do not require all of the shown processes or steps. Furthermore, the shown processes are chip-on-wafer (CoW) processes and can also be used to fabricate 3D stacked packages or chip-on-wafer-on-substrate (CoWoS) packages.

[0044] Figure 10 A cross-sectional view showing an exemplary 3D stacked structure according to some embodiments of the present disclosure. In Figure 10In [the figure], the 3D stacked structure 30A includes at least a first die 12, a second die 14 and a third die 16 disposed on the first die 12, and a filling material 17 filled between the second die 14 and the third die 16, surrounding the second die 14 and the third die 16, and disposed on the first die 12. In some embodiments, except for not having TSVs, the first die 12 is similar to the semiconductor die 10D described in the previous paragraph, and the second die 14 and the third die 16 are similar to the second die 200 and the third die 300 described in the previous paragraph. Herein, the same reference numerals may be used to label the same or similar structural features or components.

[0045] As Figure 10 shown, the first die 12 includes a first bonding structure 106 and a first metallization structure 104. The first bonding structure 106 has dummy pads 1066 in the peripheral region. The first metallization structure 104 has a seal ring structure 1043 directly above the dummy pads 1066. Inside the first die 12, there is a metal-free or metal-free pad region DB1 of the insulating material 105 sandwiched between the dummy pads 1066 and the seal ring structure 1043. In some embodiments, the second die 14 includes a second bonding structure 206 and a second metallization structure 204. The second bonding structure 206 has dummy pads 2066 in the peripheral region. The second metallization structure 204 has a stacked seal ring 2043 directly below the dummy pads 2066. And there is a metal-free or metal-free pad region DB2 of the insulating material 205 directly above the seal ring 2043. The metal-free or metal-free pad region DB2 of the insulating material 205 is sandwiched between the dummy pads 2066 and the top of the seal ring 2043. In some embodiments, the third die 16 also includes a third bonding structure 306 and a third metallization structure 304. The third bonding structure 306 has dummy pads 3066 formed in the peripheral region. The third metallization structure 304 has a stacked seal ring 3043 directly below the dummy pads 3066. In addition, there is a metal-free or metal-free pad region DB3 of the insulating material 305 directly above the seal ring 3043. The metal-free or metal-free pad region DB3 of the insulating material 305 is sandwiched between the dummy pads 3066 and the top of the seal ring 3043. In some embodiments, for the 3D stacked structure 30A, the metal-free pad regions DB1, DB2, DB3 that are generally vertically aligned around the peripheral region of the stacked structure 30A can be used as metal-free dielectric blocks, which can reduce cracking or delamination at the edges of the stacked structure 30A (or the packaging unit) and improve the production yield. In some embodiments, the bonded dummy pads 1066, 2066, 3066 together with the surrounding seal ring structures 1043, 2043, 3043 can improve the bonding strength and the reliability of the stacked structure 30A.

[0046] In some embodiments, the third die 16 and the second die 14 are stacked face-to-face with the first die 12, and the third bonding structure 306 of the third die 16 and the second bonding structure 206 of the second die 14 contact and are directly connected to the first bonding structure 106 of the first die 12. That is, the first die 12 is hybrid bonded with the second die 14 and the third die 16, and there is a hybrid bonding interface between the first die 12 and the second die 14 and the third die 16. In some embodiments, the second die 14 and the third die 16 are electrically connected to the first die 12 via the metallization structures 104, 204, 304 and the bonding structures 106, 206, 306. In some embodiments, the filler material 17 sandwiched between the second die 14 and the third die 16 covers the exposed dummy bonding pads 1064 and the dummy pads 1066.

[0047] In certain embodiments, as Figure 10 shown, the 3D stacked structure 30A further includes a redistribution layer (RDL) 18 disposed on the second die 14, the third die 16, and the filler material 17, and conductive terminals 20 located on the RDL 18. For example, the conductive terminals 20 can be electrically connected to the second die 14 and the third die 16 via the RDL 18 of the second die 14 and the third die 16 and the TSVs 2048 and 3048.

[0048] Figure 11 and Figure 12 FIG. shows a cross-sectional view of an exemplary 3D stacked structure according to some embodiments of the present disclosure. According to an embodiment, the same or similar components may be labeled with the same reference numerals, and for the sake of brevity, the details and descriptions of the same or similar components will not be repeated herein.

[0049] In Figure 11 , the 3D stacked structure 40 includes at least a first die 12A and a second die 12B located on the first die 12A. In some embodiments, the first die 12A and the second die 12B perform different functions but have substantially the same size. In some embodiments, the first die 12A and the second die 12B perform substantially the same or similar functions and have substantially the same size. For example, the first die 12A and / or the second die 12B may be similar to the semiconductor die 10D described in the previous paragraph, but it should be understood that certain structural features may have different configurations or modifications.

[0050] In some embodiments, the first die 12A includes a front-side bonding structure 106A, and the second die 12B includes a front-side bonding structure 106B. As Figure 11As shown, the first die 12A and the second die 12B are face-to-face bonded via a first bonding structure 106A, and the first bonding structure 106A is connected to the corresponding second bonding structure 106B using a bonding interface BI1. In one embodiment, the bonding interface BI1 is a hybrid bonding interface. In some embodiments, the 3D stacked structure 40 includes a redistribution layer (RDL) 18 disposed on the first die 12A and conductive terminals 20 located on the RDL 18. In some embodiments, within the peripheral region of the 3D stacked structure 40, the seal ring structures 1043A of the first die 12A and the seal ring structures 1043B of the second die 12B are arranged in a ring shape along the peripheral region of the first die 12A and the peripheral region of the second die 12B, respectively. Additionally, the position of the seal ring structure 1043A overlaps (partially or fully) with the position of the seal ring structure 1043B. The seal ring structures 1043A and 1043B can be arranged as rings stacked on top of each other. In one embodiment, the seal ring structures 1043A and 1043B are generally aligned in the vertical direction (along the thickness direction). In some embodiments, the dummy pads 1066A of the first die 12A are bonded to the corresponding dummy pads 1066B of the second die 12B, and both the dummy pads 1066A and 1066B are located between the seal ring structures 1043A and 1043B. Additionally, within the peripheral region of the 3D stacked structure 40, there is a metal-free region DB1A sandwiched between the dummy pad 1066A and the seal ring structure 1043A, and there is a metal-free region DB1B sandwiched between the dummy pad 1066B and the seal ring structure 1043B. In some embodiments, the dielectric-only zone DB1B of the insulating material 105B is generally aligned in the vertical direction with the dielectric-only zone DB1A of the insulating material 105A.

[0051] In some embodiments, the semiconductor devices 103A of the first die 12A and the semiconductor devices 103B of the second die 12B are electrically connected via metallization structures 104A and 104B and bonding pads 1062A and 1062B located between the metallization structures 104A and 104B. In some embodiments, the conductive terminals 20 are electrically connected to the first die 12A and the second die 12B via the RDL 18 and the TSV 1048A that penetrate the semiconductor substrate 102A of the first die 12A.

[0052] In Figure 12In [the figure], the 3D stacked structure 50 includes at least a first die 12A and a second die 12B located on the first die 12A. In some embodiments, the first die 12A and the second die 12B perform different functions, but have substantially the same size. In some embodiments, the first die 12A and the second die 12B perform substantially the same or similar functions and have substantially the same size. For example, the first die 12A and / or the second die 12B may be similar to the semiconductor die 10D described in the previous paragraph. As Figure 12 shown, the first die 12A and the second die 12B are face-to-face bonded, and some structural features are modified to have a configuration different from that of the die 10D.

[0053] In some embodiments, the first die 12A includes a front-side bonding structure 106A located above the metallization structure 104A, and the second die 12B includes a back-side bonding structure 106B located below the metallization structure 104B and on the semiconductor substrate 102B. As Figure 12 shown, the front side of the first die 12A and the back side of the second die 12B are bonded via the connected bonding structures 106A and 106B having a bonding interface BI2. In one embodiment, the bonding interface BI2 is a hybrid bonding interface. In certain embodiments, the 3D stacked structure 50 includes an RDL 18 disposed on the back side of the first die 12A and conductive terminals 20 located on the RDL 18.

[0054] In some embodiments, in the peripheral region of the 3D stacked structure 50, the seal ring structure 1043A of the first die 12A and the seal ring structure 1043B of the second die 12B are respectively arranged in a ring shape along the peripheral region of the first die 12A and the peripheral region of the second die 12B. In addition, the seal ring structures 1043A and 1043B are substantially vertically aligned (along the thickness direction). As Figure 12 shown, the dummy pad 1066A is located directly above the seal ring structure 1043A in the peripheral region of the first die 12A, and the dummy pad 1066B is located directly below the seal ring structure 1043B in the peripheral region of the second die 12B. In some embodiments, the dummy pad 1066A of the first die 12A is directly bonded to the corresponding dummy pad 1066B of the second die 12B. In addition, in the peripheral region of the 3D stacked structure 50, there is a metal-free pad region DB1B of the insulating material 105B located directly above the seal ring structure 1043B, and no metal pad or metal wire is formed in the metal-free pad region DB1B. In one embodiment, the metal-free region DB1B may be an annular region that surrounds the metal pad 1042B formed above the metallization structure 104B in the main device region.

[0055] Referring to Figure 12, in some embodiments, a nail via 1065 extending between the dummy pad 1066A and the seal ring structure 1043A physically connects the dummy pad 1066A and the seal ring structure 1043A. The seal ring structure 1043A, the nail via 1065, the paired dummy pads 1066A, 1066B are electrically floating, and the seal ring structure 1043B is electrically floating. In some embodiments, the nail via 1065 is not used as an electrical connection part (i.e., not part of the electrical connection path of the 3D stacked structure), and the nail via 1065 connecting to the seal ring structure 1043A can be used as a structural reinforcement component to enhance the structural integrity during dicing. Additionally, such a structural reinforcement feature is electrically isolated from the semiconductor devices within the 3D stacked structure.

[0056] In some embodiments, there is a padless region of the insulating material 105A (in which no metal pad or aluminum pad is formed), such a padless region is sandwiched between the dummy pad 1066A and the seal ring structure 1043A, but there is a nail via 1065 located in the padless region (represented by a dashed ring). In one embodiment, such a padless region is not a metal-free region or a region having only a dielectric, because nail vias are formed in such a padless region. Such a padless region in which nail vias are formed can be used as a cracking stopper, because the nail vias enhance the structural resistance to dicing, and the padless region without metal pads reduces film delamination or cracking occurring from the edge. In some embodiments, the nail via 1065, the paired dummy pads 1066A, 1066B are generally vertically aligned with the region DB1B having only a dielectric. As Figure 12 shown in the schematic diagram in the upper left part of, the metal-free region DB1B (represented by a dashed line) can be an annular region overlapping with the annular seal ring structure 1043, and the dummy pad 1066B (together with the dummy pad 1066A and the nail via 1065) is arranged along the span of the metal-free region DB1B and is located within the span of the metal-free region DB1B. In some embodiments, the semiconductor devices 103A and 103B of the first die 12A and the second die 12B are electrically connected via the metallization structures 104A and 104B, the TSV 1048B, and the bonding pads 1062A and 1062B. In some embodiments, the conductive terminal 20 is electrically connected to the first die 12A via the RDL 18 and the TSV 1048A of the first die 12A, and is further electrically connected to the second die 12B via the metallization structure 104A, the bonding pads 1062A, 1062B, the metallization structure 104B, and the TSV 1048B.

[0057] In some embodiments, a wafer-on-wafer (WoW) process may be utilized to fabricate the 3D stacked structures 40 and 50. Additionally, the above 3D stacked structures may be further bonded to a circuit substrate or used as a packaging unit, and may be fabricated into a 3D stacked package or a CoWoS package. The present disclosure is not limited to the packaging structures shown in the figures.

[0058] Figure 13 , Figure 14 and Figure 15 FIGS. illustrate schematic cross-sectional views of some portions of exemplary 3D stacked structures in accordance with various embodiments of the present disclosure. In the following figures, the bonding portion between the first die and the second die of the 3D stacked structure is enlarged for illustrative purposes.

[0059] Referring to Figure 13 , in some embodiments, the 3D stacked structure 60 includes a bottom die 130A, a top die 130B bonded to the bottom die 130A, and passivation layers PA and PB covering the bottom and the top of the stacked structure 60. In some embodiments, the bonding structure 106A located on the back side of the bottom die 130A includes bonding pads 1062A, dummy bonding pads 1064A, and dummy pads 1066A embedded in a dielectric material 1061A. In some embodiments, the bonding structure 106B located on the front side of the top die 130B includes bonding pads 1062B, dummy bonding pads 1064B, and dummy pads 1066B embedded in a dielectric material 1061B. Using a hybrid bonding interface BI3, there is a dielectric-to-dielectric bond between the dielectric materials 1061A and 1061B, and there are metal-to-metal bonds between the paired pads 1062A / 1062B, 1064A / 1064B, and 1066A / 1066B. In some embodiments, the dummy pads 1066A and 1066B are located within a first region R1 of the stacked structure, while the dummy bonding pads 1064A and 1064B and the bonding pads 1062A and 1062B are located within a second region R2. In some embodiments, the second region R2 is or includes a main region where devices are formed, and the first region R1 is or includes a peripheral region where no active or passive devices are formed.

[0060] Referring to Figure 13, within the peripheral region R1 of the 3D stacked structure 60, there is a metal-free region DB1A of the insulating material 105A sandwiched between the dummy pad 1066A and the sealing ring structure 1043A, and there is a metal-free region DB1B of the insulating material 105B sandwiched between the dummy pad 1066B and the sealing ring structure 1043B. In some embodiments, the regions DB1B and DB1A having only dielectrics are generally aligned in the vertical direction (in the thickness direction). In some embodiments, as an electrical connection path, the metallization structure 104B and the contact pad 1042B in the second region R2 are connected to the bonding pad 1062B via the via 1045B, and the bonding pad 1062A is connected to the metallization structure 104A and the contact pad 1042A via the TSV 1048A. In some embodiments, the conductive terminal 20 is electrically connected to the contact pad 1042A for further electrical connection.

[0061] Referring to Figure 14 , in some embodiments, the 3D stacked structure 70 is similar to Figure 13 the stacked structure 60 shown, and the same reference numerals can be used to label the same components. In some embodiments, the 3D stacked structure 70 has a hybrid bonding interface BI4, and there is a dielectric-to-dielectric bond between the dielectric materials 1061A, 1061B, and there is a metal-to-metal bond between the paired bonding pads 1062A / 1062B, the dummy bonding pads 1064A / 1064B, and the dummy pads 1066A / 1066B. In some embodiments, the dummy pads 1066A, 1066B are located in the first region R1, while the dummy bonding pads 1064A, 1064B and the bonding pads 1062A, 1062B are located in the second region R2.

[0062] Referring to Figure 14, within the peripheral region R1 of the 3D stacked structure 70, there is a metal-free region DB1A sandwiched between the dummy pad 1066A and the sealing ring structure 1043A, and there is a stud through-hole (metallic through-hole) 1065B that extends between the dummy pad 1066B and the sealing ring structure 1043B and connects the dummy pad 1066B and the sealing ring structure 1043B. In some embodiments, the paired dummy pads 1066A / 1066B and the stud through-hole 1065B fall within the span of the region DB1A that has only a dielectric. In some embodiments, the paired dummy pads 1066A / 1066B and the stud through-hole 1065B are connected to the sealing ring structure 1043B and are electrically floating. In some embodiments, there is a padless region of the insulating material 105B (in which no metal pad or aluminum pad is formed), such a padless region is sandwiched between the dummy pad 1066B and the sealing ring structure 1043B, but there is a stud through-hole 1065B located in the padless region (represented by a dashed ring).

[0063] Referring to Figure 15 , in some embodiments, the 3D stacked structure 80 is similar to Figure 14 the stacked structure 70 shown, and the same reference numerals can be used to label the same components. In some embodiments, in addition to the dummy pads 1066A, 1066B, there is also a stud through-hole 1065B located in the first region R1. In addition, in addition to the dummy bonding pads 1064A, 1064B and the bonding pads 1062A, 1062B located in the second region R2, there is also a stud through-hole 1065B located in the second region R2. In some embodiments, the 3D stacked structure 80 has a hybrid bonding interface BI5, and there is a dielectric-to-dielectric bond between the dielectric materials 1061A, 1061B, and there is a metal-to-metal bond between the paired bonding pads 1062A / 1062B, the dummy bonding pads 1064A / 1064B and the dummy pads 1066A / 1066B.

[0064] Referring to Figure 15, in the peripheral region R1, there is a metal-free region DB1A sandwiched between the dummy pad 1066A and the sealing ring structure 1043A, and the stud via hole (metallic via hole) 1065B extends between the dummy pad 1066B and the sealing ring structure 1043B and connects the dummy pad 1066B and the sealing ring structure 1043B. In some embodiments, the paired dummy pads 1066A / 1066B and the stud via hole 1065B connected to the sealing ring structure 1043B are electrically floating. In some embodiments, there is a padless region of the insulating material 105B (in which no metal pad or aluminum pad is formed), such a padless region is sandwiched between the dummy pad 1066B and the sealing ring structure 1043B, but there is a stud via hole 1065B located in the padless region (represented by the dashed ring). In some embodiments, the stud via hole 1065B extends between the dummy bonding pad 1064B and the metallization structure 104B. Since the dummy bonding pads 1064A / 1064B are electrically floating pads, the stud via hole 1065B connected to the dummy bonding pads 1064A / 1064B is not part of an electrical connection path.

[0065] In some embodiments, with respect to the bonding interface (represented by the dashed line), additional dummy pads and / or dummy bonding pads create more interface bonding pads and a more uniform layout design, which helps for a more reliable interface bonding and reduces delamination around the edge of the package unit. In addition, by eliminating the formation of aluminum pads on the sealing ring structure in the peripheral region, film rupture near the die edge is minimized. In fact, the presence of only dielectric regions and metal-free regions can act as a crack stopper for the stacked structure.

[0066] According to some embodiments of the present disclosure, a stacked structure is provided. The stacked structure includes a first die and a second die stacked on the first die and bonded to the first die. The first die has a first region and a second region surrounded by the first region. The first die includes a first metallization structure embedded in a first insulating material and a first bonding structure located on the first insulating material and the first metallization structure. In the first region, the first metallization structure includes a first sealing ring structure, and the first bonding structure includes a first dummy pad located on the first sealing ring structure. The second die includes a second metallization structure embedded in a second insulating material and a second bonding structure located on the second insulating material and the second metallization structure. The second metallization structure includes a second sealing ring structure, and the second bonding structure includes a second dummy pad located on the second sealing ring structure. The first die and the second die are bonded by the bonding of the first bonding structure and the second bonding structure. The first sealing ring structure and the second sealing ring structure are generally aligned in the vertical direction, and the first dummy pads are respectively bonded to the second dummy pads.

[0067] In some embodiments of the present disclosure, a stacked structure is provided. The stacked structure includes a first die, a second die stacked on and bonded to the first die, and a filling material located above the first die. The first die has a first region and a second region surrounded by the first region. The first die includes a first metallization structure embedded in a first insulating material and a first bonding structure located above the first insulating material and the first metallization structure. In the first region, the first metallization structure includes a first sealing ring structure, and the first bonding structure includes a first dummy pad located above the first sealing ring structure. The second die includes a second metallization structure embedded in a second insulating material and a second bonding structure located above the second insulating material and the second metallization structure. The second metallization structure includes a second sealing ring structure, and the second bonding structure includes a second dummy pad located above the second sealing ring structure. The filling material is disposed on the first die and around the second die. The second bonding structure is bonded to the first bonding structure, the second sealing ring structure is partially aligned with the first sealing ring structure, and the second dummy pads are respectively bonded to the first dummy pads in the first region.

[0068] In some embodiments of the present disclosure, a first padless region exists in the first insulating material, and the first padless region is sandwiched between the first sealing ring structure and the first dummy pad and overlaps with the first sealing ring structure. In some embodiments of the present disclosure, a second padless region exists in the second insulating material, and the second padless region is sandwiched between the second sealing ring structure and the second dummy pad and overlaps with the second sealing ring structure, and the first padless region in the first region is aligned with the second padless region. In some embodiments of the present disclosure, the stacked structure further includes a third die stacked on and bonded to the first die, where the third die includes a third metallization structure embedded in a third insulating material and a third bonding structure located above the third insulating material and the third metallization structure, where the third metallization structure includes a third sealing ring structure, and the third bonding structure includes a third dummy pad located above the third sealing ring structure. A third padless region exists in the third insulating material, and the third padless region is sandwiched between the third sealing ring structure and the third dummy pad and overlaps with the third sealing ring structure, and the first padless region in the first region is aligned with the third padless region.

[0069] It will be apparent to those skilled in the art that various modifications and changes can be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In summary, the present disclosure is intended to cover the provided modifications and changes that fall within the scope of the above patent application and their equivalents.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor stack structure, characterized in that, Comprising: A first die having a first region and a second region surrounded by the first region, wherein the first die includes a first metallization structure embedded in a first insulating material and a first bonding structure located above the first insulating material and the first metallization structure, wherein in the first region, the first metallization structure includes a first sealing ring structure, and the first bonding structure includes a first dummy pad located above the first sealing ring structure; And A second die stacked on and bonded to the first die, wherein the second die includes a second metallization structure embedded in a second insulating material and a second bonding structure located above the second insulating material and the second metallization structure, wherein the second metallization structure includes a second sealing ring structure, and the second bonding structure includes a second dummy pad located above the second sealing ring structure, Wherein the first die and the second die are bonded by bonding of the first bonding structure and the second bonding structure, the first sealing ring structure and the second sealing ring structure are substantially aligned in a vertical direction, and the first dummy pad is respectively bonded to the second dummy pad.

2. The semiconductor stack structure according to claim 1, wherein Wherein a first padless region exists in the first insulating material, the first padless region is located above the first sealing ring structure and overlaps with the first sealing ring structure.

3. The semiconductor stack structure according to claim 2, wherein, Wherein the first padless region is sandwiched between the first sealing ring structure and the first dummy pad.

4. The semiconductor stack structure according to claim 2, wherein, Wherein at least one stud via is located between at least one of the second dummy pads of the second sealing ring structure and the second dummy pad and connects the second sealing ring structure and the at least one of the second dummy pads.

5. The semiconductor stack structure according to claim 2, wherein Wherein a second padless region exists in the second insulating material, the second padless region is located above the second sealing ring structure and overlaps with the second sealing ring structure.

6. A semiconductor stack structure, characterized in that, Comprising: A first die having a first region and a second region surrounded by the first region, wherein the first die includes a first metallization structure embedded in a first insulating material and a first bonding structure located above the first insulating material and the first metallization structure, wherein in the first region, the first metallization structure includes a first sealing ring structure, and the first bonding structure includes a first dummy pad located above the first sealing ring structure; A second die stacked on and bonded to the first die, wherein the second die includes a second metallization structure embedded in a second insulating material and a second bonding structure located above the second insulating material and the second metallization structure, wherein the second metallization structure includes a second sealing ring structure, and the second bonding structure includes a second dummy pad located above the second sealing ring structure; And A filler material disposed on the first die and around the second die, Wherein the second bonding structure is bonded to the first bonding structure, the second sealing ring structure is partially aligned with the first sealing ring structure, and the second dummy pad is bonded to the first dummy pad in the first region, respectively.

7. The semiconductor stack structure according to claim 6, wherein Wherein a first padless region exists in the first insulating material, and the first padless region is sandwiched between the first sealing ring structure and the first dummy pad and overlaps with the first sealing ring structure.

8. The semiconductor stack structure according to claim 7, wherein, Wherein at least one stud via hole is located between at least one of the second dummy pads in the second sealing ring structure and the second dummy pad and connects the second sealing ring structure and the at least one of the second dummy pads in the second dummy pad.

9. The semiconductor stack structure according to claim 7, wherein Wherein a second padless region exists in the second insulating material, and the second padless region is sandwiched between the second sealing ring structure and the second dummy pad and overlaps with the second sealing ring structure, and the first padless region in the first region is aligned with the second padless region.

10. The semiconductor stack structure according to claim 9, wherein, Further comprising a third die stacked on and bonded to the first die, wherein the third die includes a third metallization structure embedded in a third insulating material and a third bonding structure located on the third insulating material and the third metallization structure, wherein the third metallization structure includes a third sealing ring structure, and the third bonding structure includes a third dummy pad located on the third sealing ring structure, a third padless region exists in the third insulating material, and the third padless region is sandwiched between the third sealing ring structure and the third dummy pad and overlaps with the third sealing ring structure, and the first padless region in the first region is aligned with the third padless region.

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