Shield gate trench MOSFET and power device
By introducing a dual-trench layout and oxide layer and gate polysilicon structure into the shielded gate trench MOSFET, the conductive channel density is increased, and the balance problem of high breakdown voltage and low on-resistance is solved, thereby achieving lower on-resistance and higher device efficiency.
Patent Information
- Application Number
- CN202422224880.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-09-10
AI Technical Summary
The prior art is difficult to achieve a balance between high breakdown voltage and low on-resistance in power MOSFET devices.
A shielded gate trench MOSFET structure with a dual trench layout is added, a shallow trench is added and an oxide layer and gate polysilicon are provided therein, forming two contact holes to increase the conductive channel density.
While maintaining high breakdown voltage, it significantly reduces on-resistance and improves device efficiency and performance.
Smart Images
Figure CN223157520U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a shielded-gate trench MOSFET and a power device. Background Art
[0002] With the growth of the demand for electronic consumer products, the demand for power MOSFET devices is increasing, such as in disk drives, automotive electronics, and power devices, etc. The trench MOSFET (Trench MOS) has a higher device integration, a lower on-resistance, a lower gate-drain charge density, and a larger current capacity, thus having lower switching losses and faster switching speeds, and is widely used in the low-voltage power field.
[0003] However, there is no obvious technical solution in the prior art that can enable the power MOSFET device to simultaneously obtain a high breakdown voltage and a low on-resistance, and achieve a balance between the high breakdown voltage and the low on-resistance. Summary of the Utility Model
[0004] Therefore, in order to overcome at least some of the defects and deficiencies of the above prior art, an embodiment of the utility model provides a shielded-gate trench MOSFET, which can reduce the on-resistance of the shielded-gate trench MOSFET, thereby improving the efficiency and performance of the device.
[0005] On the one hand, a shielded-gate trench MOSFET provided by an embodiment of the utility model includes: a substrate, an epitaxial layer, a first trench, a second trench, an oxide layer, a source polysilicon layer, and a gate polysilicon layer; wherein, an epitaxial layer is disposed on one side of the substrate; the first trench and the second trench are formed in the epitaxial layer, the first trench and the second trench are arranged at intervals, and the first trench and the second trench extend along the thickness direction of the epitaxial layer; the oxide layer, the source polysilicon layer, and the gate polysilicon layer are disposed in the first trench, wherein the oxide layer wraps the source polysilicon layer to isolate the source polysilicon layer from the gate polysilicon layer and the epitaxial layer; the oxide layer and the gate polysilicon layer are disposed in the second trench, and the gate polysilicon layer is disposed on the oxide layer; wherein, an active region and a well region are respectively formed in the end of the epitaxial layer far from the substrate, and the well region is disposed on the side of the source region close to the substrate; the first trench passes through the source region and the well region, and the second trench passes through the source region and the well region, wherein the depth of the first trench is greater than the depth of the second trench.
[0006] In an embodiment of the present utility model, the shield gate trench MOSFET further includes a surface metal layer, the surface metal layer is disposed on a side of the epitaxial layer away from the substrate, and contact holes are formed in the epitaxial layer; the contact holes are located between the first trench and the second trench, and the surface metal layer is filled in the contact holes.
[0007] In an embodiment of the present utility model, the depth of the contact holes is 0.2 - 0.5 micrometers, and the width of the contact holes is 0.05 - 0.5 micrometers.
[0008] In an embodiment of the present utility model, the height of the surface of the gate polysilicon layer away from the substrate is lower than the height of the surface of the epitaxial layer away from the substrate.
[0009] In an embodiment of the present utility model, the distance between the surface of the epitaxial layer away from the substrate and the surface of the gate polysilicon layer away from the substrate is 500 - 1500 angstroms.
[0010] In an embodiment of the present utility model, the gate polysilicon layer in the first trench corresponds to the gate polysilicon layer in the second trench, and the gate polysilicon layer in the first trench and the gate polysilicon layer in the second trench have the same height.
[0011] In an embodiment of the present utility model, the depth of the second trench is 0.2 - 1.5 micrometers.
[0012] In an embodiment of the present utility model, the width of the second trench is 0.1 - 2 micrometers
[0013] In an embodiment of the present utility model, the depth of the first trench is 2 - 10 micrometers.
[0014] On the other hand, a power device provided by an embodiment of the present utility model includes: the shield gate trench MOSFET as described above.
[0015] As can be seen from the above, the above technical features of the present utility model can have the following beneficial effects: By providing a first trench and a second trench, the first trench passes through the source region and the well region and extends to a position adjacent to the substrate, and the second trench passes through the source region and the well region and extends to the surface of the well region close to the substrate side, that is, the depth of the first trench exceeds the depth of the second trench. When a voltage is applied to the device gate electrode, the gate polysilicon layer in the first trench and the gate polysilicon layer in the second trench reach the MOSFET turn-on voltage simultaneously. A conductive channel is formed on the trench sidewall near the gate polysilicon layer in the first trench, and at the same time, a conductive channel is also formed on the trench sidewall near the gate polysilicon layer in the second trench. Therefore, when the gate electrode voltage is applied and the device is turned on, the conductive channel density doubles, thereby achieving the purpose of reducing the channel resistance of the shielded gate trench MOSFET, reducing the on-resistance of the device, and improving the efficiency and performance of the device. Description of the Drawings
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for description in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0017] Figure 1 It is a schematic structural diagram of a shielded gate trench MOSFET provided by the first embodiment of the present utility model.
[0018] Figures 2a - 2f It is a flowchart of a manufacturing method of a shielded gate trench MOSFET provided by the second embodiment of the present utility model.
[0019]
Description of the Drawings Reference Numerals
[0020] 10: Shielded gate trench MOSFET; 100: Substrate; 101: Epitaxial layer; 102: Source region; 103: Well region; 111: First trench; 112: Second trench; 120: Oxide layer; 121: Silicon nitride; 130: Source polysilicon layer; 140: Gate polysilicon layer; 150: Contact hole; 160: Surface metal layer. Detailed Embodiments
[0021] The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present utility model.
[0022] Power MOSFETs have characteristics such as high input impedance, small drive current, fast switching speed, and good high-temperature performance. Their advantages are widely used in the field of power electronics. High breakdown voltage, large current, and low on-resistance are the most critical indicators of power MOSFETs. The breakdown voltage is related to the on-resistance value. During the MOSFET design process, it is impossible to simultaneously obtain a high breakdown voltage and a low on-resistance. A balance needs to be achieved between the two.
[0023] In order to obtain as high a breakdown voltage and as low an on-resistance as possible, a new type of separated-gate structure MOSFET device has emerged. Compared with the ordinary trench MOSFET structure, its main feature is the addition of a deep trench separated-gate shorted to the source, and then the lateral electric field between the separated-gates is utilized to improve the device's breakdown voltage.
[0024] Currently, the SGT (Shield Gate Trench) device, as a new type of shielded-gate trench MOSFET structure, uses the charge balance principle to alleviate the contradiction between the device's breakdown voltage and on-resistance. Its optimization of the breakdown voltage and on-resistance is mainly based on the improvement of process capabilities. For example, trench etching processes with a higher aspect ratio and polycrystalline filling processes make the device's unit cell pitch smaller, thereby optimizing the on-resistance.
[0025]
First Embodiment
[0026] In order to further reduce the on-impedance in this application and make the device's performance more excellent, this application proposes a shielded-gate trench MOSFET device with a double-trench layout. The difference from the traditional SGT structure is that, as Figure 1 shown, the shielded-gate trench MOSFET device proposed in this application adds a shallow trench (i.e., the second trench) between the existing two deep trenches (i.e., the first trench). An oxide layer (such as a gate oxide layer) and gate polysilicon are arranged in the shallow trench. Since the added shallow trench occupies the position of the contact hole in the original SGT device structure, the contact holes of the device structure in this application change from one to two, which are respectively placed on both sides of the shallow trench.
[0027] As Figure 1 shown, an embodiment of the present utility model provides a shielded-gate trench MOSFET10. The shielded-gate trench MOSFET10 includes, for example: a substrate 100, an epitaxial layer 101, a first trench 111, a second trench 112, an oxide layer 120, a source polysilicon layer 130, and a gate polysilicon layer 140;
[0028] Among them, an epitaxial layer 101 is provided on one side of the substrate 100; the first trench 111 and the second trench 112 are formed in the epitaxial layer 101.
[0029] The substrate 100 is, for example, a substrate wafer, which is the basis for fabricating a shield-gate trench MOSFET. Subsequent other components, such as the epitaxial layer 101, etc., all need to be grown on the substrate 100. The substrate wafer can be, for example, a wafer made of single-crystalline semiconductor material, which is an important step in semiconductor fabrication and lays the foundation for subsequent circuit etching.
[0030] The first trench 111 is formed in the epitaxial layer 101. Then, source polysilicon is deposited in the first trench 111, and the source polysilicon in the first trench 111 is etched back to form a source polysilicon layer 130, that is, the source polysilicon in the first trench 111 is etched back to form the source polysilicon layer 130. After depositing an isolation oxide layer, the second trench 112 is etched.
[0031] The first trench 111 and the second trench 112 can be formed, for example, by etching on the epitaxial layer 101. The first trench 111 and the second trench 112 are arranged at intervals. The first trench 111 and the second trench 112 extend along the thickness direction of the epitaxial layer 101. The oxide layer 120, the source polysilicon layer 130, and the gate polysilicon layer 140 are disposed in the first trench 111. Among them, the oxide layer 120 wraps the source polysilicon layer 130 to isolate the source polysilicon layer 130 from the gate polysilicon layer 140 and the epitaxial layer 101, that is, the upper part (including the top), both sides, and the lower part (including the bottom) of the source polysilicon layer 130 all have the oxide layer 120.
[0032] The oxide layer 120 and the gate polysilicon layer 140 are disposed in the second trench 112, and the gate polysilicon layer 140 is disposed on the oxide layer 120. Among them, an active region 102 and a well region 103 are respectively formed in one end of the epitaxial layer 101 away from the substrate 100. The well region 103 is disposed on one side of the source region 102 close to the substrate 100. The first trench 111 passes through the source region 102 and the well region 103, and the second trench 112 passes through the source region 102 and the well region 103, where the depth of the first trench 111 is greater than the depth of the second trench 112.
[0033] Only a gate oxide layer needs to be grown or deposited in the second trench 112, and then gate polysilicon is deposited, and the gate polysilicon is etched back to form a gate polysilicon layer 140 in the second trench 112.
[0034] The shielded-gate trench MOSFET 10 further includes a well region (P-body) 103 and a source region (N+Plus) 102. Both the well region 103 and the source region 102 are located within the epitaxial layer 101. The source region 102 is close to the side of the epitaxial layer 101 away from the substrate 100, and the well region 103 is disposed on the side of the source region 102 close to the substrate, that is, the well region 103 is disposed below the source region 102.
[0035] In this embodiment, by providing the first trench 111 and the second trench 112, the gate polysilicon in the first trench 111 and the gate polysilicon in the second trench 112 are at the same potential. The gate electrodes of the shielded-gate trench MOSFET 10 are respectively interconnected with the gate polysilicon layer 140 in the first trench 111 and the gate polysilicon layer 140 in the second trench 112. When a voltage is applied to the gate electrodes of the shielded-gate trench MOSFET 10, the gate polysilicon layer 140 in the first trench 111 and the gate polysilicon layer 140 in the second trench 112 will reach the gate electrode voltage simultaneously. A conductive channel is formed on the sidewall of the first trench near the gate polysilicon layer 140 in the first trench 111, and at the same time, a conductive channel is also formed on the sidewall of the second trench near the gate polysilicon layer 140 in the second trench 112. Therefore, when a gate electrode voltage is applied and the shielded-gate trench MOSFET is turned on, the density of the conductive channels doubles, thereby achieving the purpose of reducing the channel resistance of the shielded-gate trench MOSFET.
[0036] Furthermore, the shielded-gate trench MOSFET 10 further includes a surface metal layer 160, and a contact hole 150 is formed in the epitaxial layer 101; the contact hole 150 is located between the first trench 111 and the second trench 112, the surface metal layer 160 is disposed on the side of the epitaxial layer 101 away from the substrate 100, and the surface metal layer 160 is filled in the contact hole 150. The surface metal layer 160 is, for example, a single-layer aluminum alloy. By filling tungsten metal in the contact hole 150 and interconnecting it with the surface metal layer 160, an electrical connection between the surface metal layer 160 and the gate polysilicon layer 140 and the source polysilicon layer 130 is achieved.
[0037] Among them, the surface metal layer 160 can be formed by the process of existing SGT devices to form a structurally complete MOSFET device. The depth of the contact hole is 0.2 - 0.5 microns, and the width of the contact hole is 0.05 - 0.5 microns.
[0038] Further, the height of the gate polysilicon layer 140 away from the surface of the substrate 100 (i.e., the upper surface of the gate polysilicon layer 140) is lower than the height of the epitaxial layer 101 away from the substrate (i.e., the upper surface of the epitaxial layer 101), that is, the height of the gate polysilicon layer 140 etched in the first trench 111 and the second trench 112 is lower than the height of the epitaxial layer 101, or the height of the gate polysilicon layer 140 etched in the first trench 111 and the second trench 112 is lower than the height of the silicon plane. The silicon plane is the height of the epitaxial layer 101 after growing the epitaxial layer 101 on the substrate 100. Since the epitaxial layer 101 will have its height reduced after processes such as oxidation and etching.
[0039] Specifically, the distance between the surface of the epitaxial layer 101 away from the substrate 100 and the surface of the gate polysilicon layer 140 away from the substrate 100 is 500 - 1500 angstroms.
[0040] Further, the gate polysilicon layer 140 in the first trench 111 corresponds to the gate polysilicon layer 140 in the second trench 112, and the gate polysilicon layer 140 in the first trench 111 has the same height as the gate polysilicon layer 140 in the second trench 112. Of course, the height of the gate polysilicon layer 140 in the first trench 111 and the height of the gate polysilicon layer 140 in the second trench 112 can also be basically the same. Considering the actual manufacturing and production situation, there may be a slight difference in height between the two, but the difference is not significant. Therefore, the height of the gate polysilicon layer 140 in the first trench 111 and the height of the gate polysilicon layer 140 in the second trench 112 are basically the same. Setting the height of the gate polysilicon layer 140 in the first trench 111 and the height of the gate polysilicon layer 140 in the second trench 112 to be basically the same is to make the gate polysilicon layer 140 in the first trench 111 and the gate polysilicon layer 140 in the second trench 112 at the same potential, so that the conduction channel density doubles when the device is turned on, thereby achieving the purpose of reducing the channel resistance of the shielded gate trench MOSFET.
[0041] In a preferred embodiment of the present application, the depth range of the first trench 111 is 2 to 10 micrometers. The depth range of the second trench 112 is 0.2 to 1.5 micrometers. By defining the depth ranges of the first trench 111 and the second trench 112 in this embodiment, it is possible to ensure that the sidewalls of the first trench 111 and the second trench 112 are not damaged during subsequent steps, further ensuring the performance of the device. At the same time, by defining the depth range of the second trench 112 and the depth range of the first trench, and the depth of the second trench 112 being less than the depth of the first trench 111, it can be ensured that the height of the gate polysilicon layer 140 etched in the first trench 111 is the same as the height of the gate polysilicon layer 140 etched in the second trench 112, thereby further reducing the channel resistance to achieve a lower on-resistance.
[0042] Furthermore, the width of the second trench 112 is 0.1 - 2 micrometers. By defining the width of the second trench 112 and the width of the contact hole 150, it is ensured that the width ranges of the second trench 112 and the contact hole 150 do not exceed the spacing formed between two first trenches 111.
[0043] Furthermore, the breakdown voltage of the shielded gate trench MOSFET 10 is 30 - 200 volts. Through simulation experiments on the device of the present application and the SGT device of the prior art, the simulation results shown in Table 1 below are obtained:
[0044]
[0045] Table 1
[0046] As can be seen from Table 1 above, the existing SGT structure and the present application both use the same epitaxial material. With the first trench parameters unchanged, the breakdown voltage of the device remains at 68 volts. However, due to the introduction of the second trench in the device structure of the present application, the resistance of the device during conduction is lower and the performance is more superior, with the RSP being reduced by approximately 10.3% compared to the original traditional structure. That is, the device of the present application can achieve a lower on-resistance under the same breakdown voltage.
[0047] By providing the second trench 112 between two first trenches 111 in the present application, compared with the existing SGT devices, the device of the present application can further reduce the on-resistance while maintaining the breakdown voltage unchanged. At the same time, the device of the present application can use a smaller element size to achieve the same on-resistance specification as the existing SGT devices, and can obtain better other dynamic parameters to achieve lower switching losses, thereby further improving the reliability of the device.
[0048]
Second Embodiment
[0049] As Figures 2a - 2fAs shown in the figure, this embodiment provides a manufacturing process for a shield-gate trench MOSFET. The specific structure of the shield-gate trench MOSFET can refer to the shield-gate trench MOSFET described in the first embodiment above, and will not be elaborated here specifically.
[0050] Specifically, as Figure 2a shown in the figure, an epitaxial layer 101 is grown on the substrate 100, and an oxide-nitride-oxide layer is deposited on the epitaxial layer 101 to form a hard mask. This structure is the basis for generating the shield-gate trench MOSFET and is the basic condition for ensuring the performance of the MOSFET device. The thickness of the epitaxial layer 101 is determined according to the breakdown voltage between the drain and source electrodes. A structure of an oxide-nitride-oxide layer with a certain thickness is deposited on the upper surface of the epitaxial layer to form a hard mask, so as to protect the non-trench area on the epitaxial layer 101 when forming the trench.
[0051] Then, trench etching is performed on the epitaxial layer 101. First, a structure of an oxide layer 120 - nitride layer 121 - oxide layer 120 is deposited to form a hard mask, such as Figure 2a the structure of the oxide layer 120 and the nitride layer 121 shown in the figure. That is, the epitaxial layer 101 is etched on the hard mask using a trench mask plate to obtain a first trench 111, and the depth range of the first trench is between 2 microns and 10 microns.
[0052] Secondly, as Figure 2b shown in the figure, growth is performed on the surface of the first trench 111 and the epitaxial layer 101 to grow a field oxide layer (i.e., oxide layer 120) as a field dielectric layer. Then, source polysilicon is filled in the field dielectric layer and source polysilicon etch-back is performed. First, source polysilicon is filled in the field dielectric layer within the first trench 111, and by etching back the source polysilicon, source polysilicon with a suitable height is obtained, and a source polysilicon layer 130 is formed, such that the height of the source polysilicon layer 130 is less than the depth of the first trench 111.
[0053] As Figure 2c shown in the figure, then for the device with the source polysilicon layer 130 formed, an oxide layer is deposited using the HDPCVD (high-density plasma chemical vapor deposition) method to obtain an oxide layer 120 for isolation.
[0054] As Figure 2d shown in the figure, the second trench 112 is etched to remove part of the isolation oxide layer, and then a gate oxide layer 120 is grown above the isolation oxide layer within the first trench 111, and a gate oxide layer is grown above the isolation oxide layer within the second trench 112.
[0055] As Figure 2eAs shown, gate polysilicon is deposited on the oxide layer of the gate, and through etch-back, a gate polysilicon layer 140 containing gate polysilicon is obtained. The distance between the upper surface of the gate polysilicon layer 140 and the silicon plane of the epitaxial layer 101 (i.e., the upper surface of the epitaxial layer 101 before etching) is 500 - 1500 angstroms, so as to form the gate polysilicon layer 140 in the first trench 111 and the second trench 112.
[0056] As Figure 2f shown, this process is the same as the remaining manufacturing processes of SGT devices in the prior art, and through this process, a structurally complete MOSFET device is finally formed.
[0057] This application reduces the process variability. By simply adding one etching process step for the second trench 112, that is, further reducing the on-resistance is achieved with the minimum process variation. The optimization of the on-components of the shield-gate trench MOSFET 10 is simpler.
[0058]
Third Embodiment
[0059] In this embodiment, the power device includes the shield-gate trench MOSFET as described in the first embodiment above. The power device is, for example, a low-voltage to medium-voltage power MOSFET, a high-efficiency DC-DC converter, a synchronous rectification controller, etc.
[0060] The specific effects of the power device can be as described in the first embodiment above, and will not be elaborated here specifically.
[0061] In addition, it can be understood that the foregoing embodiments are only exemplary descriptions of the present invention. On the premise that the technical features do not conflict, the structures are not contradictory, and the invention purpose of the present invention is not violated, the technical solutions of each embodiment can be arbitrarily combined and used.
[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the present invention.
Claims
1. A shield-gate trench MOSFET (10), characterized in that, Including: a substrate (100), an epitaxial layer (101), a first trench (111), a second trench (112), an oxide layer (120), a source polysilicon layer (130), and a gate polysilicon layer (140); Wherein, an epitaxial layer (101) is provided on one side of the substrate (100); the first trench (111) and the second trench (112) are formed in the epitaxial layer (101), the first trench (111) and the second trench (112) are arranged at intervals, and the first trench (111) and the second trench (112) extend along the thickness direction of the epitaxial layer (101); the oxide layer (120), the source polysilicon layer (130), and the gate polysilicon layer (140) are provided in the first trench (111), wherein the oxide layer (120) wraps the source polysilicon layer (130) to isolate the source polysilicon layer (130) from the gate polysilicon layer (140) and the epitaxial layer (101); the oxide layer (120) and the gate polysilicon layer (140) are provided in the second trench (112), and the gate polysilicon layer (140) is provided on the oxide layer (120); Wherein, an active region (102) and a well region (103) are respectively formed in the end of the epitaxial layer (101) away from the substrate (100), and the well region (103) is provided on the side of the source region (102) close to the substrate (100); the first trench (111) penetrates through the source region (102) and the well region (103), and the second trench (112) penetrates through the source region (102) and the well region (103), and the depth of the first trench (111) is greater than the depth of the second trench (112).
2. The shielded gate trench MOSFET (10) according to claim 1, wherein The shield gate trench MOSFET (10) further includes a surface metal layer (160), the surface metal layer (160) is provided on the side of the epitaxial layer (101) away from the substrate (100), and a contact hole (150) is formed in the epitaxial layer (101); the contact hole (150) is located between the first trench (111) and the second trench (112), and the surface metal layer (160) is filled in the contact hole (150).
3. The shielded gate trench MOSFET (10) according to claim 2, characterized in that, The depth of the contact hole (150) is 0.2 - 0.5 micrometers, and the width of the contact hole (150) is 0.05 - 0.5 micrometers.
4. The shield gate trench MOSFET (10) according to claim 1, wherein The height of the surface of the gate polysilicon layer (140) away from the substrate (100) is lower than the height of the surface of the epitaxial layer (101) away from the substrate (100).
5. The shielded-gate trench MOSFET (10) according to claim 4, wherein The distance between the surface of the epitaxial layer (101) away from the substrate (100) and the surface of the gate polysilicon layer (140) away from the substrate (100) is 500 - 1500 angstroms.
6. The shielded gate trench MOSFET (10) according to claim 5, characterized in that, The gate polysilicon layer (140) in the first trench (111) corresponds to the gate polysilicon layer (140) in the second trench (112), and the gate polysilicon layer (140) in the first trench (111) has the same height as the gate polysilicon layer (140) in the second trench (112).
7. The shielded-gate trench MOSFET (10) according to any one of claims 1-6, characterized in that, The depth of the second trench (112) is 0.2 - 1.5 microns.
8. The shielded-gate trench MOSFET (10) according to claim 7, wherein The width of the second trench (112) is 0.1 - 2 microns.
9. The shielded gate trench MOSFET (10) according to claim 7, wherein The depth of the first trench (111) is 2 - 10 microns.
10. A power device, characterized in that, Comprising: The shielded-gate trench MOSFET according to any one of claims 1 - 9 above.