Low-loss VDMOSFET structure based on SiC material
By introducing P-body area, P column and insulating heat insulator into the VDMOSFET structure of SiC material, the conductive channel and depletion layer design are optimized, and the problems of increased on-resistance and large losses under high voltage of VDMOSFET devices are solved, achieving low loss and high reliability.
Patent Information
- Application Number
- CN202421679111.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-16
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-07-16
AI Technical Summary
In order to achieve high voltage, existing VDMOSFET devices usually need to reduce the doping concentration of the epitaxial layer or increase the thickness of the epitaxial layer, resulting in an increase in on-resistance and an increase in loss.
Using a low-loss VDMOSFET structure based on SiC material, by forming multiple P-body areas and P columns in the N-drift region, combined with insulating heat insulation sheets, the conductive channel and depletion layer design is optimized, charge balance and heat isolation are achieved, and on-resistance and loss are reduced.
While maintaining high voltage, it significantly reduces on-resistance and losses, improves device reliability and efficiency, and reduces production costs.
Smart Images
Figure CN223157521U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of vertical double-diffused MOSFETs, and more specifically discloses a low-loss VDMOSFET structure based on SiC materials. Background Art
[0002] A VDMOSFET (vertical double-diffused MOSFET) is a single-stage device that uses a planar self-aligned process double-diffusion process on a high-resistivity epitaxial layer. By utilizing the difference in the junction depths of the two diffusions, a MOS structure multi-carrier conductive channel is formed in the horizontal direction. Its gate and drain are respectively located on the upper and lower surfaces of the chip, forming a vertical current channel. VDMOSFET devices are widely used in motor speed regulation, inverters, switching power supplies, electronic switches, high-fidelity audio, automotive electrical appliances, and electronic ballasts, etc.
[0003] With the continuous development of the power electronics industry, silicon carbide (SiC) shows great application potential due to its excellent material properties.
[0004] Since the high voltage of the VDMOSFET device is mainly formed by the reverse bias of the PN junction between the N-drain region and the P-region where the channel is located, in order to achieve high voltage, it is necessary to reduce the doping concentration of the epitaxial layer or increase the thickness of the epitaxial layer. However, this will lead to an increase in the on-resistance of the VDMOSFET device and large losses during the use of the VDMOSFET device. Therefore, a low-loss VDMOSFET structure based on SiC materials is designed. Summary of the Invention
[0005] The utility model provides a low-loss VDMOSFET structure based on SiC materials, which can solve the problem that in order to achieve high voltage, the doping concentration of the epitaxial layer of the VDMOSFET device must be reduced or the thickness of the epitaxial layer must be increased. However, this will lead to an increase in the on-resistance of the VDMOSFET device and large losses during the use of the VDMOSFET device.
[0006] To solve the above technical problems, according to one aspect of the present utility model, more specifically, a low-loss VDMOSFET structure based on SiC material, including a drain, a substrate, a source, and a gate. The substrate is welded to the upper surface of the drain. An N-drift region is epitaxially grown on the upper surface of the substrate. A plurality of P-body regions are diffused inside the N-drift region. A P-column is provided on the lower surface of the P-body region. There is a doping region around the P-column and the P-body region, and the doping region is boron. A P+ region is formed by diffusion inside the P-body region. The P+ region has a first N+ region and a second N+ region inside. The first N+ region is located on both sides above the inside of the P+ region, and the second N+ region is located in the middle position inside the P+ region. The gate is provided on the upper surfaces of the P+ region and the second N+ region. An insulating layer is transversely covered on the upper surfaces of the two first N+ regions on adjacent P+ regions. The source is embedded in each insulating layer.
[0007] In a preferred solution in some embodiments, a plurality of the P-columns are vertically arranged between the gate and the drain.
[0008] In a preferred solution in some embodiments, a conductive channel is formed by the difference in diffusion depth on both sides of the P-body region and the P+ region. The current moves along the surface in the conductive channel and is vertically received by the drain.
[0009] In a preferred solution in some embodiments, the substrate is highly doped N+.
[0010] In a preferred solution in some embodiments, the total doping amounts in the first N+ region and the P+ region are equal.
[0011] In a preferred solution in some embodiments, a P-region is embedded inside the N-drift region and between the two P-body regions. The upper surface of the P-region contacts the lower surface of the insulating layer.
[0012] In a preferred solution in some embodiments, the injection region of the P-region is 4 μm in the middle of the bonding protection layer, and the injection energy is 43 keV.
[0013] In a preferred solution in some embodiments, insulating and heat-insulating sheets are provided on the left and right sides of the upper surface of the insulating layer and between the source and the gate, and the thickness of the insulating and heat-insulating sheets is 3 μm.
[0014] In a preferred solution in some embodiments, the substrate is made of silicon carbide material.
[0015] The beneficial effects of the low-loss VDMOSFET structure based on SiC material of the present utility model are:
[0016] In the present utility model, under the condition of having the same current density and device size as the prior art, the present utility model has a higher blocking voltage and gate oxide reliability.
[0017] In the present utility model, under the condition of having the same blocking voltage as the prior art, the present utility model has a lower epitaxial wafer material cost, a larger current density, a smaller device size, and higher reliability, greatly reducing the device production cost.
[0018] In the present utility model, the setting of the heat insulation sheet can reduce the transfer of heat between the gate and the source, reduce the influence of the source heat generation on the gate, and improve the device reliability. Brief Description of the Drawings
[0019] The following further elaborates on the present utility model in detail with reference to the drawings and specific implementation methods.
[0020] Figure 1 It is a structural schematic diagram of the present utility model.
[0021] In the figure: 1. Drain; 2. Substrate; 3. N-drift region; 4. P-column; 5. Doped region; 6. P-body region; 7. P+ region; 8. First N+ region; 9. Second N+ region; 10. Insulating layer; 11. Source; 12. Gate; 13. P-region; 14. Insulating heat insulation sheet. Detailed Description of the Preferred Embodiments
[0022] The present utility model will be described in detail below with reference to the drawings and in conjunction with the embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other.
[0023] According to the attached Figure 1, a low-loss VDMOSFET structure based on SiC material is provided, including a drain 1, a substrate 2, a source 11 and a gate 12. The upper surface of the drain 1 is welded with the substrate 2. An N-drift region 3 is epitaxially grown on the upper surface of the substrate 2. Multiple P-body regions 6 are formed by diffusion inside the N-drift region 3. A P-column 4 is arranged on the lower surface of the P-body region 6. There is a doping region 5 around the P-column 4 and the P-body region 6. The doping region 5 is boron. After the doping region 5 forms covalent bonds with surrounding semiconductor atoms, a vacancy will be left. The hole is positively charged, and when moving in the VDMOSFET semiconductor, there are always electrons replenishing, so it appears as the movement of holes; a P+ region 7 is formed by diffusion inside the P-body region 6. The P+ region 7 has a first N+ region 8 and a second N+ region 9 inside. The first N+ region 8 is located on both sides above the inside of the P+ region 7, and the second N+ region 9 is located in the middle position inside the P+ region 7. The gate 12 is arranged on the upper surfaces of the P+ region 7 and the second N+ region 9. The upper surfaces of two first N+ regions 8 on adjacent P+ regions 7 are laterally covered with an insulating layer 10, and the source 11 is embedded inside each insulating layer 10.
[0024] As Figure 1 shown, a P-injection region is added below the Pwell, and a small amount of boron ions are injected into the outer layer of the P-injection region to form a P-region with a lower concentration. In the device blocking state, the two P-injection regions will completely deplete the drift region at a lower drain-source voltage, and high-voltage blocking can be achieved when the drift region is very thin, and the gate oxide can be effectively protected; when the device is conducting, since the thickness of the drift region is greatly reduced, the on-resistance of the device will also be greatly reduced, and there are two carriers, electrons and holes, in the drift region, which can also further reduce the resistance.
[0025] An insulating and heat-insulating sheet 14 is arranged between the gate 12 and the source 11, with a thickness of about 3um, which can reduce the heat transfer between the gate and the source, and avoid the influence on the gate structure and materials when the source heats up due to passing a large current, thereby improving the reliability of the device. The insulating and heat-conducting material can be composed of 70% ceramic fiber, 1% inorganic adhesive and 29% graphene.
[0026] Specifically, multiple P-columns 4 are vertically arranged between the gate 12 and the drain 1. A larger PN junction is formed between the P-column 4 and the N-drift region 3. When the VDMOSFET device is reverse-biased, a thick PN depletion layer is formed to achieve a high isolation voltage, which can effectively reduce the switching loss, improve the efficiency and reliability, solve the problem that the on-resistance increases with the increase of the rated voltage, and achieve a low on-resistance while maintaining a high voltage.
[0027] Specifically, the difference in diffusion depth on both sides of the P-body region 6 and the P+ region 7 forms a conductive channel, and the current moves along the surface in the conductive channel and is vertically received by the drain 1.
[0028] Specifically, the substrate 2 is highly doped N+.
[0029] Specifically, the total doping amounts in the first N+ region 8 and the P+ region 7 are equal. In the on state of the VDMOSFET, current flows from the gate 12 through the first and second N+ regions to the drain 1. In the blocking state, the N- drift region 3 is completely depleted at a relatively low drain voltage through the auxiliary depletion effect of the P pillar 4. Due to complete depletion, the equal amounts of opposite charges of the P pillar and the N pillar cancel each other out to achieve charge balance. Therefore, the breakdown voltage is approximately equal to the product of the critical electric field and the length of the drift region, which can reduce the specific on-resistance and lower the loss.
[0030] Specifically, a P- region 13 is embedded inside the N- drift region 3 and between two P- body regions 6. The upper surface of the P- region 13 contacts the lower surface of the insulating layer 10, and the thickness of the P- region 13 is 5 - 9 μm.
[0031] Specifically, the injection region of the P- region 13 is 4 μm in the middle of the bonding protection layer, and the injection energy is 43 keV, which can reduce the switching loss and improve the stability of the VDMOSFET device.
[0032] Specifically, insulating and heat-insulating sheets 14 are provided on the left and right sides of the upper surface of the insulating layer 10 and between the source 11 and the gate 12. The thickness of the insulating and heat-insulating sheets 14 is 3 μm. The insulating and heat-insulating sheets 14 are composed of 70% ceramic fiber, 1% inorganic adhesive, and 29% graphene. The insulating and heat-insulating sheets 14 have excellent electrical properties, high strength, and good insulation.
[0033] Specifically, the substrate 2 is made of silicon carbide. Silicon carbide has characteristics such as a large bandgap, high thermal conductivity, high critical breakdown field strength, and high electron saturation drift rate. The N- drift region 3 is a single-crystal thin film grown on the surface of the substrate 2 and the same as the substrate 2.
[0034] The working principle of the present utility model is:
[0035] There is a P pillar 4 below the P-body region 6, and there is a doped region 5 around the P pillar 4 and the P-body region 6. There are a first N+ region 8 and a second N+ region 9 in the P+ region 7. In the blocking state, the N-drift region 3 of the VDMOSFET device can be completely depleted at a lower drain voltage through the auxiliary depletion effect of the P pillar 4. The equal amounts of opposite charges of the P pillar 4 and the N pillar cancel each other out to achieve charge balance, realizing a low on-resistance while maintaining a high voltage, thereby reducing losses. There is a P-region 13 in the N-drift region 3, which changes the shape of the depletion region of the VDMOSFET device and removes the overlapping part between the source electrode and the N-drift region 3, which can greatly reduce the charge of the source electrode and improve the performance of the device. There is an insulating and heat-insulating sheet 14 between the source electrode 11 and the gate electrode 1. The thickness of the insulating and heat-insulating sheet 14 is 3 μm. The insulating and heat-insulating sheet 14 is composed of 70% ceramic fiber, 1% inorganic adhesive, and 29% graphene, which can reduce the heat transfer between two tiny components and has a good isolation effect.
[0036] All the electrical components mentioned in this article are electrical components that exist in reality.
[0037] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions, or substitutions made by those of ordinary skill in the art within the scope of the essence of the present invention also belong to the protection scope of the present invention.
Claims
1. A low-loss VDMOSFET structure based on SiC material, comprising a drain (1), a substrate (2), a source (11) and a gate (12), characterized in that: The substrate (2) is soldered to the upper surface of the drain (1). An N-drift region (3) is epitaxially grown on the upper surface of the substrate (2). A plurality of P-body regions (6) are formed by diffusion inside the N-drift region (3). A P pillar (4) is disposed on the lower surface of the P-body region (6). A doping region (5) is provided around the P pillar (4) and the P-body region (6), and the doping region (5) is boron. A P+ region (7) is formed by diffusion inside the P-body region (6). A first N+ region (8) and a second N+ region (9) are provided inside the P+ region (7). The first N+ region (8) is located on both upper sides inside the P+ region (7), and the second N+ region (9) is located at the middle position inside the P+ region (7). The gate (12) is disposed on the upper surfaces of the P+ region (7) and the second N+ region (9). An insulating layer (10) laterally covers the upper surfaces of the two first N+ regions (8) on adjacent P+ regions (7). The source (11) is embedded inside each insulating layer (10).
2. The low-loss VDMOSFET structure based on SiC material according to claim 1, characterized in that: A plurality of the P pillars (4) are vertically arranged between the gate (12) and the drain (1).
3. The low-loss VDMOSFET structure based on SiC material according to claim 1, characterized in that: A conductive channel is formed by the difference in diffusion depth on both sides of the P-body region (6) and the P+ region (7). Current moves along the surface inside the conductive channel and is vertically received by the drain (1).
4. The low-loss VDMOSFET structure based on SiC material according to claim 1, characterized in that: The substrate (2) is highly doped N+.
5. The low-loss VDMOSFET structure based on SiC material according to claim 1, characterized in that: The total doping amounts in the first N+ region (8) and the P+ region (7) are equal.
6. The low-loss VDMOSFET structure based on SiC material according to claim 1, characterized in that: A P-region (13) is embedded inside the N-drift region (3) and between the two P-body regions (6). The upper surface of the P-region (13) is in contact with the lower surface of the insulating layer (10).
7. The low-loss VDMOSFET structure based on SiC material according to claim 6, characterized in that: The injection region of the P-region (13) is the middle 4 μm of the bonding protection layer, and the injection energy is 43 keV.
8. The low-loss VDMOSFET structure based on SiC material according to claim 1, characterized in that: Insulating and heat-insulating sheets (14) are disposed on the left and right sides of the upper surface of the insulating layer (10) and between the source (11) and the gate (12). The thickness of the insulating and heat-insulating sheets (14) is 3 μm.
9. The low-loss VDMOSFET structure based on SiC material according to claim 1, characterized in that: The substrate (2) is made of silicon carbide material.