T-shaped three-level bridge arm

Abstract

The utility model discloses a T-shaped three-level bridge arm, and belongs to the field of power converters. The T-type three-level bridge arm comprises a first power semiconductor device, a second power semiconductor device, a third power semiconductor device, a fourth power semiconductor device and a first decoupling capacitor which are arranged on a first side surface of a printed circuit board, and a second decoupling capacitor which is arranged on a second side surface of the printed circuit board, the first power semiconductor device, the second power semiconductor device, the third power semiconductor device and the fourth power semiconductor device are arranged in a central symmetry manner; the first power semiconductor device, the second power semiconductor device, the third power semiconductor device and the first decoupling capacitor form a first power loop; and the second power semiconductor device, the third power semiconductor device, the fourth power semiconductor device and the second decoupling capacitor form a second power loop. The layout mode shortens the length of a power loop, reduces the area of the power loop, and reduces the parasitic inductance of the power loop.

Description

Technical Field

[0001] The utility model belongs to the field of power converters, and more specifically, relates to a T-type three-level arm. Background Art

[0002] The T-type three-level converter has advantages such as high conversion efficiency, small AC filter, and low output harmonics, and has been widely used in new energy power generation systems. So far, Si-IGBT is still the mainstream device of commercial T-type three-level converters. Compared with traditional Si-IGBT, SiC-MOSFET has a high switching frequency and low switching loss. Therefore, the T-type three-level converter based on SiC-MOSFET has the potential of high conversion efficiency, high power density, and high control bandwidth.

[0003] The T-type three-level arm is an important component of the T-type three-level converter. Since there is currently no commercial SiC T-type three-level arm power module, SiC discrete devices are required to construct the T-type three-level arm. When the SiC-MOSFET operates at high frequencies, the rising / falling rate of the switching voltage / current is very fast (i.e., high dv / dt and high di / dt). If the parasitic inductance of the power loop is large, extremely high voltage / current spikes will be generated during the switching transient, which will not only significantly increase the device operating stress but also generate serious electromagnetic interference, resulting in a reduction in the overall operating reliability of the inverter. In order to fully utilize the advantages of high-speed switching of SiC power devices, it is necessary to minimize the parasitic inductance of the power loop as much as possible.

[0004] For the T-type three-level arm, there is currently no layout method with low parasitic inductance of the power loop. In related technologies, those skilled in the art mostly adopt the traditional parallel layout method. Limited by the position constraints of power devices, the power loop is long and the surrounding area is large, resulting in a large parasitic inductance of the power loop. In addition, the two formed power loops are asymmetric in length and area, resulting in poor consistency of the parasitic inductance of the power loop. Summary of the Utility Model

[0005] Aiming at the defects of the related technologies, the purpose of the utility model is to provide a T-type three-level arm, aiming to solve the problems of large parasitic inductance of the power loop and poor consistency of the parasitic inductance caused by the traditional layout method.

[0006] To achieve the above purpose, the utility model provides a T-type three-level arm, which includes, in a direction perpendicular to the plane where the printed circuit board is located: a first power semiconductor device, a second power semiconductor device, a third power semiconductor device, a fourth power semiconductor device, a first decoupling capacitor, and a second decoupling capacitor;

[0007] The first power semiconductor device, the second power semiconductor device, the third power semiconductor device, the fourth power semiconductor device, and the first decoupling capacitor are respectively arranged on the first side of the printed circuit board, and the first power semiconductor device, the second power semiconductor device, the third power semiconductor device, and the fourth power semiconductor device are arranged in central symmetry;

[0008] The second decoupling capacitor is arranged on the second side of the printed circuit board;

[0009] The first power semiconductor device, the second power semiconductor device, the third power semiconductor device, and the first decoupling capacitor form a first power loop; the second power semiconductor device, the third power semiconductor device, the fourth power semiconductor device, and the second decoupling capacitor form a second power loop.

[0010] Optionally, the first power semiconductor device, the second power semiconductor device, the third power semiconductor device, and the fourth power semiconductor device are respectively arranged close to the four sides of the first side of the printed circuit board, in a windmill shape.

[0011] Optionally, the printed circuit board includes a top copper clad laminate, a second copper clad laminate, a third copper clad laminate, and a bottom copper clad laminate;

[0012] The first source electrode d1 of the first power semiconductor device, the second source electrode d2 and the second drain electrode s2 of the second power semiconductor device, and the third source electrode d3 of the third power semiconductor device are connected to the top copper clad laminate through vias;

[0013] The first drain electrode s1 of the first power semiconductor device and the second drain electrode s2 of the second power semiconductor device are connected to the second copper clad laminate through vias;

[0014] The second source electrode d2 of the second power semiconductor device and the third source electrode d3 of the third power semiconductor device are connected to the third copper clad laminate through vias;

[0015] The first drain electrode s1 of the first power semiconductor device, the second drain electrode s2 of the second power semiconductor device, the third drain electrode s3 of the third power semiconductor device, the fourth source electrode d4 and the fourth drain electrode s4 of the fourth power semiconductor device are connected to the bottom copper clad laminate through vias.

[0016] Optionally, the first source electrode d1 of the first power semiconductor device is connected to the second drain electrode s2 of the second power semiconductor device through the first decoupling capacitor;

[0017] The second drain electrode s2 of the second power semiconductor device and the fourth drain electrode s4 of the fourth power semiconductor device are connected to each other through the second decoupling capacitor.

[0018] Optionally, the first power semiconductor device, the second power semiconductor device, the third power semiconductor device, and the fourth power semiconductor device are respectively arranged in pairs on two parallel sides of the first side of the printed circuit board, forming a "field" shape.

[0019] Optionally, the printed circuit board includes a top copper clad laminate, a second copper clad laminate, a third copper clad laminate, and a bottom copper clad laminate;

[0020] The first source electrode d1 and the first drain electrode s1 of the first power semiconductor device, the second drain electrode s2 of the second power semiconductor device, the third drain electrode s3 of the third power semiconductor device, and the fourth source electrode d4 of the fourth power semiconductor device are connected to the top copper clad laminate through vias;

[0021] The second source electrode d2 of the second power semiconductor device and the third source electrode d3 of the third power semiconductor device are connected to the second copper clad laminate and the third copper clad laminate through vias;

[0022] The second drain electrode s2 of the second power semiconductor device, the third drain electrode s3 of the third power semiconductor device, the fourth source electrode d4 of the fourth power semiconductor device, and the fourth drain electrode s4 are connected to the bottom copper clad laminate through vias.

[0023] Optionally, the first source electrode d1 of the first power semiconductor device is connected to the second drain electrode s2 of the second power semiconductor device through the first decoupling capacitor;

[0024] The second drain electrode s2 of the second power semiconductor device and the fourth drain electrode s4 of the fourth power semiconductor device are connected through the second decoupling capacitor.

[0025] Optionally, the vias are filled with copper.

[0026] Optionally, the first power semiconductor device, the second power semiconductor device, the third power semiconductor device, and the fourth power semiconductor device all adopt TO-247-4 packages.

[0027] Through the above technical solutions conceived by the present utility model, compared with the prior art, the following beneficial effects can be achieved:

[0028] 1. The present utility model provides a T-type three-level bridge arm. By arranging four power semiconductor devices in a centrosymmetric manner on a printed circuit board, the layout structure of the power semiconductor devices is optimized. Without sacrificing the insulation distance, the pin pitch is reduced, that is, the distance between non-adjacent power semiconductor devices is reduced, thereby shortening the loop length and reducing the loop area. At the same time, the two formed power loops are concentrated in the central area surrounded by the four power semiconductor devices, enhancing the magnetic flux cancellation effect, thereby realizing the reduction of the parasitic inductance of the commutation loop. Moreover, due to the centrosymmetric arrangement of the four power semiconductor devices, the first power loop and the second power loop formed by them are basically symmetric in length and area, so the consistency of the parasitic inductance of the power loop is better.

[0029] 2. The present utility model provides a T-type three-level bridge arm. The four power semiconductor devices can be arranged close to the four sides of the printed circuit board in a windmill shape, or arranged in pairs on two parallel sides of the first side of the printed circuit board in a "field" shape. The layout of the four power semiconductor devices is dispersed, which is beneficial to the heat dissipation of the devices, thereby improving the reliability of the devices. At the same time, this technical solution does not increase the cost, so it does not increase the failure risk points and has universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a circuit diagram of a T-type three-level bridge arm topology;

[0031] Figure 2 is a schematic diagram of the top copper clad laminate distribution of a T-type three-level bridge arm provided by an embodiment of the present utility model;

[0032] Figure 3 is a schematic diagram of the second-layer copper clad laminate distribution of a T-type three-level bridge arm provided by an embodiment of the present utility model;

[0033] Figure 4 is a schematic diagram of the third-layer copper clad laminate distribution of a T-type three-level bridge arm provided by an embodiment of the present utility model;

[0034] Figure 5 is a schematic diagram of the bottom copper clad laminate distribution of a T-type three-level bridge arm provided by an embodiment of the present utility model;

[0035] Figure 6 is a schematic diagram of the top copper clad laminate distribution of another T-type three-level bridge arm provided by an embodiment of the present utility model;

[0036] Figure 7 is a schematic diagram of the second-layer copper clad laminate distribution of another T-type three-level bridge arm provided by an embodiment of the present utility model;

[0037] Figure 8 is a schematic diagram of the third-layer copper clad laminate distribution of another T-type three-level bridge arm provided by an embodiment of the present utility model;

[0038] Figure 9 It is a schematic diagram of the bottom copper clad laminate distribution of another T-type three-level bridge arm provided by the embodiment of the present utility model. Detailed implementation manners

[0039] In order to make the purpose, technical solutions and advantages of the present utility model clearer, the present utility model will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model. In addition, the technical features involved in the various embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.

[0040] The following describes the content involved in the above embodiments in conjunction with a preferred embodiment.

[0041] Figure 1 It is a schematic diagram of the parasitic inductance of the T-type three-level bridge arm, including the first power semiconductor device Q1, the second power semiconductor device Q2, the third power semiconductor device Q3, the fourth power semiconductor device Q4, the first decoupling capacitor C decu and the second decoupling capacitor C decl , and L xy represents the line inductance between devices.

[0042] In the positive half cycle of the modulation wave, the first power semiconductor device Q1 and the second power semiconductor device Q2 conduct complementarily, the third power semiconductor device Q3 conducts constantly, and the fourth power semiconductor device Q4 is constantly off, forming a first power loop. In the negative half cycle of the modulation wave, the third power semiconductor device Q3 and the fourth power semiconductor device Q4 conduct complementarily, the first power semiconductor device Q1 is constantly off, and the second power semiconductor device Q2 conducts constantly, forming a second power loop. Respectively use L u , L l to represent the total inductances of the first and second power loops. According to Figure 1 , the expression is as follows:

[0043]

[0044] In the formula, L C is the equivalent series inductance of the decoupling capacitor, L sw is the package inductance of the power semiconductor device, and M u , M l are the mutual inductances in the first and second power loops respectively. L C and L sw are independent of the layout, while the others depend on the power loop design.

[0045] In the related art, a traditional parallel layout method is mostly adopted. Limited by the position constraints of power devices, the power loop is long and the surrounding area is large, resulting in a large parasitic inductance of the power loop. In addition, there is an asymmetry in the length and area between the first power loop and the second power loop, resulting in poor consistency of the parasitic inductance of the power loop. Therefore, for a T-type three-level bridge arm, the traditional layout is not ideal.

[0046] In view of the above problems, the present utility model provides a T-type three-level bridge arm, which is used to solve the problem of reducing the parasitic inductance of the power loop of the T-type three-level bridge arm by optimizing the design of devices and wiring layout, and this solution avoids the adverse effects brought by the conventional solution while solving the problem.

[0047] As Figure 2 shown, a T-type three-level bridge arm includes, in a direction perpendicular to the plane of the printed circuit board: a first power semiconductor device, a second power semiconductor device, a third power semiconductor device, a fourth power semiconductor device, a first decoupling capacitor and a second decoupling capacitor;

[0048] The first power semiconductor device, the second power semiconductor device, the third power semiconductor device, the fourth power semiconductor device and the first decoupling capacitor are respectively arranged on the first side of the printed circuit board, and the first power semiconductor device, the second power semiconductor device, the third power semiconductor device and the fourth power semiconductor device are arranged in central symmetry;

[0049] The second decoupling capacitor is arranged on the second side of the printed circuit board;

[0050] The first power semiconductor device, the second power semiconductor device, the third power semiconductor device and the first decoupling capacitor form a first power loop; the second power semiconductor device, the third power semiconductor device, the fourth power semiconductor device and the second decoupling capacitor form a second power loop.

[0051] In the traditional layout, the four power semiconductor devices are arranged side by side. Although the distance between adjacent power semiconductor devices is small, the distance between non-adjacent power semiconductor devices is greatly increased. Therefore, the loop length and area are inevitably larger.

[0052] In this embodiment, by optimizing the layout structure of the power semiconductor devices, the four power semiconductor devices are arranged in central symmetry on the printed circuit board, and the pin pitch is reduced without sacrificing the insulation distance, so that the distance between non-adjacent power semiconductor devices is reduced, thereby shortening the loop length and reducing the loop area, and thus reducing the parasitic inductance of the power loop. Moreover, due to the central symmetry setting of the four power semiconductor devices, the first power loop and the second power loop formed by them are basically symmetrical in length and area, so that the consistency of the parasitic inductance of the power loop is better.

[0053] Reference Figure 2 and Figure 5 Reference Figure 6 and Figure 9 The first source d1 and the first drain s1 of the first power semiconductor device, the third source d3 and the third drain s3 of the third power semiconductor device, the second source d2 and the second drain s2 of the second power semiconductor device, the first decoupling capacitor C Decu form a first power loop; the fourth source d4 and the fourth drain s4 of the fourth power semiconductor device, the third source d3 and the third drain s3 of the third power semiconductor device, the second source d2 and the second drain s2 of the second power semiconductor device, the second decoupling capacitor C Decl form a second power loop.

[0054] The two power loops formed are concentrated in the central area surrounded by the four power semiconductor devices, enhancing the magnetic flux cancellation effect, so as to achieve the purpose of reducing the parasitic inductance of the commutation loop.

[0055] On the basis of the above embodiments, the embodiments of the present invention specifically provide two PCB layouts of power loops with low parasitic inductance. Refer to Figures 2 to 5 which is the distribution schematic diagram of each layer of copper clad board in the first layout method. Refer to Figures 6 to 9 which is the distribution schematic diagram of each layer of copper clad board in the second layout method.

[0056] In the two layout methods, the first power semiconductor device Q1 includes a first source d1 and a first drain s1, the second power semiconductor device Q2 includes a second source d2 and a second drain s2, the third power semiconductor device Q3 includes a third source d3 and a third drain s3; the fourth power semiconductor device Q4 includes a fourth source d4 and a fourth drain s4.

[0057] Refer to Figure 2 , in the first layout method, the first power semiconductor device, the second power semiconductor device, the third power semiconductor device and the fourth power semiconductor device are respectively arranged close to the four sides of the first side of the printed circuit board, in a windmill shape.

[0058] Among them, as Figure 2 shown, the arrangement order of the power semiconductor devices on the first side of the printed circuit board is the first power semiconductor device Q1, the third power semiconductor device Q3, the fourth power semiconductor device Q4 and the second power semiconductor device Q2 in clockwise order.

[0059] Refer to Figures 3 to 5 , optionally, the printed circuit board includes a top copper clad board, a second layer copper clad board, a third layer copper clad board and a bottom copper clad board;

[0060] The first source d1 of the first power semiconductor device, the second source d2 and the second drain s2 of the second power semiconductor device, and the third source d3 of the third power semiconductor device are connected to the top copper clad laminate through vias;

[0061] The first drain s1 of the first power semiconductor device and the second drain s2 of the second power semiconductor device are connected to the second copper clad laminate through vias;

[0062] The second source d2 of the second power semiconductor device and the third source d3 of the third power semiconductor device are connected to the third copper clad laminate through vias;

[0063] The first drain s1 of the first power semiconductor device, the second drain s2 of the second power semiconductor device, the third drain s3 of the third power semiconductor device, the fourth source d4 and the fourth drain s4 of the fourth power semiconductor device are connected to the bottom copper clad laminate through vias.

[0064] Among them, the vias are filled with metallic copper for connecting the pins and each layer of copper clad laminate.

[0065] Optionally, the first source d1 of the first power semiconductor device is connected to the second drain s2 of the second power semiconductor device through the first decoupling capacitor C Decu connected;

[0066] The second drain s2 of the second power semiconductor device and the fourth drain s4 of the fourth power semiconductor device are connected through the second decoupling capacitor C Decl connected.

[0067] This layout can reduce the average distance between different semiconductor power devices without sacrificing the insulation distance, and concentrate the commutation loop in the central area, reducing the loop area, and enhancing the magnetic flux cancellation effect, reducing the parasitic inductance of the commutation loop.

[0068] Refer to Figure 6 , the second layout method, the first power semiconductor device, the second power semiconductor device, the third power semiconductor device and the fourth power semiconductor device are respectively arranged in pairs on two parallel sides of the first side of the printed circuit board, in a "field" shape.

[0069] Among them, as Figure 6 shown, there are two parallel sides on the first side of the printed circuit board. The first power semiconductor device Q1 and the third power semiconductor device Q3 are arranged on one of the two sides, and the second power semiconductor device Q2 and the fourth power semiconductor device Q4 are arranged on the other of the two sides.

[0070] Refer toFigures 7 to 9 , optionally, the printed circuit board includes a top copper clad laminate, a second copper clad laminate, a third copper clad laminate, and a bottom copper clad laminate;

[0071] The first source d1 and the first drain s1 of the first power semiconductor device, the second drain s2 of the second power semiconductor device, the third drain s3 of the third power semiconductor device, and the fourth source d4 of the fourth power semiconductor device are connected to the top copper clad laminate through vias;

[0072] The second source d2 of the second power semiconductor device and the third source d3 of the third power semiconductor device are connected to the second and third copper clad laminates through vias;

[0073] The second drain s2 of the second power semiconductor device, the third drain s3 of the third power semiconductor device, the fourth source d4 of the fourth power semiconductor device, and the fourth drain s4 are connected to the bottom copper clad laminate through vias.

[0074] Among them, the vias are filled with metallic copper for connecting the pins and the copper clad laminates of each layer.

[0075] This layout can also reduce the average distance between different semiconductor power devices without sacrificing the insulation distance, and concentrate the commutation loop in the central area, reducing the loop area, and enhancing the magnetic flux cancellation effect, reducing the parasitic inductance of the commutation loop.

[0076] Optionally, the first source d1 of the first power semiconductor device is connected to the second drain s2 of the second power semiconductor device through the first decoupling capacitor C Decu connected;

[0077] The second drain s2 of the second power semiconductor device and the fourth drain s4 of the fourth power semiconductor device are connected through the second decoupling capacitor C Decl connected.

[0078] In the above two layout methods, the connection methods of the power semiconductor device with the first decoupling capacitor C Decu and the second decoupling capacitor C Decl are the same.

[0079] Using decoupling capacitors can provide transient energy for the commutation process and further reduce the effective length and area of the commutation loop.

[0080] Furthermore, in the above two layout methods, the four power semiconductor devices, the first decoupling capacitor C Decu and the second decoupling capacitor C Decl constitute the power loop in the same way.

[0081] Optionally, the first power semiconductor device, the second power semiconductor device, the third power semiconductor device, and the fourth power semiconductor device all adopt TO-247-4 package. This package has excellent switching performance and good heat dissipation performance, and is a widely used package form.

[0082] Based on the above two layout methods, through Q3D simulation, two PCB layout methods for reducing the parasitic inductance of the T-type three-level bridge arm power loop are further described.

[0083] The traditional parallel layout is simulated, and the parasitic inductance of the first power loop is 16.2 nH, and the parasitic inductance of the second power loop is 23.0 nH; the first layout method provided by the present invention is simulated, and the parasitic inductance of the first power loop is 13.2 nH, and the parasitic inductance of the second power loop is 11.0 nH; the second layout method provided by the present invention is simulated, and the parasitic inductance of the first power loop is 12.1 nH, and the parasitic inductance of the second power loop is 12.1 nH.

[0084] Therefore, compared with the traditional parallel layout method, for the two T-type three-level bridge arms provided by the present invention, the parasitic inductance of the first power loop is reduced by nearly 20%, the parasitic inductance of the second power loop is reduced by nearly 50%, and the consistency of the parasitic inductances of the first and second power loops is better.

[0085] In the embodiment of the present invention, by arranging four power semiconductor devices symmetrically centered on the printed circuit board, the layout structure of the power semiconductor devices is optimized, and the problems of large parasitic inductance and poor consistency of parasitic inductance in the traditional layout method are solved. The loop length is shortened and the loop area is reduced, the parasitic inductance of the power loop is reduced, the magnetic flux cancellation effect is enhanced, and the parasitic inductance of the commutation loop is reduced.

[0086] It is easy for those skilled in the art to understand that the above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A T-type three-level bridge arm, characterized in that, In a direction perpendicular to the plane of the printed circuit board, it includes: a first power semiconductor device, a second power semiconductor device, a third power semiconductor device, a fourth power semiconductor device, a first decoupling capacitor, and a second decoupling capacitor; The first power semiconductor device, the second power semiconductor device, the third power semiconductor device, the fourth power semiconductor device, and the first decoupling capacitor are respectively arranged on the first side of the printed circuit board, and the first power semiconductor device, the second power semiconductor device, the third power semiconductor device, and the fourth power semiconductor device are arranged in central symmetry; The second decoupling capacitor is arranged on the second side of the printed circuit board; The first power semiconductor device, the second power semiconductor device, the third power semiconductor device, and the first decoupling capacitor form a first power loop; the second power semiconductor device, the third power semiconductor device, the fourth power semiconductor device, and the second decoupling capacitor form a second power loop.

2. The T-type three-level bridge arm according to claim 1, characterized in that The first power semiconductor device, the second power semiconductor device, the third power semiconductor device, and the fourth power semiconductor device are respectively arranged close to the four sides of the first side of the printed circuit board, in a windmill shape.

3. The T-type three-level bridge arm according to claim 2, characterized in that, The printed circuit board includes a top copper clad laminate, a second copper clad laminate, a third copper clad laminate, and a bottom copper clad laminate; The first source electrode d1 of the first power semiconductor device, the second source electrode d2 and the second drain electrode s2 of the second power semiconductor device, and the third source electrode d3 of the third power semiconductor device are connected to the top copper clad laminate through vias; The first drain electrode s1 of the first power semiconductor device and the second drain electrode s2 of the second power semiconductor device are connected to the second copper clad laminate through vias; The second source electrode d2 of the second power semiconductor device and the third source electrode d3 of the third power semiconductor device are connected to the third copper clad laminate through vias; The first drain electrode s1 of the first power semiconductor device, the second drain electrode s2 of the second power semiconductor device, the third drain electrode s3 of the third power semiconductor device, the fourth source electrode d4 and the fourth drain electrode s4 of the fourth power semiconductor device are connected to the bottom copper clad laminate through vias.

4. The T-type three-level bridge arm according to claim 3, characterized in that, The first source electrode d1 of the first power semiconductor device is connected to the second drain electrode s2 of the second power semiconductor device through the first decoupling capacitor; The second drain electrode s2 of the second power semiconductor device and the fourth drain electrode s4 of the fourth power semiconductor device are connected to each other through the second decoupling capacitor.

5. The T-type three-level bridge arm according to claim 1, characterized in that, The first power semiconductor device, the second power semiconductor device, the third power semiconductor device, and the fourth power semiconductor device are respectively arranged in pairs on two parallel sides of the first side of the printed circuit board, in a "field" shape.

6. The T-type three-level bridge arm according to claim 5, characterized in that, The printed circuit board includes a top copper clad laminate, a second copper clad laminate, a third copper clad laminate, and a bottom copper clad laminate; The first source electrode d1 and the first drain electrode s1 of the first power semiconductor device, the second drain electrode s2 of the second power semiconductor device, the third drain electrode s3 of the third power semiconductor device, and the fourth source electrode d4 of the fourth power semiconductor device are connected to the top copper clad laminate through vias; The second source electrode d2 of the second power semiconductor device and the third source electrode d3 of the third power semiconductor device are connected to the second-layer copper clad laminate and the third-layer copper clad laminate through vias; The second drain electrode s2 of the second power semiconductor device, the third drain electrode s3 of the third power semiconductor device, the fourth source electrode d4 of the fourth power semiconductor device, and the fourth drain electrode s4 are connected to the bottom-layer copper clad laminate through vias.

7. The T-type three-level bridge arm according to claim 6, characterized in that The first source electrode d1 of the first power semiconductor device and the second drain electrode s2 of the second power semiconductor device are connected through the first decoupling capacitor; The second drain electrode s2 of the second power semiconductor device and the fourth drain electrode s4 of the fourth power semiconductor device are connected through the second decoupling capacitor.

8. The T-type three-level bridge arm according to claim 3 or 6, characterized in that, The vias are filled with metallic copper.

9. The T-type three-level bridge arm according to claim 1, characterized in that, The first power semiconductor device, the second power semiconductor device, the third power semiconductor device, and the fourth power semiconductor device all adopt TO-247-4 packages.

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