Level conversion circuit and power supply equipment

Abstract

The utility model discloses a level conversion circuit and power supply equipment, and relates to the technical field of power supplies, and the level conversion circuit comprises a signal channel, a first current mirror, a second current mirror, a third current mirror and a phase inverter. A first end of the signal channel inputs a level signal, a second end of the signal channel is connected with an input end of the first current mirror, a first mirror current output end of the first current mirror is connected with an input end of the phase inverter, a second mirror current output end of the first current mirror is connected with an input end of the second current mirror, and the first current mirror is further connected with a negative power supply. The mirror current output end of the second current mirror is connected with a third current mirror, the second current mirror is grounded, the input end of the third current mirror is connected with a negative power supply, the mirror current output end of the third current mirror is connected with the input end of the phase inverter, and the third current mirror is grounded. The circuit has a high conversion rate, can realize positive-to-negative conversion, and is powered by a single power supply, so that the complexity of a system in practical application can be reduced, and the application range is widened.

Description

Technical Field

[0001] The present application relates to the field of power supply technology, and in particular to a level conversion circuit and a power supply device. Background Art

[0002] Currently, there are multiple design solutions for level conversion circuits. The first is to use a linear resistor divider circuit, connecting two or more resistors in parallel to the power supply to convert high voltage to low voltage. The second is to use a cascade of operational amplifiers, using them as voltage followers or differential amplifiers to perform voltage proportional conversion. The third is to use bipolar transistor or field-effect transistor switching circuits, changing the input and output voltages by controlling the on / off switching devices. The fourth is to use an LDO regulator for level conversion. The fifth is to use an analog switch matrix, combining multiple switches to create a complex signal path for voltage conversion. However, these designs are mostly applied to the positive voltage domain and require multiple power supply voltages, which increases the complexity of the system in practical applications and reduces its scope of application. Although linear resistors in series can achieve positive voltage to negative voltage conversion, the input detection range is limited, the conversion rate is low, and it is significantly affected by power consumption. Therefore, providing a level conversion circuit with a wide input detection range, high conversion rate, and single power supply has become a technical problem that has been urgently addressed by those skilled in the art. Utility Model Content

[0003] The purpose of this application is to provide a level conversion circuit and power supply equipment with a high conversion rate and the ability to achieve positive to negative conversion. In addition, the level conversion circuit is powered by a single power supply, which can reduce the complexity of the system in actual application and broaden the scope of use.

[0004] To solve the above technical problems, the present application provides a level conversion circuit, comprising:

[0005] A signal channel, a first current mirror, a second current mirror, a third current mirror, and an inverter;

[0006] A level signal is input to a first end of the signal channel, a second end of the signal channel is connected to an input end of the first current mirror, a first mirror current output end of the first current mirror is connected to an input end of the inverter, a second mirror current output end of the first current mirror is connected to an input end of the second current mirror, the first current mirror is further connected to a negative power supply, a mirror current output end of the second current mirror is connected to the third current mirror, the second current mirror is further connected to ground, an input end of the third current mirror is connected to the negative power supply, a mirror current output end of the third current mirror is connected to the input end of the inverter, and the third current mirror is further connected to ground;

[0007] When no current is generated in the signal channel, the first current mirror does not output an image current, the second current mirror does not output an image current, the third current mirror outputs an image current, the input terminal of the inverter inputs the ground voltage, and the output terminal of the inverter outputs the negative power supply;

[0008] When current is generated in the signal channel, the first current mirror outputs an image current, the second current mirror outputs an image current, the third current mirror does not output an image current, the input terminal of the inverter inputs the negative power supply, and the output terminal of the inverter outputs the ground voltage.

[0009] In some embodiments, the signal channel includes:

[0010] A first resistor and a first transistor;

[0011] One end of the first resistor is used as the first end of the signal channel to input a level signal, the other end of the first resistor is connected to the source electrode of the first transistor, the drain electrode of the first transistor is used as the second end of the signal channel to be connected to the input terminal of the first current mirror, and the gate electrode of the first transistor is grounded.

[0012] In some embodiments, the signal channel further includes:

[0013] A second resistor; the first end of the second resistor is connected to the drain electrode of the first transistor, and the second end of the second resistor is used as the second end of the signal channel to be connected to the input terminal of the first current mirror.

[0014] In some embodiments, the signal channel further includes:

[0015] A diode; the anode of the diode is connected to the drain electrode of the first transistor, the cathode of the diode is connected to the first end of the second resistor, and the second end of the second resistor is used as the second end of the signal channel to be connected to the input terminal of the first current mirror.

[0016] In some embodiments, the first current mirror includes:

[0017] A second transistor, a third transistor, and a fourth transistor;

[0018] The drain of the second transistor is connected to the gate of the second transistor and serves as the input terminal of the first current mirror. The source of the second transistor is connected to the negative power supply. The gate of the third transistor is connected to the gate of the second transistor. The source of the third transistor is connected to the negative power supply. The drain of the third transistor serves as the first mirror current output terminal of the first current mirror. The gate of the fourth transistor is connected to the gate of the second transistor. The source of the fourth transistor is connected to the negative power supply. The drain of the fourth transistor serves as the second mirror current output terminal of the first current mirror.

[0019] In some embodiments, the second current mirror includes:

[0020] A fifth transistor and a sixth transistor. The drain of the fifth transistor is connected to the gate of the fifth transistor and serves as the input terminal of the second current mirror. The source of the fifth transistor is grounded. The gate of the sixth transistor is connected to the gate of the fifth transistor. The source of the sixth transistor is grounded. The drain of the sixth transistor serves as the mirror current output terminal of the second current mirror.

[0021] In some embodiments, the third current mirror includes:

[0022] A third resistor, a seventh transistor, and an eighth transistor;

[0023] The first end of the third resistor is connected to the negative power supply. The second end of the third resistor is connected to the drain of the seventh transistor. The gate of the seventh transistor is connected to the drain of the seventh transistor. The source of the seventh transistor is grounded. The gate of the eighth transistor is connected to the gate of the seventh transistor and the mirror current output terminal of the second current mirror. The drain of the eighth transistor is connected to the input terminal of the inverter. The source of the eighth transistor is grounded.

[0024] In some embodiments, the inverter includes:

[0025] A ninth transistor and a tenth transistor. The source of the ninth transistor is grounded. The gate of the ninth transistor is connected to the gate of the tenth transistor and serves as the input terminal of the inverter. The drain of the ninth transistor is connected to the drain of the tenth transistor and serves as the output terminal of the inverter. The source of the tenth transistor is connected to the negative power supply.

[0026] In some embodiments, the first transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are PMOS transistors, and the second transistor, the third transistor, the fourth transistor, and the tenth transistor are NMOS transistors.

[0027] To solve the above technical problems, the present application also provides a power supply device, including the level conversion circuit described above.

[0028] The level conversion circuit provided by the present application includes: a signal channel, a first current mirror, a second current mirror, a third current mirror, and an inverter; a level signal is input to the first end of the signal channel, the second end of the signal channel is connected to the input end of the first current mirror, the first mirror current output end of the first current mirror is connected to the input end of the inverter, the second mirror current output end of the first current mirror is connected to the input end of the second current mirror, the first current mirror is also connected to the negative power supply, the mirror current output end of the second current mirror is connected to the third current mirror, the second current mirror is also grounded, the input end of the third current mirror is connected to the negative power supply, the mirror current output end of the third current mirror is connected to the input end of the inverter, and the third current mirror is also connected to the ground; when no current is generated in the signal channel, the first current mirror does not output mirror current, the second current mirror does not output mirror current, the third current mirror outputs mirror current, the input end of the inverter inputs the ground voltage, and the output end of the inverter outputs the negative power supply; when current is generated in the signal channel, the first current mirror outputs mirror current, the second current mirror outputs mirror current, the third current mirror does not output mirror current, the input end of the inverter inputs the negative power supply, and the output end of the inverter outputs the ground voltage.

[0029] It can be seen that the level conversion circuit provided by the present application includes multiple current mirrors, relying on the pulling-up and pulling-down capabilities of the current mirrors and performing inversion through the inverter, can obtain faster conversion efficiency, and can achieve positive-to-negative conversion. At the same time, the level conversion circuit does not require an external positive power supply, and the positive voltage is provided by the level signal itself, which can reduce costs and the complexity of use.

[0030] The power supply device provided by the present application also has the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the prior art and the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0032] Figure 1 It is a schematic diagram of a level conversion circuit provided by an embodiment of the present application;

[0033] Figure 2 It is a schematic diagram of another level conversion circuit provided by an embodiment of the present application;

[0034] Figure 3 Schematic diagram of the simulation results of a level conversion circuit provided by an embodiment of the present application under PVT conditions;

[0035] Figure 4 Schematic diagram of the simulation results of another level conversion circuit provided by an embodiment of the present application under PVT conditions. Detailed implementation manners

[0036] The core of the present application is to provide a level conversion circuit and a power supply device, which have a high conversion rate, can achieve positive-to-negative conversion, and in addition, the level conversion circuit is powered by a single power supply, which can reduce the complexity in the actual application of the system and broaden the scope of use.

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0038] Please refer to Figure 1 , Figure 1 Schematic diagram of a level conversion circuit provided by an embodiment of the present application. Referring to Figure 1 as shown, the level conversion circuit includes:

[0039] Signal channel 10, first current mirror 20, second current mirror 30, third current mirror 40, and inverter 50;

[0040] The first end of the signal channel 10 inputs a level signal, the second end of the signal channel 10 is connected to the input end of the first current mirror 20, the first mirror current output end of the first current mirror 20 is connected to the input end of the inverter 50, the second mirror current output end of the first current mirror 20 is connected to the input end of the second current mirror 30, the first current mirror 20 is also connected to a negative power supply, the mirror current output end of the second current mirror 30 is connected to the third current mirror 40, the second current mirror 30 is also grounded, the input end of the third current mirror 40 is connected to the negative power supply, the mirror current output end of the third current mirror 40 is connected to the input end of the inverter 50, and the third current mirror 40 is also connected to ground;

[0041] When no current is generated in the signal channel 10, the first current mirror 20 does not output mirror current, the second current mirror 30 does not output mirror current, the third current mirror 40 outputs mirror current, the input end of the inverter 50 inputs a ground voltage, and the output end of the inverter 50 outputs a negative power supply;

[0042] When the signal channel 10 generates a current, the first current mirror 20 outputs a mirror current, the second current mirror 30 outputs a mirror current, the third current mirror 40 does not output a mirror current, the input terminal of the inverter 50 inputs a negative power supply, and the output terminal of the inverter 50 outputs a ground voltage.

[0043] In this embodiment, the level conversion circuit includes a signal channel 10, a first current mirror 20, a second current mirror 30, a third current mirror 40, and an inverter 50. Among them, the first end of the signal channel 10 is connected to an input level signal, and the level signal is a TTL (Transistor-Transistor Logic) signal. The second end of the signal channel 10 is connected to the input terminal of the first current mirror 20. When the signal channel 10 generates a current, there is a current at the input terminal of the first current mirror 20, and both the first mirror current output terminal and the second mirror current output terminal of the first current mirror 20 output mirror currents. When the signal channel 10 does not generate a current, there is no current at the input terminal of the first current mirror 20, and both the first mirror current output terminal and the second mirror current output terminal of the first current mirror 20 do not output mirror currents. Figure 1 Wherein VEE represents a negative power supply and GND represents ground.

[0044] In some embodiments, the signal channel 10 includes:

[0045] A first resistor R1 and a first transistor M1;

[0046] One end of the first resistor R1 serves as the first end of the signal channel 10 to input a level signal. The other end of the first resistor R1 is connected to the source of the first transistor M1. The drain of the first transistor M1 serves as the second end of the signal channel 10 and is connected to the input terminal of the first current mirror 20. The gate of the first transistor M1 is grounded.

[0047] The first resistor R1 plays a role in voltage division and can realize the adjustment of the level signal range. When the first transistor M1 is turned on, the signal channel 10 is turned on. Conversely, when the first transistor M1 is turned off, the signal channel 10 is turned off. If the level signal input to the signal channel 10 is lower than the threshold voltage of the first transistor M1, the first transistor M1 is turned off and the signal channel 10 does not generate a current. If the level signal input to the signal channel 10 is higher than the threshold voltage of the first transistor M1, the first transistor M1 is turned on and the signal channel 10 generates a current.

[0048] The TTL signal is input to the source of the first transistor M1, and the input detection range is determined by the threshold voltage of the first transistor M1, which greatly improves the detection range of the input voltage and expands the application environment of the level conversion circuit.

[0049] In some embodiments, the signal channel 10 further includes:

[0050] A second resistor R2; a first end of the second resistor R2 is connected to a drain of the first transistor M1, and a second end of the second resistor R2 serves as a second end of the signal channel 10 and is connected to an input end of the first current mirror 20.

[0051] The second resistor R2 functions as a current limiter and can control the magnitude of the current of the level signal.

[0052] In some embodiments, the signal channel 10 further includes:

[0053] A diode D; an anode of the diode D is connected to a drain of the first transistor M1, a cathode of the diode D is connected to a first end of the second resistor R2, and a second end of the second resistor R2 serves as a second end of the signal channel 10 and is connected to an input end of the first current mirror 20.

[0054] Reference Figure 2 As shown, in this embodiment, the signal channel 10 further includes a diode D. The diode D can prevent the first transistor M1 from being broken down due to a large voltage difference between the drain and the source during the conversion of the level signal, thereby improving the reliability of the circuit.

[0055] Reference Figure 2 As shown, in some embodiments, the first current mirror 20 includes:

[0056] A second transistor M2, a third transistor M3, and a fourth transistor M4;

[0057] A drain of the second transistor M2 is connected to a gate of the second transistor M2 and serves as an input end of the first current mirror 20, and a source of the second transistor M2 is connected to the negative power supply; a gate of the third transistor M3 is connected to the gate of the second transistor M2, a source of the third transistor M3 is connected to the negative power supply, and a drain of the third transistor M3 serves as a first mirror current output end of the first current mirror 20; a gate of the fourth transistor M4 is connected to the gate of the second transistor M2, a source of the fourth transistor M4 is connected to the negative power supply, and a drain of the fourth transistor M4 serves as a second mirror current output end of the first current mirror 20.

[0058] When no current is generated in the signal channel 10, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all in an off state, and the first current mirror 20 does not output a mirror current. When current is generated in the signal channel 10, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all turned on, and the third transistor M3 and the fourth transistor M4 output a mirror current by mirroring the current of the second transistor M2.

[0059] Reference Figure 2 As shown, in some embodiments, the second current mirror 30 includes:

[0060] A fifth transistor M5 and a sixth transistor M6; the drain of the fifth transistor M5 is connected to the gate of the fifth transistor M5 and serves as the input end of the second current mirror 30, and the source of the fifth transistor M5 is grounded; the gate of the sixth transistor M6 is connected to the gate of the fifth transistor M5, the source of the sixth transistor M6 is grounded, and the drain of the sixth transistor M6 serves as the mirror current output end of the second current mirror 30.

[0061] When no current is generated in the signal channel 10, the first current mirror 20 does not output current, and both the fifth transistor M5 and the sixth transistor M6 are turned off. When current is generated in the signal channel 10, the first current mirror 20 outputs current, the fifth transistor M5 and the sixth transistor M6 are turned on, and the sixth transistor M6 mirrors the current of the fifth transistor M5 and outputs a mirror current.

[0062] Reference Figure 2 As shown, in some embodiments, the third current mirror 40 includes:

[0063] A third resistor R3, a seventh transistor M7, and an eighth transistor M8;

[0064] The first end of the third resistor R3 is connected to the negative power supply, and the second end of the third resistor R3 is connected to the drain of the seventh transistor M7; the gate of the seventh transistor M7 is connected to the drain of the seventh transistor M7, the source of the seventh transistor M7 is grounded, the gate of the eighth transistor M8 is connected to the gate of the seventh transistor M7 and the mirror current output end of the second current mirror 30, the drain of the eighth transistor M8 is connected to the input end of the inverter 50, and the source of the eighth transistor M8 is grounded.

[0065] The seventh transistor M7 is always on, and there is current in the third resistor R3. When the second current mirror 30 does not output current, the eighth transistor M8 is on, and the drain of the eighth transistor M8 is pulled up to the ground voltage. At this time, the input end of the inverter 50 inputs the ground voltage, and after being inverted by the inverter 50, the inverter 50 outputs the negative power supply. When the second current mirror 30 outputs current, the gate of the eighth transistor M8 is pulled up to the ground voltage, the eighth transistor M8 is turned off, and at the same time, the drain of the eighth transistor M8 is pulled down to the negative power supply by the first mirror current output end of the first current mirror 20. At this time, the input end of the inverter 50 inputs the negative power supply, and after being inverted by the inverter 50, the inverter 50 outputs the ground voltage.

[0066] Reference Figure 2As shown, in some embodiments, the inverter 50 includes:

[0067] A ninth transistor M9 and a tenth transistor M10; the source of the ninth transistor M9 is grounded, the gate of the ninth transistor M9 is connected to the gate of the tenth transistor M10 and serves as the input terminal of the inverter 50, the drain of the ninth transistor M9 is connected to the drain of the tenth transistor M10 and serves as the output terminal of the inverter 50, and the source of the tenth transistor M10 is connected to the negative power supply.

[0068] In some embodiments, the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are PMOS transistors, and the second transistor M2, the third transistor M3, the fourth transistor M4, and the tenth transistor M10 are NMOS transistors.

[0069] Among them, the first transistor M1 can use a PMOS transistor with a smaller channel length to improve the switching speed.

[0070] Reference Figure 2 As shown, the working principle of the level conversion circuit described below is as follows: Figure 2 As shown, the working principle of the level conversion circuit:

[0071] When the TTL signal is lower than the threshold voltage of the first transistor M1, the first transistor M1 is turned off, no current is generated on the signal path 10, and the second transistor M2, the third transistor M3, and the fourth transistor M4 are all in the off state, and no current is generated in the first current mirror 20 composed of the second transistor M2, the third transistor M3, and the fourth transistor M4. Since no current is generated in the fourth transistor M4, the sixth transistor M6 is turned off and has no pull-up ability. Since there is current in the seventh transistor M7, the eighth transistor M8 is turned on, and the drain of the eighth transistor M8 is pulled up to GND. Through the inverter 50 composed of the ninth transistor M9 and the tenth transistor M10, the output of the inverter 50 is VEE.

[0072] When the TTL signal is higher than the threshold voltage of the first transistor M1, the first transistor M1 is turned on, and the high-level signal is transmitted to the drain of the second transistor M2 through the first resistor R1, the first transistor M1, the diode D, and the second resistor R2, and current is generated on the signal path 10. At this time, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all in the on state, and the fourth transistor M4 mirrors the current of the second transistor M2, making the voltage at the gate of the sixth transistor M6 lower, and the sixth transistor M6 is turned on, generating a pull-up ability, making the gate of the eighth transistor M8 pulled high, the eighth transistor M8 is turned off, and the drain is pulled down to VEE by the third transistor M3. Through the inverter 50 composed of M9 and M10, the output of the inverter 50 is GND.

[0073] When the TTL signal is at a high level, the gate of the eighth transistor M8 is affected by the pull-up of the sixth transistor M6 and also by the pull-down of the third resistor R3. Therefore, under PVT (Process, Voltage, Temperature) conditions, it is necessary to reasonably configure the pull-up ability of the sixth transistor M6 and the pull-down ability of the third resistor R3.

[0074] When the TTL signal changes from low to high, the third transistor M3 has a pull-down ability and the eighth transistor M8 has a pull-up ability, which will slow down the speed at which the drain of the third transistor M3 is pulled down and reduce the system conversion rate. And when the third transistor M3 and the eighth transistor M8 are turned on simultaneously, a large current will be generated. In view of this, in this embodiment, the sixth transistor M6 is provided. Through the sixth transistor M6, the eighth transistor M8 can be quickly turned off, so that the drain of the third transistor M3 can be quickly pulled down, improving the system conversion rate while avoiding a large current generated by the simultaneous conduction of the third transistor M3 and the eighth transistor M8.

[0075] Figure 3 、 Figure 4 This is the simulation result of the level conversion circuit provided by the embodiment of the present application under PVT conditions, which can achieve an input low level of 0~0.8V and an input high level of 2.0~5.0V. When the input is 2.0V, the maximum conversion frequency is 34MHz, and the TTL input current and the maximum conversion frequency increase with the increase of the input voltage.

[0076] Reference Figure 3 As shown, when simulating at a TTL input frequency of 10MHz under the conditions of VEE±10% and -55~125°C, the signal is converted from 0~5V to 0~-5V. Combining the process corner, the conversion time under the worst conditions is 11ns, and the TTL input current is 151uA.

[0077] Reference Figure 4 As shown, when simulating at a TTL input frequency of 10MHz under the conditions of VEE±10% and -55~125°C, the signal is converted from 0.8~2.0V to 0~-5V. Combining the process corner, the conversion time under the worst conditions is 29ns, and the TTL input current is 90uA.

[0078] In summary, the level conversion circuit provided by the present application includes multiple current mirrors, relies on the pull-up and pull-down abilities of the current mirrors and performs inversion through an inverter, can obtain faster conversion efficiency, and can achieve positive-to-negative conversion. At the same time, the level conversion circuit does not need to provide a positive power supply externally, and the positive voltage is provided by the level signal itself, which can reduce costs and the complexity of use.

[0079] The present application also provides a power supply device, which includes the level conversion circuit as described in the above embodiments. For the power supply device provided by the present application, reference may be made to the embodiments of the above level conversion circuit, which will not be elaborated herein.

[0080] Due to the complex situation, it is impossible to list and elaborate one by one. Those skilled in the art should be able to realize that under the basic principle of the embodiments provided by the present application, multiple examples may exist in combination with the actual situation. Without sufficient creative labor, they should all fall within the scope of the present application.

[0081] The various embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0082] The above has introduced the level conversion circuit and the power supply device provided by the present application in detail. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0083] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the element.

Claims

1. A level conversion circuit, characterized in that, Including: A signal channel, a first current mirror, a second current mirror, a third current mirror, and an inverter; A level signal is input at the first end of the signal channel. The second end of the signal channel is connected to the input end of the first current mirror. The first mirror current output end of the first current mirror is connected to the input end of the inverter. The second mirror current output end of the first current mirror is connected to the input end of the second current mirror. The first current mirror is also connected to the negative power supply. The mirror current output end of the second current mirror is connected to the third current mirror. The second current mirror is also grounded. The input end of the third current mirror is connected to the negative power supply. The mirror current output end of the third current mirror is connected to the input end of the inverter. The third current mirror is also connected to the ground; When no current is generated in the signal channel, the first current mirror does not output mirror current, the second current mirror does not output mirror current, the third current mirror outputs mirror current, the input end of the inverter inputs the ground voltage, and the output end of the inverter outputs the negative power supply; When current is generated in the signal channel, the first current mirror outputs mirror current, the second current mirror outputs mirror current, the third current mirror does not output mirror current, the input end of the inverter inputs the negative power supply, and the output end of the inverter outputs the ground voltage.

2. The level conversion circuit according to claim 1, wherein The signal channel includes: A first resistor and a first transistor; One end of the first resistor is used as the first end of the signal channel to input the level signal. The other end of the first resistor is connected to the source of the first transistor. The drain of the first transistor is used as the second end of the signal channel and is connected to the input end of the first current mirror. The gate of the first transistor is grounded.

3. The level conversion circuit according to claim 2, characterized in that The signal channel further includes: A second resistor; the first end of the second resistor is connected to the drain of the first transistor, and the second end of the second resistor is used as the second end of the signal channel and is connected to the input end of the first current mirror.

4. The level conversion circuit according to claim 3, wherein The signal channel further includes: A diode; the anode of the diode is connected to the drain of the first transistor, the cathode of the diode is connected to the first end of the second resistor, and the second end of the second resistor is used as the second end of the signal channel and is connected to the input end of the first current mirror.

5. The level conversion circuit according to claim 1, characterized in that The first current mirror includes: A second transistor, a third transistor, and a fourth transistor; The drain of the second transistor is connected to the gate of the second transistor and serves as the input end of the first current mirror. The source of the second transistor is connected to the negative power supply. The gate of the third transistor is connected to the gate of the second transistor. The source of the third transistor is connected to the negative power supply. The drain of the third transistor serves as the first mirror current output end of the first current mirror. The gate of the fourth transistor is connected to the gate of the second transistor. The source of the fourth transistor is connected to the negative power supply. The drain of the fourth transistor serves as the second mirror current output end of the first current mirror.

6. The level conversion circuit according to claim 1, wherein The second current mirror includes: The fifth transistor and the sixth transistor; the drain of the fifth transistor is connected to the gate of the fifth transistor and serves as the input terminal of the second current mirror, and the source of the fifth transistor is grounded; the gate of the sixth transistor is connected to the gate of the fifth transistor, the source of the sixth transistor is grounded, and the drain of the sixth transistor serves as the output terminal of the mirror current of the second current mirror.

7. The level conversion circuit according to claim 1, characterized in that, The third current mirror includes: A third resistor, a seventh transistor, and an eighth transistor; The first end of the third resistor is connected to the negative power supply, and the second end of the third resistor is connected to the drain of the seventh transistor; the gate of the seventh transistor is connected to the drain of the seventh transistor, the source of the seventh transistor is grounded, the gate of the eighth transistor is connected to the gate of the seventh transistor and the output terminal of the mirror current of the second current mirror, the drain of the eighth transistor is connected to the input terminal of the inverter, and the source of the eighth transistor is grounded.

8. The level conversion circuit according to claim 7, wherein The inverter includes: A ninth transistor and a tenth transistor; the source of the ninth transistor is grounded, the gate of the ninth transistor is connected to the gate of the tenth transistor and serves as the input terminal of the inverter, the drain of the ninth transistor is connected to the drain of the tenth transistor and serves as the output terminal of the inverter, and the source of the tenth transistor is connected to the negative power supply.

9. The level conversion circuit according to claim 8, wherein The first transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are PMOS transistors, and the second transistor, the third transistor, the fourth transistor, and the tenth transistor are NMOS transistors.

10. A power supply device, characterized in that, Comprising the level conversion circuit according to any one of claims 1 to 9.

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