Integrated longitudinal high-voltage device

Abstract

The utility model discloses an integratable longitudinal high-voltage device. The integratable longitudinal high-voltage device comprises an N-type substrate; the first N-type epitaxial layer is positioned above the N-type substrate; the first P well region is located on the first N-type epitaxial layer; the second N-type epitaxial layer is positioned above the first N-type epitaxial layer; the second P well region is located on the second N-type epitaxial layer and located above the first P well region; the gate trench is positioned on the second N-type epitaxial layer without the second P well region; a longitudinal gate oxide layer and a longitudinal polysilicon gate are arranged in the gate trench; the longitudinal body region is also positioned on the second N-type epitaxial layer which is not provided with the second P well region; the longitudinal body region is provided with a longitudinal source region, a heavy doping region and a body light doping region; and the planar device is located in the second P well region and located on the upper surface of the second P well region. By adopting the technical scheme, the reliability of the device can be improved, and the integration of a large-area power output tube is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a vertical high-voltage device. Background Art

[0002] In the field of high-voltage integrated circuits, it is often necessary to integrate a large-area power output transistor and ordinary complementary metal oxide semiconductor (CMOS) devices. In the traditional BCD (Bipolar-CMOS-DMOS) process, the large-area power transistor is completed by using a planar laterally diffused metal oxide semiconductor (LDMOS) device. However, for the LDMOS device, especially as the voltage increases, the area of this device will increase sharply, resulting in a sharp decline in the performance-price ratio of the device under high voltage. At the same time, the poor reliability of the high-voltage LDMOS has also been restricting the continuous development of the high-voltage BCD process.

[0003] In the existing method, a vertical high-voltage device is also used for the power transistor, that is, the drain of the LDMOS is arranged on the back of the chip to reduce the device area and improve the utilization rate of the chip. The substrate of the chip is generally silicon with extremely low resistance. It is necessary to epitaxially grow a certain thickness of high-resistance silicon on the substrate, and form a gate deep trench on the epitaxial high-resistance silicon, and fill the polysilicon trench gate to form a vertical device. A deep well can be implanted in the vertical high-voltage device to isolate the high-voltage device and the planar CMOS device, so as to integrate the CMOS device into the vertical high-voltage device, and complete the vertical high-voltage device and the planar CMOS device at the same time, realizing the high-voltage BCD process.

[0004] However, in order to form a deep trench gate structure and ensure the breakdown voltage value of the vertical high-voltage device, it is necessary to set a relatively large thickness of the epitaxial high-resistance silicon, which will lead to great difficulty in deep well implantation and it is difficult to achieve deep well implantation with a relatively large depth. If the implantation depth is shallower than the epitaxial high-resistance silicon, it is not conducive to device integration. If a relatively small thickness of the epitaxial high-resistance silicon is set to meet device integration, the required breakdown voltage value cannot be satisfied. Summary of the Utility Model

[0005] The utility model provides a vertical high-voltage device to improve the reliability of the voltage device and realize the integration of a large-area power output transistor.

[0006] According to one aspect of the utility model, there is provided an integrable vertical high-voltage device, comprising:

[0007] An N-type substrate;

[0008] A first N-type epitaxial layer, located above the N-type substrate;

[0009] The first P-well region is located in the first N-type epitaxial layer;

[0010] The second N-type epitaxial layer is located above the first N-type epitaxial layer;

[0011] The second P-well region is located in the second N-type epitaxial layer and above the first P-well region;

[0012] The gate trench is located in the second N-type epitaxial layer where the second P-well region is not provided; a longitudinal gate oxide layer and a longitudinal polysilicon gate are provided in the gate trench, and the longitudinal gate oxide layer wraps the longitudinal polysilicon gate;

[0013] The longitudinal body region is also located in the second N-type epitaxial layer where the second P-well region is not provided; the longitudinal body region is adjacent to the gate trench in the horizontal direction; wherein, the longitudinal body region is provided with a longitudinal source region, a heavily doped body region and a lightly doped body region, the heavily doped body region, the longitudinal source region and the gate trench are adjacent to each other in the horizontal direction in sequence, and the lightly doped body region is located below the heavily doped body region and the longitudinal source region;

[0014] The planar device is located in the second P-well region and on the upper surface of the second P-well region; wherein, the planar device includes an LDMOS transistor and / or a CMOS device.

[0015] Optionally, the planar device includes the LDMOS transistor and the CMOS device;

[0016] The LDMOS transistor and the CMOS device are respectively located in different second P-well regions, and different second P-well regions are respectively located above different first P-well regions;

[0017] In the horizontal direction, device shallow trench isolation is provided between any two of the longitudinal high-voltage device, the LDMOS transistor and the CMOS device.

[0018] Optionally, a drain region is provided in the second N-type epitaxial layer where the second P-well region is not provided; the drain region penetrates through the second N-type epitaxial layer and the first N-type epitaxial layer and is connected to the N-type substrate;

[0019] Wherein, at least part of the first P-well region and the second P-well region above it are located between the drain region and the longitudinal high-voltage device.

[0020] Optionally, the drain region includes a deep N-well region;

[0021] Alternatively, the drain region includes a deep drain trench and N-type polysilicon located in the deep drain trench;

[0022] Alternatively, the leakage region includes a deep leakage trench and a conductive metal structure located within the deep leakage trench.

[0023] Optionally, it further includes: a P-type substrate;

[0024] The P-type substrate is located below the N-type substrate.

[0025] Optionally, the planar device includes the LDMOS transistor;

[0026] The LDMOS transistor includes a lateral drift region and a lateral body region located in the second P-well region;

[0027] The LDMOS transistor further includes a lateral leakage region located in the lateral drift region, a lateral source region located in the lateral body region, and a lateral polysilicon gate at least partially located between the lateral drift region and the lateral body region and above the second P-well region.

[0028] Optionally, the LDMOS transistor further includes a lateral shallow trench isolation located above the lateral drift region;

[0029] The lateral shallow trench isolation is located on a side of the lateral leakage region close to the lateral body region, and the lateral shallow trench isolation is adjacent to the lateral leakage region in the horizontal direction;

[0030] In the vertical direction, the depth of the lateral shallow trench isolation is greater than or equal to the depth of the lateral leakage region.

[0031] Optionally, the planar device includes the CMOS device;

[0032] The CMOS device includes a P-type body region, an N-type body region located in the second P-well region, an NMOS region located in the P-type body region, and a PMOS region located in the N-type body region;

[0033] The NMOS region includes two N-type heavily doped regions, and there is a first gap between the two N-type heavily doped regions; a first gate oxide layer and a first polysilicon gate are disposed above the first gap, wherein the first polysilicon gate is located above the first gate oxide layer;

[0034] The PMOS region includes two P-type heavily doped regions, and there is a second gap between the two P-type heavily doped regions; a second gate oxide layer and a second polysilicon gate are disposed above the second gap, wherein the second polysilicon gate is located above the second gate oxide layer.

[0035] Optionally, the P-type body region further includes a heavily doped P-type region, which is located on a side of one of the N-type heavily doped regions in the NMOS region away from the first spacer, and a first shallow trench isolation is provided between the heavily doped P-type region and the N-type heavily doped region;

[0036] The N-type body region further includes a heavily doped N-type region, which is located on a side of one of the P-type heavily doped regions in the PMOS region away from the second spacer, and a second shallow trench isolation is provided between the heavily doped N-type region and the P-type heavily doped region;

[0037] The CMOS device further includes a third shallow trench isolation located between the P-type body region and the N-type body region.

[0038] The technical solution of the present utility model is beneficial to saving the space of signal traces and reducing the lateral space by providing a vertical high-voltage device. At the same time, it is also beneficial to reducing the on-resistance; by providing a first N-type epitaxial layer and a second N-type epitaxial layer above the N-type substrate, and providing a first P-well region in the first N-type epitaxial layer and a second P-well region in the second N-type epitaxial layer above the first P-well region, epitaxy can be carried out in two times to respectively form the first N-type epitaxial layer and the second N-type epitaxial layer, and ion implantation can be carried out respectively after each epitaxy, that is, implanted in two times to respectively form the first P-well region and the second P-well region, so as to reduce the difficulty of deep well implantation, realize deep well implantation with a larger depth, be beneficial to the integration of planar devices, and at the same time, realize a higher breakdown voltage value; in addition, the first P-well region and the second P-well region can not only isolate the vertical high-voltage device and the planar device, but also serve as the substrate of the planar device, and planar devices are fabricated in the second P-well region, so as to facilitate the integration of devices and improve the integration degree.

[0039] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present utility model, nor is it used to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present utility model, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0041] Figure 1 is a schematic structural diagram of an integrable vertical high-voltage device provided by an embodiment of the present utility model;

[0042] Figure 2It is a partial structural schematic diagram of another integrated vertical high-voltage device provided by an embodiment of the present invention;

[0043] Figure 3 It is a structural schematic diagram of another integrated vertical high-voltage device provided by an embodiment of the present invention;

[0044] Figure 4 It is a structural schematic diagram of another integrated vertical high-voltage device provided by an embodiment of the present invention;

[0045] Figure 5 It is a structural schematic diagram of another integrated vertical high-voltage device provided by an embodiment of the present invention;

[0046] Figure 6 It is a circuit structural schematic diagram of a CMOS device provided by an embodiment of the present invention;

[0047] Figure 7 It is a flowchart of a preparation method of an integrated vertical high-voltage device provided by an embodiment of the present invention;

[0048] Figure 8 It is a structural schematic diagram of a preparation process of an integrated vertical high-voltage device provided by an embodiment of the present invention

[0049] Figure 9 It is a structural schematic diagram of a preparation process of a device in an integrated vertical high-voltage device provided by an embodiment of the present invention;

[0050] Figure 10 It is a structural schematic diagram of a preparation process of another integrated vertical high-voltage device provided by an embodiment of the present invention;

[0051] Figure 11 It is a structural schematic diagram of a preparation process of a device in another integrated vertical high-voltage device provided by an embodiment of the present invention;

[0052] In the figure:

[0053] 01 - N-type substrate, 02 - P-type substrate, 11 - first N-type epitaxial layer, 12 - second N-type epitaxial layer, 20 - deep P-well region, 21 - first P-well region, 22 - second P-well region, 231 - P-type well heavily doped region, 31 - vertical gate oxide layer, 32 - vertical polysilicon gate, 40 - vertical body region, 41 - body heavily doped region, 42 - body lightly doped region, 50 - vertical source region, 60 - drain region, 61 - deep N-well region, 611 - first N-well region, 612 - second N-well region, 62 - N-type well heavily doped region, 700 - LDMOS transistor, 710 - lateral drift region, 720 - lateral body region, 730 - lateral drain region, 740 - lateral source region, 750 - lateral body heavily doped region, 761 - lateral gate oxide layer, 762 - lateral polysilicon gate, 800 - CMOS device, 810 - NMOS region, 811 - first gate oxide layer, 812 - first polysilicon gate, 820 - PMOS region, 821 - second polysilicon gate, 822 - second polysilicon gate. Detailed implementation manners

[0054] In order to enable those skilled in the art to better understand the solution of the present utility model, the technical solutions in the embodiments of the present utility model will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present utility model.

[0055] It should be noted that the terms "first", "second", etc. in the specification and claims of the present utility model and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0056] Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the protection scope of the present utility model. The technical solutions in the embodiments of the present utility model will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present utility model.

[0057] Figure 1It is a schematic structural diagram of an integrable vertical high-voltage device provided by an embodiment of the present invention. Refer to Figure 1 , the integrable vertical high-voltage device includes:

[0058] An N-type substrate 01;

[0059] A first N-type epitaxial layer 11, located above the N-type substrate 01;

[0060] A first P-well region 21, located in the first N-type epitaxial layer 11;

[0061] A second N-type epitaxial layer 12, located above the first N-type epitaxial layer 11;

[0062] A second P-well region 22, located in the second N-type epitaxial layer 12 and above the first P-well region 21;

[0063] A gate trench GT, located in the second N-type epitaxial layer 12 where the second P-well region 22 is not provided; a vertical gate oxide layer 31 and a vertical polysilicon gate 32 are provided in the gate trench GT, and the vertical gate oxide layer 31 wraps the vertical polysilicon gate 32;

[0064] A vertical body region 40 is also located in the second N-type epitaxial layer 12 where the second P-well region 22 is not provided; the vertical body region 40 is adjacent to the gate trench GT in the horizontal direction; wherein, the vertical body region 40 is provided with a vertical source region 50, a body heavily doped region 41 and a body lightly doped region 42, the body heavily doped region 41, the vertical source region 50 and the gate trench GT are adjacent to each other in the horizontal direction in sequence, and the body lightly doped region 42 is located below the body heavily doped region 41 and the vertical source region 50;

[0065] A planar device PLD, located in the second P-well region 22 and on the upper surface of the second P-well region 22; wherein, the planar device PLD includes an LDMOS transistor 700 and / or a CMOS device 800.

[0066] Wherein, above the N-type substrate 01 refers to the direction on the side for fabricating the device, and below is the opposite direction; the horizontal direction refers to the direction parallel to the plane where the N-type substrate 01 is located, and can also be called the transverse direction; the vertical direction refers to the direction perpendicular to the plane where the N-type substrate 01 is located, and can also be called the longitudinal direction.

[0067] The N-type substrate 01 is a low-resistance substrate. For example, the resistivity of the N-type substrate 01 can be 1.15 ± 0.01 mΩ·cm. The first N-type epitaxial layer 11 and the second N-type epitaxial layer 12 are semiconductor layers with higher resistance and have a certain thickness. For example, the sum of the thicknesses of the first N-type epitaxial layer 11 and the second N-type epitaxial layer 12 can be 5 ± 0.1 μm to ensure that the integrable vertical high-voltage device has a higher breakdown voltage value.

[0068] Specifically, the first P-well region 21 is formed in the first N-type epitaxial layer 11, and the first P-well region 21 can be formed by the ion implantation direction before forming the second N-type epitaxial layer 12; the second P-well region 22 is formed in the second N-type epitaxial layer 12, and the second P-well region 22 can be formed by the ion implantation direction after forming the second N-type epitaxial layer 12; the first P-well region 21 and the second P-well region 22 arranged vertically and connected to each other constitute a deep P-well region 20.

[0069] The integrable vertical high-voltage device represents the integration of the vertical high-voltage device 100 and the planar device PLD. The vertical high-voltage device 100 and the planar device PLD are arranged horizontally. The vertical high-voltage device 100 is disposed in the second N-type epitaxial layer 12 where the second P-well region 22 is not provided, and the planar device PLD is disposed in the second P-well region 22. The vertical high-voltage device 100 includes a vertical gate oxide layer 31, a vertical polysilicon gate 32, a vertical body region 40, and a vertical source region 50. A vertical conductive channel can be formed between the vertical high-voltage device 100 and the N-type substrate 01; the planar device PLD can form a horizontal conductive channel. The deep P-well region 20 can isolate the vertical conductive channel of the vertical high-voltage device 100 and the horizontal conductive channel of the planar device PLD. The deep P-well region 20 can not only isolate the vertical high-voltage device 100 and the planar device PLD, but also serve as the substrate of the planar device PLD. The planar device PLD is fabricated in the deep P-well region 20 to facilitate device integration.

[0070] Exemplarily, continuing to refer to Figure 1 Taking the vertical high-voltage device 100 as an NMOS transistor as an example, the first N-type epitaxial layer 11 and the second N-type epitaxial layer 12 under the vertical high-voltage device 100 can serve as the N-type drift region. The vertical source region 50 can include an N-type heavily doped region N+, the body lightly doped region 42 can include a P-type lightly doped region PB, and the body heavily doped region 41 can include a P-type heavily doped region P+. The vertical high-voltage device 100 can further include a gate 101, a source 102, and a body 103. The gate 101 is in contact connection with the vertical polysilicon gate 32, the source 102 is in contact connection with the vertical source region 50, and the body 103 is in contact connection with the body heavily doped region 41. In an alternative embodiment, the source 102 can be electrically connected to the body 103; the drain 104 of the vertical high-voltage device 100 is disposed below the N-type substrate 01, and the drain 104 is in contact connection with the N-type substrate 01. When a positive voltage is applied between the drain 104 and the source 102, and the voltage between the gate 101 and the source 102 is greater than the threshold voltage, a vertical N-type channel can be formed and conduct in the N-type drift region, and the current flows from the N-type substrate 01 to the vertical source region 50.

[0071] The electrodes of the planar device PLD can all be located above the second P-well region 22 (not shown in the figure). When corresponding voltages are applied to the electrodes of the planar device PLD, a lateral conduction channel can be formed and conducted in the planar device PLD, and the current of the planar device PLD can flow in the same second P-well region 22.

[0072] It should be noted that only two deep P-well regions 20 that can be integrated are exemplarily shown in the figure, and they are respectively located on both sides of the vertical high-voltage device 100. In other alternative embodiments, the vertically integrated high-voltage device may include one or more deep P-well regions 20. All the deep P-well regions 20 can be located on the same side of the vertical high-voltage device 100, or at least some of the deep P-well regions 20 can be located on different sides of the vertical high-voltage device 100.

[0073] It should also be noted that only one gate trench GT and the internal vertical gate oxide layer 31 and vertical polysilicon gate 32 are exemplarily shown in the vertical high-voltage device 100 in the figure. In other alternative embodiments, the vertical high-voltage device 100 may include multiple gate trenches GT and the internal vertical gate oxide layer 31 and vertical polysilicon gate 32, as Figure 2 shown.

[0074] In the embodiment of the present utility model, by providing the vertical high-voltage device, it is beneficial to save the space for signal routing, reduce the lateral space, and at the same time, it is also beneficial to reduce the on-resistance; by providing the first N-type epitaxial layer and the second N-type epitaxial layer above the N-type substrate, and by providing the first P-well region in the first N-type epitaxial layer and the second P-well region in the second N-type epitaxial layer above the first P-well region, epitaxy can be carried out in two steps to respectively form the first N-type epitaxial layer and the second N-type epitaxial layer, and ion implantation can also be carried out respectively after each epitaxy, that is, ion implantation is carried out in two steps to respectively form the first P-well region and the second P-well region, so as to reduce the difficulty of deep well implantation, achieve deep well implantation with a larger depth, be beneficial to the integration of planar devices, and at the same time, achieve a higher breakdown voltage value; in addition, the first P-well region and the second P-well region can not only isolate the vertical high-voltage device and the planar device, but also serve as the substrate of the planar device, and a planar device is fabricated in the second P-well region, so as to facilitate the integration of devices and improve the integration degree.

[0075] Optionally, continuing to refer to Figure 1 , the planar device PLD includes an LDMOS transistor 700 and a CMOS device 800; the LDMOS transistor 700 and the CMOS device 800 are respectively located in different second P-well regions 22, and the different second P-well regions 22 are respectively located above different first P-well regions 21; along the horizontal direction, a device shallow trench isolation D-STI is provided between any two of the vertical high-voltage device 100, the LDMOS transistor 700, and the CMOS device 800.

[0076] Among them, the device shallow trench isolation D-STI includes, but is not limited to, insulating materials such as silicon oxide materials. The device shallow trench isolation D-STI can be formed by etching an isolation groove and filling the isolation groove with an insulating material, or can be formed by a local oxidation process. The embodiments of the present invention do not limit this.

[0077] Exemplarily, a first P-well region 21 and a second P-well region 22 arranged vertically and connected form a deep P-well region 20. A device is disposed near each deep P-well region 20. Between different devices or between different deep P-well regions 20, device shallow trench isolation D-STI is provided to prevent leakage current from occurring between different devices or different deep P-well regions 20.

[0078] It should be noted that only two deep P-well regions 20 of the integratable vertical high-voltage devices are exemplarily shown in the figure. The planar device PLD in one deep P-well region 20 may include an LDMOS transistor 700, and the planar device PLD in the other deep P-well region 20 may include a CMOS device 800. In other alternative embodiments, the planar device PLD of all deep P-well regions 20 may all include an LDMOS transistor 700, or the planar device PLD of all deep P-well regions 20 may also all include a CMOS device 800. In an alternative implementation manner, the LDMOS transistor 700 is a high-voltage device, and the CMOS device 800 is a low-voltage device.

[0079] In an alternative embodiment, a P-type well heavily doped region 231 is provided on the upper surface of the second P-well region 22. In this way, it is beneficial to control the potentials of the second P-well region 22 and the first P-well region 21, block the signal interference of the vertical high-voltage device 100, and improve the reliability of the planar device PLD.

[0080] Optionally, Figure 3 is a schematic structural diagram of another integratable vertical high-voltage device provided by the embodiments of the present invention. Refer to Figure 3 , a drain region 60 is provided in the second N-type epitaxial layer 12 where the second P-well region 22 is not provided; the drain region 60 penetrates through the second N-type epitaxial layer 12 and the first N-type epitaxial layer 11 and is connected to the N-type substrate 01. Among them, at least part of the first P-well region 21 and the second P-well region 22 above it are located between the drain region 60 and the vertical high-voltage device 100.

[0081] Specifically, the leakage region 60 is electrically connected to the N-type substrate 01, and the drain 104 of the vertical high-voltage device 100 can be led out to the front surface of the chip, that is, the upper surface of the second N-type epitaxial layer 12. In this way, during measurement, it is not necessary to thin the N-type substrate 01 and sputter thick metal on the lower surface of the N-type substrate 01 to form the drain 104. When the drain 104 is led out to the front surface of the chip, the drain 104 of the vertical high-voltage device 100 can be formed in the same process as the gate 101, the source 102, and the body 103, which is beneficial to simplifying the process, improving the yield and production efficiency, and reducing the production cost. At least one deep P-well region 20 is located between the leakage region 60 and the vertical high-voltage device 100. The deep P-well region 20 can be used as an isolation structure between the leakage region 60 and the vertical high-voltage device 100 to prevent the electrical signal of the leakage region 60 from interfering with the vertical channel between the vertical high-voltage device 100 and the N-type substrate 01; at the same time, the deep P-well region 20 can also be used as the substrate of the planar device PLD to form the planar device PLD, which is beneficial to the integration of the planar device PLD and the vertical high-voltage device 100 and improves the utilization rate of the chip.

[0082] In an optional embodiment, continue to refer to Figure 3 , the leakage region 60 includes a deep N-well region 61.

[0083] Exemplarily, the deep N-well region 61 includes a first N-well region 611 and a second N-well region 612. The first N-well region 611 is located in the first N-type epitaxial layer 11, and the second N-well region 612 is located in the second N-type epitaxial layer 12. The first N-well region 611 and the second N-well region 612 are arranged and connected in the vertical direction. The first N-well region 611 can be formed by ion implantation before the formation of the second N-type epitaxial layer 12, and the second N-well region 612 can be formed by ion implantation after the formation of the second N-type epitaxial layer 12.

[0084] In an optional implementation manner, the leakage region 60 further includes an N-well heavily doped region 62, and the N-well heavily doped region 62 is disposed on the upper surface of the second N-well region 612.

[0085] In yet another optional embodiment, Figure 4 is a schematic structural diagram of another integrable vertical high-voltage device provided by an embodiment of the present invention. Refer to Figure 4 , the leakage region 60 includes a deep drain trench DT and an N-type polysilicon N-poly or a conductive metal structure Metal located in the deep drain trench DT. In this way, a vertical high-voltage device 100 with a lower on-resistance can be obtained.

[0086] Optionally, refer to Figure 3 and Figure 4 , the integrable vertical high-voltage device further includes a P-type substrate 02, and the P-type substrate 02 is located below the N-type substrate 01.

[0087] Exemplarily, in practical applications, the N-type substrate 01 is at a high potential, the vertical polysilicon gate 32 is at a low potential, the P-type substrate 02 can be at zero potential, and the N-type substrate 01 and the P-type substrate 02 can form a reverse bias to avoid device leakage current.

[0088] Optionally, Figure 5 is a schematic structural diagram of another integrated vertical high-voltage device provided by an embodiment of the present invention. Refer to Figure 5 , the planar device PLD includes an LDMOS transistor 700; the LDMOS transistor 700 includes a lateral drift region 710 and a lateral body region 720 located in the second P-well region 22; the LDMOS transistor 700 further includes a lateral drain region 730 located in the lateral drift region 710, a lateral source region 740 located in the lateral body region 720, and a lateral gate oxide layer 761 and a lateral polysilicon gate 762 at least partially located between the lateral drift region 710 and the lateral body region 720 and above the second P-well region 22, wherein the lateral polysilicon gate 762 is located above the lateral gate oxide layer 761.

[0089] Exemplarily, taking the LDMOS transistor 700 as an NMOS transistor as an example, the lateral drift region 710 may include an N-type drift region NDD, the lateral body region 720 may include a P-type well PW, the lateral drain region 730 may include an N-type heavily doped region N+, and the lateral source region 740 may include an N-type heavily doped region N+. The LDMOS transistor 700 further includes a lateral body heavily doped region 750 located in the lateral body region 720, and the lateral body heavily doped region 750 may include a P-type heavily doped region P+. When a positive voltage is applied between the lateral drain region 730 and the lateral source region 740, and the voltage between the lateral polysilicon gate 762 and the lateral source region 740 is greater than the threshold voltage, a lateral N-type channel can be formed and turned on in the second P-well region 22 under the lateral gate oxide layer 761 and the lateral polysilicon gate 762, and the current flows from the lateral drain region 730 to the lateral source region 740.

[0090] Based on the above embodiment, the LDMOS transistor 700 may further include a lateral shallow trench isolation L-STI located above the lateral drift region 710; the lateral shallow trench isolation L-STI is located on one side of the lateral drain region 730 close to the lateral body region 720, and the lateral shallow trench isolation L-STI is adjacent to the lateral drain region 730 in the horizontal direction; in the vertical direction, the depth of the lateral shallow trench isolation L-STI is greater than or equal to the depth of the lateral drain region 730. Herein, the depth refers to the distance extending from the surface towards the N-type substrate 01 in the vertical direction. The lateral shallow trench isolation L-STI includes, but is not limited to, silicon oxide material.

[0091] Optionally, continue to refer to Figure 5, The planar device includes a CMOS device 800; the CMOS device 800 includes a P-type body region P-body and an N-type body region N-body located in the second P-well region, an NMOS region 810 located in the P-type body region P-body, and a PMOS region 820 located in the N-type body region N-body; the NMOS region 810 includes two N-type heavily doped regions N+, and there is a first gap between the two N-type heavily doped regions N+; a first gate oxide layer 811 and a first polysilicon gate 812 are disposed above the first gap, wherein the first polysilicon gate 812 is located above the first gate oxide layer 811; the PMOS region 820 includes two P-type heavily doped regions P+, and there is a second gap between the two P-type heavily doped regions P+; a second gate oxide layer 821 and a second polysilicon gate 822 are disposed above the second gap, wherein the second polysilicon gate 821 is located above the second gate oxide layer 821.

[0092] Exemplarily, Figure 6 is a schematic circuit diagram of a CMOS device provided by an embodiment of the present invention. Referring to Figure 5 and Figure 6 , the two N-type heavily doped regions of the NMOS region 810 can be respectively connected to the source and the drain, and the two P-type heavily doped regions P+ of the PMOS region 820 can also be respectively connected to the source and the drain. The source of the NMOS region 810 can be connected to a low potential, for example, it can be grounded, and the source of the PMOS region 820 can be connected to a high potential, for example, it can be connected to the power supply VDD; the drain of the NMOS region 810 and the drain of the PMOS region 820 can be commonly connected to the output terminal OUT; the first polysilicon gate 812 of the NMOS region 810 and the second polysilicon gate 821 of the PMOS region 820 can be commonly connected to the input terminal IN. When the signal at the input terminal IN is at a high potential, the gate-source voltage of the NMOS region 810 is greater than its threshold voltage, and a lateral N-type channel can be formed and conducted in the P-type body region P-body of the NMOS region 810, and the output terminal OUT outputs a low-level signal; when the signal at the input terminal IN is at a low potential, the absolute value of the gate-source voltage of the PMOS region 820 is greater than the absolute value of its threshold voltage, and a lateral P-type channel can be formed and conducted in the N-type body region N-body of the PMOS region 810, and the output terminal OUT outputs a high-level signal.

[0093] Based on the above embodiments, the P-type body region P-body further includes a heavily doped P-type region P+, the heavily doped P-type region P+ is located on a side of one of the heavily doped N-type regions N+ in the NMOS region 810 away from the first spacer, and a first shallow trench isolation STI-1 is provided between the heavily doped P-type region P+ and the heavily doped N-type region N+; the N-type body region N-body further includes a heavily doped N-type region N+, the heavily doped N-type region N+ is located on a side of one of the heavily doped P-type regions P+ in the PMOS region 820 away from the second spacer, and a second shallow trench isolation STI-2 is provided between the heavily doped N-type region N+ and the heavily doped P-type region P+; the CMOS device 800 further includes a third shallow trench isolation STI-3 located between the P-type body region P-body and the N-type body region N-body.

[0094] Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing an integrable vertical high-voltage device. Figure 7 It is a flowchart of a method for manufacturing an integrable vertical high-voltage device provided by an embodiment of the present invention. Figure 8 It is a schematic structural diagram of a manufacturing process of an integrable vertical high-voltage device provided by an embodiment of the present invention. Refer to Figure 7 and Figure 8 , the manufacturing method includes:

[0095] S1001. Provide an N-type substrate.

[0096] Among them, the N-type substrate 01 includes but is not limited to a silicon substrate.

[0097] S1002. Grow a first N-type epitaxial layer above the N-type substrate, and perform ion implantation in a partial region of the first N-type epitaxial layer to form a first P-well region.

[0098] Exemplarily, the thickness of the first N-type epitaxial layer 11 can be 0.5 - 2 μm. Then, through a photolithography process, an ion implantation region (not shown in the figure) that is not covered by the photoresist is formed, and boron ions are implanted to form the first P-well region 21.

[0099] S1003. Grow a second N-type epitaxial layer above the first N-type epitaxial layer, and perform ion implantation in the second N-type epitaxial layer above the first P-well region to form a second P-well region.

[0100] Exemplarily, the thickness of the second N-type epitaxial layer 12 can be 3 - 6 μm. Then, through a photolithography process, an ion implantation region (not shown in the figure) that is not covered by the photoresist is formed, and boron ions are implanted to form the second P-well region 22. Among them, the thickness and resistivity of the second N-type epitaxial layer 12 can be determined by the breakdown voltage and on-resistance of the vertical high-voltage device 100.

[0101] S1004. Form a vertical high-voltage device in the second N-type epitaxial layer where the second P-well region is not provided, and form a planar device in the second P-well region.

[0102] Among them, part of the structures of the vertical high-voltage device 100 and the planar device PLD can be carried out in the same process.

[0103] Exemplarily, taking the integrable vertical high-voltage device including two second P-well regions 22 as an example, where one of the second P-well regions 22 can be used to form an LDMOS transistor 700, and the other second P-well region 22 can be used to form a CMOS device 800. Figure 9 It is a schematic structural diagram of the preparation process of the device in an integrable vertical high-voltage device provided by an embodiment of the present invention. Refer to Figure 8 and Figure 9 , after forming the first N-type epitaxial layer 11 and the second N-type epitaxial layer 12 by epitaxy in two times respectively, and forming the first P-well region 21 and the second P-well region 22 by ion implantation in two times respectively, a vertical body region 40 can be formed in the region of the second N-type epitaxial layer 12 where the second P-well region 22 is not formed, a lateral drift region 710 and a lateral body region 720 can be formed in one of the second P-well regions 22, and a P-type body region P-body and an N-type body region N-body can be formed in the other second P-well region 22; secondly, an isolation groove is etched, and an insulating material is filled in the etched groove to form device shallow trench isolation D-STI, lateral shallow trench isolation L-STI, first shallow trench isolation STI-1, second shallow trench isolation STI-2, and third shallow trench isolation STI-3 respectively. After forming the shallow trench isolation, a gate trench GT is etched, and a vertical gate oxide layer 31 and a vertical polysilicon gate 32 are formed in the gate trench GT in sequence; then, heavy doping implantation is carried out to form a source region and a drain region, and the preparation of the vertical high-voltage device 100 is completed. Finally, a gate oxide layer and a polysilicon gate are formed on the surface of the second P-well region 22 in sequence, and the preparation of the LDMOS transistor 700 and the CMOS device 800 is completed.

[0104] In the embodiment of the present invention, by forming the first N-type epitaxial layer and the second N-type epitaxial layer in two times above the N-type substrate, forming the first P-well region in the first N-type epitaxial layer, and forming the second P-well region in the second N-type epitaxial layer above the first P-well region, and performing ion implantation respectively after each epitaxy, that is, injecting in two times to form the first P-well region and the second P-well region respectively, the difficulty of deep well implantation can be reduced, deep well implantation with a larger depth can be realized, which is beneficial to the integration of planar devices. At the same time, a higher breakdown voltage value can be achieved; forming a planar device in the second P-well region enables the first P-well region and the second P-well region to not only isolate the vertical high-voltage device and the planar device, but also serve as the substrate of the planar device, which is beneficial to the integration of devices and improves the integration degree.

[0105] Optionally, ion implantation is performed in a partial region of the first N-type epitaxial layer to form a first P-well region, including: performing high-temperature furnace tube push-annealing at a first temperature; the first temperature is greater than or equal to 1000 °C and less than or equal to 1500 °C; and / or, ion implantation is performed in the second N-type epitaxial layer above the first P-well region to form a second P-well region, including: performing high-temperature furnace tube push-annealing at a second temperature; the second temperature is greater than or equal to 1000 °C and less than or equal to 1500 °C. In this way, it is beneficial to uniformly implant ions, increase the depletion region size, improve the breakdown voltage value, avoid ion aggregation, and form a step junction, which may cause easy breakdown and damage.

[0106] Optionally, after the device preparation is completed by the above preparation method, to ensure the normal use of the device, it needs to be connected to the outside, that is, it is necessary to connect metal electrodes. Therefore, after S1004, the following steps can be added: perform back-end processes to form a plurality of contact electrodes.

[0107] In an alternative embodiment, after S1004, the N-type substrate 01 can be thinned to 100 μm, and then a metal layer is sputtered to form the drain of the vertical high-voltage device 100, as Figure 1 shown.

[0108] In yet another alternative embodiment, Figure 10 is a schematic structural diagram of the preparation process of another integrable vertical high-voltage device provided by an embodiment of the present invention. Referring to Figure 10 , after growing the first N-type epitaxial layer 11 above the N-type substrate, before growing the second N-type epitaxial layer 12, ion implantation can be performed in a partial region of the first N-type epitaxial layer 11 to form a first N-well region 611; after forming the second N-type epitaxial layer 12, ion implantation can be performed in a partial region of the second N-type epitaxial layer 12 to form a second N-well region 612. The first N-well region 611 and the second N-well region 612 arranged vertically and connected to each other constitute a deep N-well region 61. The deep N-well region 61 is electrically connected to the N-type substrate 01, and the drain 104 of the vertical high-voltage device 100 can be led out to the front surface of the chip, that is, the upper surface of the second N-type epitaxial layer 12, as Figure 3 and Figure 4 shown. In this way, during measurement, there is no need to thin the N-type substrate 01 and sputter a thick metal on the lower surface of the N-type substrate 01 to form the drain 104. When the drain 104 of the vertical high-voltage device 100 is led out to the front surface of the chip, the drain 104 of the vertical high-voltage device 100 can be formed in the same process as the gate 101, the source 102, and the body 103, which is beneficial to simplifying the process, improving the yield and production efficiency, and reducing the production cost.

[0109] In yet another alternative embodiment, a vertical high-voltage device is formed in a second N-type epitaxial layer without a second P-well region, including: etching the second N-type epitaxial layer without a second P-well region to form a deep drain trench, exposing the N-type substrate; filling the deep drain trench with N-type polysilicon or a conductive metal structure.

[0110] Exemplarily, Figure 11 is a schematic structural diagram of the preparation process of a device in another integrable vertical high-voltage device provided by an embodiment of the present invention. Referring to Figure 11 , a second N-type epitaxial layer can be grown above the first N-type epitaxial layer, and ion implantation can be performed on the second N-type epitaxial layer above the first P-well region to form a second P-well region. Then, after that, etching is performed on the second N-type epitaxial layer without a second P-well region to form a deep drain trench DT, exposing the N-type substrate 01. Then, N-type polysilicon N-poly or a conductive metal structure Metal is filled in the deep drain trench DT, so that the drain electrode of the vertical high-voltage device 100 can be led out to the front surface of the chip through the N-type polysilicon N-poly or the conductive metal structure Metal. In this way, a vertical high-voltage device 100 with a lower on-resistance can be obtained.

[0111] In an alternative implementation manner, the deep drain trench DT and the gate trench GT can be formed in the same process, and there is at least one second P-well region 22 between the deep drain trench DT and the gate trench GT. Of course, the deep drain trench DT and the gate trench GT can also be formed in different processes, and the embodiments of the present invention do not limit this.

[0112] Optionally, the vertical high-voltage device further includes a P-type substrate; the P-type substrate is located below the N-type substrate, as shown in Figure 3 and Figure 4 . Providing the N-type substrate includes: providing a P-type substrate, performing epitaxy above the P-type substrate to form an N-type substrate; or, providing a P-type substrate, performing ion implantation on the P-type substrate to form an N-type substrate; or, providing a P-type substrate, bonding an N-type substrate above the P-type substrate.

[0113] Exemplarily, an N-type substrate can be epitaxially formed on the P-type substrate, and then high-concentration antimony ions and / or arsenic ions are implanted to reduce the resistivity of the N-type substrate; or, a relatively thick P-type substrate can be provided first, and then high-concentration ion implantation is directly performed on the upper surface of the P-type substrate, so that the upper half of the P-type substrate can form an N-type substrate; or, a low-resistance N-type substrate can be directly bonded to the upper surface of the P-type substrate.

[0114] The preparation method of the integrable vertical high-voltage device provided by the embodiment of the utility model is used to prepare the integrable vertical high-voltage device provided by any embodiment of the present utility model, and has the corresponding technical features and beneficial effects of the integrable vertical high-voltage device. For the content not described in detail in the embodiment of the preparation method of the integrable vertical high-voltage device, reference may be made to the description of the integrable vertical high-voltage device above, and details will not be repeated here; similarly, the integrable vertical high-voltage device provided by the embodiment of the present utility model also has a functional module and beneficial effects capable of implementing the preparation method of the integrable vertical high-voltage device provided by the embodiment of the present utility model. For the content not described in detail in the embodiment of the integrable vertical high-voltage device, reference may be made to the description of the preparation method of the integrable vertical high-voltage device above, and details will not be repeated here.

[0115] Note that the above is only the preferred embodiment of the present utility model and the technical principles applied. Those skilled in the art will understand that the present utility model is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present utility model. Therefore, although the present utility model has been described in detail through the above embodiments, the present utility model is not limited to the above embodiments. Without departing from the concept of the present utility model, more other equivalent embodiments can be included, and the scope of the present utility model is determined by the scope of the appended claims.

Claims

1. An integrable vertical high-voltage device, characterized in that, Comprising: An N-type substrate; A first N-type epitaxial layer, located above the N-type substrate; A first P-well region, located in the first N-type epitaxial layer; A second N-type epitaxial layer, located above the first N-type epitaxial layer; A second P-well region, located in the second N-type epitaxial layer and above the first P-well region; A gate trench, located in the second N-type epitaxial layer where the second P-well region is not provided; a longitudinal gate oxide layer and a longitudinal polysilicon gate are provided in the gate trench, and the longitudinal gate oxide layer wraps the longitudinal polysilicon gate; A longitudinal body region, also located in the second N-type epitaxial layer where the second P-well region is not provided; the longitudinal body region is adjacent to the gate trench in the horizontal direction; wherein, the longitudinal body region is provided with a longitudinal source region, a heavily doped body region, and a lightly doped body region, the heavily doped body region, the longitudinal source region, and the gate trench are adjacent to each other in the horizontal direction in sequence, and the lightly doped body region is located below the heavily doped body region and the longitudinal source region; A planar device, located in the second P-well region and on the upper surface of the second P-well region; wherein, the planar device includes an LDMOS transistor and / or a CMOS device.

2. The integrable vertical high-voltage device according to claim 1, characterized in that, The planar device includes the LDMOS transistor and the CMOS device; The LDMOS transistor and the CMOS device are respectively located in different second P-well regions, and different second P-well regions are respectively located above different first P-well regions; In the horizontal direction, device shallow trench isolation is provided between any two of the longitudinal high-voltage device, the LDMOS transistor, and the CMOS device.

3. The integrable longitudinal high-voltage device according to claim 1, characterized in that A drain region is provided in the second N-type epitaxial layer where the second P-well region is not provided; the drain region penetrates through the second N-type epitaxial layer and the first N-type epitaxial layer and is connected to the N-type substrate; Wherein, at least part of the first P-well region and the second P-well region above it are located between the drain region and the longitudinal high-voltage device.

4. The integrable longitudinal high-voltage device according to claim 3, characterized in that The drain region includes a deep N-well region; Or, the drain region includes a deep drain trench and N-type polysilicon located in the deep drain trench; Or, the drain region includes a deep drain trench and a conductive metal structure located in the deep drain trench.

5. The integrable vertical high-voltage device according to claim 1, characterized in that, Further comprising: A P-type substrate; The P-type substrate is located below the N-type substrate.

6. The integrable vertical high-voltage device according to claim 1, characterized in that, The planar device includes the LDMOS transistor; The LDMOS transistor includes a lateral drift region and a lateral body region located in the second P-well region; The LDMOS transistor further includes a lateral drain region located in the lateral drift region, a lateral source region located in the lateral body region, and a lateral polysilicon gate at least partially located between the lateral drift region and the lateral body region and above the second P-well region.

7. The integrable vertical high-voltage device according to claim 6, characterized in that, The LDMOS transistor further includes a lateral shallow trench isolation located above the lateral drift region; The lateral shallow trench isolation is located on a side of the lateral drain region close to the lateral body region, and the lateral shallow trench isolation and the lateral drain region are adjacently arranged in a horizontal direction; In a vertical direction, a depth of the lateral shallow trench isolation is greater than or equal to a depth of the lateral drain region.

8. The integrable vertical high-voltage device according to claim 1, characterized in that, The planar device includes the CMOS device; The CMOS device includes a P-type body region, an N-type body region located in the second P-well region, an NMOS region located in the P-type body region, and a PMOS region located in the N-type body region; The NMOS region includes two N-type heavily doped regions, and a first interval exists between the two N-type heavily doped regions; a first gate oxide layer and a first polysilicon gate are disposed above the first interval, wherein the first polysilicon gate is located above the first gate oxide layer; The PMOS region includes two P-type heavily doped regions, and a second interval exists between the two P-type heavily doped regions; a second gate oxide layer and a second polysilicon gate are disposed above the second interval, wherein the second polysilicon gate is located above the second gate oxide layer.

9. The integrable vertical high-voltage device according to claim 8, wherein The P-type body region further includes a P-type heavily doped body region, the P-type heavily doped body region is located on a side of one of the N-type heavily doped regions of the NMOS region away from the first interval, and a first shallow trench isolation is disposed between the P-type heavily doped body region and the N-type heavily doped region; The N-type body region further includes an N-type heavily doped body region, the N-type heavily doped body region is located on a side of one of the P-type heavily doped regions of the PMOS region away from the second interval, and a second shallow trench isolation is disposed between the N-type heavily doped body region and the P-type heavily doped region; The CMOS device further includes a third shallow trench isolation located between the P-type body region and the N-type body region.

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