Capacitor connection structure and integrated chip
By designing the MIM capacitor structure in a wafer-level radio frequency solution, the low-level end of the capacitor is in direct contact with the semiconductor substrate, the problem of electrical stress failure caused by water vapor intrusion is solved and the reliability of the capacitor is improved.
Patent Information
- Application Number
- CN202422121093.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2025-07-29
- Estimated Expiration
- 2034-08-30
AI Technical Summary
In wafer-level RF solutions, the metal plate and substrate interface of IPD capacitors are susceptible to invasion of water vapor, resulting in electrical stress failure and affecting reliability.
The low-level end of the capacitor is directly in contact with the semiconductor substrate. Through the MIM capacitor structure design, the capacitive metal interface in contact with the semiconductor substrate has a smaller electrical stress to avoid water vapor intrusion.
Improve the durability of the capacitor in reliability test, reduce electrochemical reactions, and enhance the reliability of the capacitor, especially under high temperature and high humidity conditions.
Smart Images
Figure CN223168645U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductors, and particularly relates to a capacitor connection structure and an integrated chip. Background Art
[0002] Integrated passive devices (IPDs) play a key role in wafer-level RF solutions and are typically used for one or more functions in PA / LNA circuits: coupling, biasing, filtering, matching, and conversion. The demand for highly integrated lightweight products is driving the development of this technology.
[0003] IPD capacitors usually include upper and lower metal plates and a dielectric layer sandwiched between the two metal plates. When used for power filtering functions or when the two ends are respectively connected in parallel with DC and GND, both the circuit design and test conditions will have unpredictable effects on reliability. Among them, in tests such as temperature humidity bias (THB) or bias high acceleration stress (BHAST), water vapor is likely to enter the chip device from the edge of the chip. The capacitor usually shows that the interface between the metal plate connected to the substrate and the substrate is more easily invaded by water vapor than other interfaces, resulting in electrical stress failure, which limits its reliability. Summary of the Utility Model
[0004] Aiming at the deficiencies existing in the prior art, the utility model provides a capacitor connection structure and an integrated chip.
[0005] In order to achieve the above purposes, the technical solution of the utility model is as follows:
[0006] A capacitor connection structure includes a first metal layer, a first dielectric layer, and a second metal layer sequentially arranged on a semiconductor substrate; the first metal layer is in direct contact with the semiconductor substrate, the first metal layer includes a first electrode plate, the second metal layer includes a separated second electrode plate and a first connection portion, the second electrode plate and the first electrode plate are spaced apart by the first dielectric layer to form a MIM capacitor, and the first connection portion is electrically connected to the first electrode plate through an opening in the first dielectric layer; the first electrode plate is led out through a first trace, the second electrode plate is led out through a second trace, and the first trace includes the first connection portion; the first electrode plate and the first trace serve as the low-level end of the capacitor, and the second electrode plate and the second trace serve as the high-level end of the capacitor.
[0007] Optionally, it further includes a second dielectric layer and a third metal layer, the third metal layer includes a third electrode plate, the second dielectric layer and the third electrode plate are sequentially arranged on the second electrode plate to form a stacked capacitor, and the third electrode plate is connected in common with the first electrode plate through the first trace.
[0008] Optionally, a third dielectric layer and an insulating layer are sequentially covered on the surface of the capacitor connection structure. The first trace further includes a fourth metal layer, which is disposed on the insulating layer and is electrically connected to the first connection portion and the third electrode plate through conductive vias respectively.
[0009] Optionally, an external connection structure is provided on the fourth metal layer.
[0010] Optionally, a back gold layer is provided on the back surface of the semiconductor substrate, and the back gold layer is set to be equipotential with the low-level end of the capacitor.
[0011] Optionally, the first trace includes a conductive via penetrating through the semiconductor substrate, and the conductive via is electrically connected to the back gold layer.
[0012] Optionally, the capacitor connection structure and the HBT device are integrated on the HBT chip, and the first metal layer is a collector contact layer.
[0013] An integrated chip includes the above capacitor connection structure, and further includes a power supply module and a GND module. The first trace is connected to the GND module, and the second trace is connected to the power supply module.
[0014] Optionally, the integrated chip is a radio frequency power amplifier chip, the capacitor is a notch capacitor in the radio frequency power amplifier circuit, the second trace includes an external bonding pad, the power supply module is provided with a Vcc terminal bonding pad, and the external bonding pad and the Vcc terminal bonding pad are wire-bonded.
[0015] Optionally, the integrated chip is a radio frequency power amplifier chip, the capacitor is a power supply filter capacitor in the radio frequency power amplifier circuit, the power supply module is provided with a Vcc terminal bonding pad, the second metal layer further includes a second connection portion connected to the second electrode plate, and the second connection portion is connected to the Vcc terminal bonding pad as the second trace.
[0016] The beneficial effects of the present utility model are as follows:
[0017] Taking the metal layer in direct contact with the semiconductor substrate as the low-level end of the capacitor makes the capacitor metal interface in contact with the semiconductor substrate have a smaller electrical stress, and it is not easy to occur an electrochemical reaction in the reliability test, avoiding the chip boundary capacitor failure caused by water vapor intrusion, and enhancing the reliability of the easily failed interval. Description of the Drawings
[0018] Figure 1 It is a cross-sectional schematic diagram of the MIM capacitor connection structure of an embodiment;
[0019] Figure 2 For Figure 1Top view schematic of the positional relationship between metal layers of the MIM capacitor connection structure in China
[0020] Figure 3 Cross-sectional schematic of the MIM capacitor connection structure of another embodiment, where the first metal layer and the back gold layer are electrically connected through a conductive via
[0021] Figure 4 Cross-sectional schematic of the stacked capacitor connection structure of another embodiment, where the first metal layer and the back gold layer are set at the same potential
[0022] Figure 5 Cross-sectional schematic of the stacked capacitor connection structure of another embodiment, where the first trace is led out through an external structure
[0023] Figure 6 Connection schematic (a) and circuit schematic (b) of an integrated chip of an embodiment
[0024] Figure 7 Connection schematic (a) and circuit schematic (b) of an integrated chip of another embodiment Specific implementation mode
[0025] The following further explains the present utility model in conjunction with the accompanying drawings and specific embodiments. The various drawings of the present utility model are only for illustration to more easily understand the present utility model, and its specific ratio can be adjusted according to design requirements. The up-down relationship between relative elements and the definition of front / back in the described figures should be understood by those skilled in the art as referring to the relative positions of the components. Therefore, they can all be flipped to present the same components, and this should all fall within the scope disclosed in this specification
[0026] Reference Figure 1 and Figure 2, A capacitive connection structure of an embodiment includes a first metal layer M1, a first dielectric layer V1, and a second metal layer M2 sequentially disposed on a semiconductor substrate 1; the first metal layer M1 is in direct contact with the semiconductor substrate 1, the first metal layer M1 includes a first electrode plate 2, the first dielectric layer V1 covers the exposed surfaces of the first metal layer M1 and the semiconductor substrate 1, the second metal layer M2 includes a separated second electrode plate 3 and a first connection portion 41, the second electrode plate 3 is disposed on the first dielectric layer V1 above the first electrode plate 2, and the first dielectric layer V1 sandwiched between the first electrode plate 2 and the second electrode plate 3 serves as a capacitive dielectric to form a MIM capacitor. The first dielectric layer V1 has an opening a outside the covering area of the second electrode plate 3 above the first electrode plate 2, and the first connection portion 4 is electrically connected to the first electrode plate 2 by being deposited in the opening a. The first electrode plate 2 is led out through the first trace 4, the second electrode plate 3 is led out through the second trace 5, and the first trace 4 includes the first connection portion 41. A back gold layer 6 is provided on the back surface of the semiconductor substrate 1. When designing the connection attributes of the capacitive electrode plates, the second electrode plate 3 and the second trace 5 serve as the high-level terminal of the capacitor, that is, the power supply terminal; the first electrode plate 2 and the first trace 4 serve as the low-level terminal of the capacitor, that is, the GND terminal, and are at the same potential as the back gold layer 6, so that the capacitive metal interface in contact with the semiconductor substrate 1 has a small electrical stress and is not prone to electrochemical reactions during reliability tests, thereby improving device reliability.
[0027] The first trace 4 and the second trace 5 can be formed by patterned metal deposition, a redistribution structure, or wire bonding. When depositing the second metal layer, the patterned second metal layer simultaneously forms the second electrode plate 3 and the first connection portion 41, the first connection portion 41 forms a wiring, or combines with the deposition of other subsequent metal layers to form a wiring to form the first trace 4, and the first trace 4 is set to be at the same potential as the back gold layer 6. In another embodiment, refer to Figure 3 , the first trace 4 includes a conductive via 42 penetrating the semiconductor substrate 1, and both ends of the conductive via 42 are connected to the first connection portion 41 and the back gold layer 6 respectively, and are grounded through the back gold layer 6. For example, the first metal layer M1 further includes a second connection portion 43, the conductive via 42 includes forming a via in the semiconductor substrate 1, the bottom of the via exposes the second connection portion 43, and when the back gold layer 6 is fabricated, the via is filled simultaneously to make the via conductive, then the conductive via 42 is electrically connected to the second connection portion 43, and the first connection portion 41 is deposited on the second connection portion 43 simultaneously to achieve electrical connection.
[0028] The capacitor can also be a stacked capacitor. Refer to Figure 4, in addition to the first metal layer M1, the first dielectric layer V1, and the second metal layer M2 sequentially disposed on the semiconductor substrate 1, it further includes a second dielectric layer V2 and a third metal layer M3. The second dielectric layer V2 covers the second metal layer M2 and the exposed surface of the first dielectric layer V1. The third metal layer M3 includes a third electrode plate 7, and the third electrode plate 7 is disposed on the second dielectric layer V2 on the second electrode plate 3 to form a stacked capacitor structure. It further includes a third dielectric layer V3 covering the third metal layer M3 and the exposed surface of the second dielectric layer V2, and an insulating layer 8 is covered on the third dielectric layer V3 to achieve planarization. The insulating layer 8 is made of materials such as polyimide (PI). The first trace 4 further includes a fourth metal layer M4. The fourth metal layer M4 is disposed on the surface of the insulating layer 8 and is electrically connected to the first connection portion 41 through a conductive via 441 penetrating the insulating layer 8, the second dielectric layer V2, and the third dielectric layer V3, and is electrically connected to the third electrode plate 7 through a conductive via 442 penetrating the insulating layer 8 and the third dielectric layer V3, so that the third electrode plate 7 and the first electrode plate 2 are collinearly connected. A back gold layer 6 is provided on the back surface of the semiconductor substrate 1. When designing the connection attributes of the capacitor electrode plates, the second electrode plate 3 and the second trace 5 are used as the high-level end of the stacked capacitor, that is, the power supply end; the first electrode plate 2, the third electrode plate 7, and the first trace 4 are used as the low-level end of the capacitor, that is, the GND end, and are at the same potential as the back gold layer 6, so that the capacitor metal interface in contact with the semiconductor substrate has a small electrical stress and is not prone to electrochemical reactions during reliability tests, thereby improving the device reliability and effectively improving the bHAST ability.
[0029] Reference Figure 5 , in another embodiment, the back gold layer is not provided on the back surface of the semiconductor substrate 1, and the first trace 4 further includes an external connection structure 45. The external connection structure 45 is disposed on the fourth metal layer M4 and is, for example, a copper pillar structure for GND bonding.
[0030] In the above embodiments, the first dielectric layer V1, the second dielectric layer V2, and the third dielectric layer V3 are respectively made of inorganic dielectric materials such as silicon nitride and silicon oxide. The first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are respectively made of conductive metal materials or their laminates. The semiconductor substrate 1 includes an epitaxial layer such as a GaAs-based epitaxial layer and a GaN-based epitaxial layer. When manufacturing the capacitor, it can be carried out synchronously with the processes of other devices in the integrated circuit chip. For example, the capacitor connection structure and the HBT device are integrated on the HBT chip, and the first metal layer M1 is synchronously deposited as the collector contact layer metal, and the other metal layers are manufactured synchronously with the wiring layers of the HBT device.
[0031] The above capacitor connection structure is applied to an integrated chip, and the first trace of the capacitor is connected to the GND module, and the second trace is connected to the power supply module. Reference Figure 6, when the capacitor C is a trap capacitor (trap capacitance), taking the trap circuit applied to a radio frequency power amplifier (PA) for suppressing harmonics as an example, the second trace 5 is formed by being arranged on the same layer as the second metal layer M2 or by combining with subsequent deposition of other metal layers to form a wiring, and an external pad 51 is provided at the end. The power supply module 9 has a Vcc terminal pad 91. The external pad 51 and the Vcc terminal pad 91 are bonded and collinear through a lead 10, so as to be connected to the line between the radio frequency input port RF in and the radio frequency output port RF out; the first trace 4 is led out and connected to the GND module 11 in the above manner. Reference Figure 7 , when the capacitor C is a filtering capacitor, taking the power supply filtering capacitor applied to a radio frequency power amplifier (PA) as an example, the power supply module 9 has a Vcc terminal pad 91. The second metal layer M2 further includes a second connection portion connected to the second electrode plate 3, which is used as the second trace 5 and is directly connected to the Vcc terminal pad 91, so as to be connected to the circuit power supply port; the first trace 4 is led out and connected to the GND module 11 in the above manner. In the capacitor, the first metal layer M1 is the low-level terminal, which has smaller electrical stress relative to the high-level terminal and is not prone to electrochemical reactions, enhancing the reliability of the easily failed interval.
[0032] The above embodiments are only used to further illustrate a capacitor connection structure and an integrated chip of the present invention, but the present invention is not limited to the embodiments. Any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. A capacitor connection structure, characterized in that: It includes a first metal layer, a first dielectric layer, and a second metal layer sequentially disposed on a semiconductor substrate; the first metal layer is in direct contact with the semiconductor substrate, the first metal layer includes a first electrode plate, the second metal layer includes a separated second electrode plate and a first connection portion, a MIM capacitor is formed with a gap between the second electrode plate and the first electrode plate through the first dielectric layer, and the first connection portion is electrically connected to the first electrode plate through an opening in the first dielectric layer; the first electrode plate is led out through a first trace, the second electrode plate is led out through a second trace, wherein the first trace includes the first connection portion; the first electrode plate and the first trace serve as the low-level terminal of the MIM capacitor, and the second electrode plate and the second trace serve as the high-level terminal of the MIM capacitor.
2. The capacitive connection structure according to claim 1, wherein: It further includes a second dielectric layer and a third metal layer, the third metal layer includes a third electrode plate, and the second dielectric layer and the third electrode plate are sequentially disposed on the second electrode plate to form a stacked capacitor, and the third electrode plate is connected in common with the first electrode plate through the first trace.
3. The capacitive connection structure according to claim 2, wherein: The surface of the capacitor connection structure is sequentially covered with a third dielectric layer and an insulating layer, the first trace further includes a fourth metal layer, and the fourth metal layer is disposed on the insulating layer and is electrically connected to the first connection portion and the third electrode plate respectively through conductive vias.
4. The capacitive connection structure according to claim 3, wherein: An external connection structure is provided on the fourth metal layer.
5. The capacitive connection structure according to claim 1, wherein: A back gold layer is provided on the back surface of the semiconductor substrate, and the back gold layer is set to be equipotential with the low-level terminal of the capacitor.
6. The capacitive connection structure according to claim 5, wherein: The first trace includes a conductive via penetrating the semiconductor substrate, and the conductive via is electrically connected to the back gold layer.
7. The capacitive connection structure according to claim 1, characterized in that: The capacitor connection structure and an HBT device are integrated on an HBT chip, and the first metal layer is a collector contact layer.
8. An integrated chip, characterized in that: It includes the capacitor connection structure according to any one of claims 1 to 7, and further includes a power supply module and a GND module, the first trace is connected to the GND module, and the second trace is connected to the power supply module.
9. The integrated chip according to claim 8, wherein: The integrated chip is a radio frequency power amplifier chip, the capacitor is a notch capacitor in a radio frequency power amplifier circuit, the second trace includes an external bonding pad, the power supply module is provided with a Vcc terminal bonding pad, and the external bonding pad and the Vcc terminal bonding pad are bonded by a wire bond.
10. The integrated chip according to claim 8, wherein: The integrated chip is a radio frequency power amplifier chip, the capacitor is a power supply filter capacitor in a radio frequency power amplifier circuit, the power supply module is provided with a Vcc terminal bonding pad, the second metal layer further includes a second connection portion connected to the second electrode plate, and the second connection portion serves as the second trace and is connected to the Vcc terminal bonding pad.