Integrated circuit device

Abstract

An integrated circuit device includes a first interconnect structure configured to distribute a supply voltage, a second interconnect structure configured to distribute a reference voltage, a third interconnect structure configured to distribute a first power gate control signal, and a plurality of logic circuits. Each logic circuit of the plurality of logic circuits includes a power switch. A power switch is coupled in series to a logic gate between the first interconnect structure and the second interconnect structure. And, the power switch includes a control terminal coupled to the third interconnect structure.

Description

Technical Field

[0001] The utility model relates to an integrated circuit device. Background Art

[0002] The continuous trend of miniaturization of integrated circuits (ICs) has led to devices that are getting smaller, consuming less power, but providing more functions at higher speeds than earlier technologies. Miniaturization has been achieved through design and manufacturing innovations related to increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify the design of semiconductor devices while ensuring that design and manufacturing specifications are met. Summary of the Utility Model

[0003] The utility model is directed to an integrated circuit device.

[0004] According to an embodiment of the utility model, an integrated circuit device includes a first interconnect structure configured to distribute a supply voltage, a second interconnect structure configured to distribute a reference voltage, a third interconnect structure configured to distribute a first power gating signal, and a plurality of logic circuits. Each logic circuit of the plurality of logic circuits includes a power switch. The power switch is serially coupled to a logic gate between the first interconnect structure and the second interconnect structure. Moreover, the power switch includes a control terminal coupled to the third interconnect structure. Description of the Drawings

[0005] Figure 1A-1C is a diagram of an IC layout and a corresponding IC device according to some embodiments.

[0006] Figure 2 is a diagram of an IC layout and a corresponding IC device according to some embodiments.

[0007] Figure 3 is a diagram of an IC layout and a corresponding IC device according to some embodiments.

[0008] Figure 4 is a diagram of an IC layout and a corresponding IC device according to some embodiments.

[0009] Figure 5 is a diagram of an IC layout and a corresponding IC device according to some embodiments.

[0010] Figure 6 is a diagram of an IC layout and a corresponding IC device according to some embodiments.

[0011] Figure 7 is a flowchart for generating an IC layout according to some embodiments.

[0012] Figure 8A and 8B is a flowchart of a method for generating an IC layout according to some embodiments.

[0013] Figure 9 is a block diagram of an IC design system according to some embodiments.

[0014] Figure 10 is a block diagram of an IC manufacturing system and an IC manufacturing process associated therewith according to some embodiments. Detailed Description

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following describes specific examples of components, values, operations, materials, arrangements, etc. to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, configurations, etc. may be contemplated. As shown by way of example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0016] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature. As shown in the figures. Spatially relative terms are intended to encompass different orientations of the device or operation in use in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0017] In various embodiments, the IC device / layout and the IC design system are for a logic circuit corresponding to an IC layout cell. The logic circuit includes a power switch responsive to a power gating signal. Therefore, the power switch needs to be able to be distributed throughout the IC circuit to address local current resistance (IR) drop issues related to electromigration and circuit timing.

[0018] In some embodiments, an IC floorplan is arranged to include logic cells / circuits with embedded power switches, thereby improving area density compared to a method where cells / circuits with equivalent logic are electrically connected to a local network (i.e., electrically connected to a power distribution network up to a network-level power switch).

[0019] In some applications, an EDA tool is used to select cells from a Cell Library and place the cells into an initial layout for routing, via which the cells are connected using one or more metal layers and corresponding vias and contacts. The EDA tool is further used to test the routing. Based on the test results, the selection, placement, and routing of standard and non-standard cells are modified. At least in some embodiments, the overall Selection, Placement, Routing, Testing (SPRT) process is iterative. Eventually, the SPRT process iteratively converges to a final layout.

[0020] In some embodiments, logic cells / circuits with embedded power switches are used to replace equivalent logic cells / circuits in response to a design check, such as detecting a resistance-based voltage drop above a threshold, thereby improving design efficiency by avoiding adding a parallel network. The power switch stage is part of an Engineering Change Order (Eco) design phase.

[0021] As described below, Figure 1A-6 is a diagram of IC layouts 100A - 600 and corresponding IC devices 100A - 600 according to some embodiments. For illustrative purposes, Figure 1A-6 each of which is simplified. In various embodiments, the IC layouts 100A - 600 and corresponding IC devices 100A - 600 include arrangement details and features not depicted for the sake of clarity, in addition to those depicted in Figure 1A-6 .

[0022] Figure 1A-6 The diagrams in represent IC layouts 100A - 600 and corresponding IC devices 100A - 600 that are at least partially fabricated based on the IC layouts 100A - 600. For example, according to the IC manufacturing system 1000 and related IC manufacturing processes discussed below for Figure 10 . According to some embodiments, Figure 7 , 8A and 8B are flowcharts of methods 700 and 800 for generating an IC layout (e.g., IC layout 100A - 600), respectively. Figure 9Block diagram of an IC design system 900 (e.g., EDA system 900), configured to perform some or all of the operations of method 700, method 800A, and / or method 800B.

[0023] As Figure 1A-1C Depicted, each of the IC layout diagrams / devices 100A - 100C includes a power switch PS configured in a series arrangement with a logic gate LG or an inverter INV (a non - limiting example of a logic gate LG). In some embodiments, the IC layout diagrams (e.g., IC layout diagrams 100A - 100C) are referred to as IC cells, cells, logic cells, embedded power switch cells, or embedded power switch logic cells. In some embodiments, the IC devices, such as IC devices 100A - 100C, are referred to as logic devices or logic circuits.

[0024] The series arrangement includes a first end electrically connected to a supply voltage TVDD (also referred to as true supply voltage TVDD in some embodiments) and a second end electrically connected to a reference voltage TVSS (also referred to as true reference voltage TVDD, ground TVSS, or true ground TVSS in some embodiments). The supply voltage TVDD and the reference voltage TVSS are further discussed below with respect to Figure 2 be further discussed.

[0025] A logic gate (e.g., logic gate LG) is an IC layout diagram / device, the layout diagram being configured to at least partially define a corresponding logic device, which is arranged to perform one or more logic functions in operation. In various embodiments, the logic gates include one or more of an inverter, a buffer, a transmission gate, and gates, NAND gates, OR gates, NOR gates, XOR gates, latches, and - or - inverters (AOI), or - and - inverters (OAI), multiplexers, flip - flops, etc.

[0026] In various embodiments, a given instance of the logic gate LG includes one or more input terminals configured to receive corresponding input signals during operation and one or more output terminals configured to output corresponding output signals. For the purpose of clarity, the input / output terminals and signals are not labeled in Figure 1A-6 are not labeled.

[0027] In various embodiments, a given instance of the power switch PS includes a control terminal (not labeled) configured to receive and a power gating signal, such as signal PGS. The power gating signal is configured to cause an instance of the power switch PS to couple and decouple a logic gate LG to and from a corresponding one of the supply voltage TVDD or the reference voltage TVSS, e.g., according to respective power-on and power-off modes of corresponding power domains.

[0028] As Figure 1A shown, the IC layout / component 100A includes a power switch PS, a transistor including a PMOS coupled between the supply voltage TVDD and a node VVDD, and a logic gate LG coupled between the node VVDD and the reference voltage TVSS. In some embodiments, the node VVDD is also referred to as voltage VVDD, virtual supply voltage VVDD, or virtual supply voltage node VVDD.

[0029] The power switch PS of the IC layout / device 100A includes a control terminal. The control terminal is a gate configured to receive the signal PGS. The IC layout / device 100A is thus configured to, in a power-on mode, in response to a low logic level of the signal PGS, couple the node VVDD and the logic gate LG to the supply voltage TVDD using the power switch PS in operation. And, the IC layout / device 100A is configured to, in a power-off mode, in response to a high logic level of the signal PGS, decouple the node VVDD and the logic gate LG from the supply voltage TVDD.

[0030] As Figure 1B shown, the IC layout / device 100B is a non-limiting example of the IC layout / device 100A, where the logic gate LG includes an inverter INV. The IC layout / device 100B is thus configured to couple and decouple the node VVDD and the inverter INV to and from the supply voltage TVDD in operation in response to the signal PGS.

[0031] As Figure 1C shown, the IC layout / component 100C includes a logic gate LG coupled between the supply voltage TVDD and a node VVSS, and a power switch PS including an NMOS transistor coupled between the node VVSS and the reference voltage TVSS. In some embodiments, the node VVSS is also referred to as voltage VVSS, virtual reference voltage VVSS, or virtual reference voltage node VVSS.

[0032] The power switch PS of the IC layout / device 100C includes a control terminal. The control terminal is a gate configured to receive the signal PGS. The IC layout / device 100C is thus configured to, in the power-on mode, in response to the high logic level of the signal PGS in the power-on mode, use the power switch PS to couple the node VVSS and the logic gate LG to the reference voltage TVSS during operation. And, the IC layout / device 100C is configured to, in the power-off mode, in response to the low logic level of the signal PGS, decouple the node VVSS and the logic gate LG from the reference voltage TVSS.

[0033] Via the above configuration, each IC layout / device 100A - 100C can be distributed throughout the IC circuit as needed to solve the local IR drop problems related to electromigration and circuit timing. In some embodiments, compared with the method in which cells / circuits with equivalent logic are electrically connected to a local network (electrically connected to the power distribution network to the network-level power switch), the IC layout plan is arranged to include one or more of the IC layouts / devices 100A - 100C, and thus can have an improved area density.

[0034] In some embodiments, as part of the ECO design phase, in response to a design check, such as detecting that the resistance-based voltage drop exceeds a threshold, instances of the IC layouts / devices 100A - 100C are used to replace equivalent logic cells / circuits, thereby improving the design efficiency by avoiding adding parallel network-level power switches.

[0035] Figure 2 FIG. 200 is a diagram of an IC layout and a corresponding IC device 200 according to some embodiments. The IC layout / device 200 includes a plurality of instances of the IC layouts / devices 100A - 100C (represented as IC layouts / devices 100). Each IC layout / device 200 is electrically connected to a power distribution network PDN1 configured to distribute the supply voltage TVDD, a power distribution network PDN2 configured to distribute the reference voltage TVSS, and a power signal distribution network PSN configured to distribute the power gating signal PGS as a single signal or the power signals PGSA and PGSB as complementary signals.

[0036] Each of the power distribution networks PDN1 and PDN2 and the power signal distribution network PSN is an IC layout / structure configured to distribute a corresponding power domain supply voltage TVDD, reference voltage TVSS, or signal PGS to various IC devices, such as the logic cells 100A - 100C discussed above. In various embodiments, the power distribution networks PDN1, power distribution network PDN2, and / or power signal distribution network PSN are referred to as the corresponding power grids PDN1 or PDN2, or the corresponding interconnect structures PDN1, PDN2, and / or PSN.

[0037] In some embodiments, in addition to the power distribution networks PDN1 and PDN2, the IC layout / device 200 further includes one or more local distribution networks (not shown) coupled to one or both of the power distribution networks PDN1 or PDN2 via one or more network power switches (such as the power switch PSW discussed below, which will receive a configuration as a power gating signal, such as signal PGS). Thus, one or more local distribution networks are configured to distribute a supply voltage (such as voltage VVDD) and / or a reference voltage (such as voltage VVSS) to, for example, one or more IC devices (not shown) other than the instances of the IC layout / device 100 in response to a power gating signal. Figure 6 discussed, which will receive a configuration as a power gating signal, such as signal PGS) coupled to one or both of the power distribution networks PDN1 or PDN2 via one or more network power switches (such as the power switch PSW discussed below). Thus, one or more local distribution networks are configured to distribute a supply voltage (such as voltage VVDD) and / or a reference voltage (such as voltage VVSS) to, for example, one or more IC devices (not shown) other than the instances of the IC layout / device 100 in response to a power gating signal.

[0038] Via the configuration discussed above, the IC layout / device 200 including the instances of the IC layout / devices 100A - 100C can achieve the benefits discussed above for Figure 1A-1C discussed.

[0039] Figure 3 is a diagram of an IC layout 300 and a corresponding IC device 300 according to some embodiments. In addition to the IC layout / device 300, Figure 3 also includes the X and Y directions. In some embodiments, the IC layout 300 is referred to as a planar layout 300.

[0040] The IC layout / device 300 includes two instances of a memory macro 300M and a memory channel 300C coupled between instances of the memory macro 300M. Figure 3 The number of instances of the memory macro 300M and the memory channel 300C depicted in Figure 3 is a non - limiting example presented for illustrative purposes. The number of instances of the memory macro 300M and the memory channel 300C other than those depicted is within the scope of the present disclosure.

[0041] In various embodiments, an instance of the memory macro 300M includes a Static Random-Access Memory (SRAM) device or other types of storage devices.

[0042] FIG. The memory channel 300C includes each instance of the memory macro 300M electrically connected as discussed above Figure 1A-1C through boundary cells (not labeled) between each other of the instance of the IC layout / device 100B.

[0043] The memory channel 300C has a width W in the X direction and extends between instances of the memory macro 300M. The value of the width W is a function of the arrangement of the boundary cells and the instance of the IC layout / device 100B. In some embodiments, the value of the width W ranges from 2 micrometers (μm) to 4 μm. In some embodiments, the value of the width W ranges from 1 μm to 2 μm.

[0044] Via the instance including the IC layout / device 100B, the IC layout / device 300 can have an area density improvement based on the width W of the memory channel 300C without including a local distribution network or including a limited local distribution network. Thus, based on other methods, such as those in which the memory channel includes a local distribution network and a network power switch and does not include an IC layout / device (including a power switch), the IC layout / device 300 can have an improved area density based on the width W being narrower than the corresponding width.

[0045] Figure 4 is a diagram of an IC layout 400 and a corresponding IC device 400 according to some embodiments. In addition to the IC layout / device 400, Figure 4 also includes the X and Y directions.

[0046] The IC layout / device 400 corresponds to a Multi-bit Synchronizer Flop circuit cell / device, which includes multiple instances of a Single-bit Synchronizer Flop 400F (a single instance labeled for clarity purposes), also referred to as the flop 400F in some embodiments. In some embodiments, the IC layout 400 is referred to as the cell 400 or the flop cell 400.

[0047] Each instance of the flop 400F is an IC layout portion corresponding to a logic circuit that includes multiple logic gates. The multiple logic gates are configured to synchronize the transmission of data bits to a clock signal (not shown). The instances of the flop 400 are thus collectively configured to synchronize the transmission of multiple data bits to the clock signal.

[0048] The IC layout / device 400 includes multiple instances of the power switch PS including PMOS transistors as described above. Each instance is configured to receive the signal PGS in operation and in response couple one or more instances of the flip-flop 400F to / decouple from the supply voltage TVDD. Figure 4 The number of instances of the power switch PS and the flip-flop 400F depicted in Figure 4 is a non-limiting example presented for illustrative purposes. The number of instances of the power switch PS and the flip-flop 400F other than those depicted in

[0049] Via the instances including the power switch PS, the IC layout / circuit / device 400 including the IC layout can include instances of the flip-flop 400F without including a native distribution network or including a limited native distribution network. Thus, compared with other methods, the IC layout / circuit including the IC layout / device 400 can have improved area density, such as those methods in which the circuit includes multiple unit element flip-flops electrically connected to a local distribution network and one or more network power switches, and does not include the IC layout / device including a power switch.

[0050] Figure 5 is a diagram of an IC layout 500 and a corresponding IC device 500 according to some embodiments. The IC layout / device 500 includes multiple instances of each of the IC layout / devices 100A and 100C, electrically connected to multiple instances of each of the supply voltage TVDD and the reference voltage TVSS.

[0051] In Figure 5 the depicted embodiment, each instance of the IC layout / device 100A includes a logic gate LG including a NAND gate and a control terminal or a power switch PS configured to receive the power gate control signal PGSA. Each instance of the IC layout / device 100C includes a logic gate LG and a power switch PS, the logic gate LG includes a NOR gate, and the control terminal or the power switch PS is configured to receive a power gate control signal PGSB complementary to the signal PGSA.

[0052] In various embodiments, in the IC layout / device 500, the power gate control signals PGSA and PGSB are configured to be received simultaneously or sequentially by each corresponding instance of the IC layout / devices 100A or 100C.

[0053] The IC layout / device 500 is thus configured to include instances of IC layout / devices 100A and 100C, configured to couple the respective instances of node VVDD and logic gate LG to / from the supply voltage TVDD in response to signal PGSA simultaneously or sequentially during operation, and couple the respective instances of node VVDD and logic gate LG to / from node VVSS and logic gate LG to the reference voltage TVSS or from the reference voltage TVSS in response to signal PGSB.

[0054] Figure 5 The number and arrangement of the instances of IC layout / devices 100A and 100C and the type of logic gate LG depicted in are provided as non-limiting examples for illustrative purposes. The IC layout / device 500 includes other numbers and / or arrangements of instances of IC layout / devices 100A and / or 100C and / or logic gate LG types, where the instances of logic gate LG are coupled to / decoupled from the supply voltage TVDD and the reference voltage TVSS simultaneously or sequentially, which are also within the scope of the present disclosure.

[0055] Via the configuration discussed above, the IC layout / device 500 including instances of IC layout / devices 100A and 100C is capable of achieving the benefits discussed above for Figure 1A-1C discussion.

[0056] Figure 6 is a diagram of an IC layout 600 and a corresponding IC device 600 according to some embodiments. In addition to the IC layout / device 600, Figure 6 also includes X and Y directions. In some embodiments, the IC layout 600 is referred to as a planar layout 600.

[0057] The IC layout / device 600 corresponds to a power domain including a supply voltage TVDD and a reference voltage TVSS. The IC layout / device 600 includes multiple instances of a network power switch PSW (a single instance marked for clarity) and multiple instances of IC layout / devices 100A - 100C (represented as IC layout / device 100). Each instance electrically connected to a power distribution network (not shown) is configured to distribute the supply voltage TVDD and the reference voltage TVSS and is configured to receive one or more power gating signals, e.g., the signal PGS discussed above.

[0058] Each instance of the network power switch PSW is coupled between one of the power distribution networks and one or more local distribution networks (not shown) and is configured to receive one or more power gating signals. The IC layout / device 600 includes multiple instances of logic cells / devices (not shown) electrically connected to one or more local distribution networks.

[0059] The IC layout diagram / device 600 includes an example of a network power switch PSW and an IC layout diagram / device 100 configured in a Daisy Chain arrangement, whereby a power-on operation is performed in the order indicated by the arrows, for example, by including one or more delay elements and being configured to propagate more power gating signals in accordance with the arrows.

[0060] In some embodiments, examples of the IC layout diagram 100 are classified as Isolation Cells so that they can be included in the low-power check of an IC layout design method, such as the methods 700 or 800 discussed below for Figure 7 and 8.

[0061] Via the configuration discussed above, the IC layout diagram / device 600 including an example of the IC layout diagram / device 100 can achieve the benefits discussed above for Figure 1A-1C discussion.

[0062] Figure 7 is a flowchart of generating an IC layout diagram according to some embodiments of method 700. In some embodiments, generating the IC layout diagram includes generating all or some of one or more of the IC layout diagrams 100A - 600 discussed above for Figure 1A-6 discussion.

[0063] In some embodiments, some or all of method 700 is performed by a processor of a computer. In some embodiments, some or all of method 700 is performed by the processor 902 of the IC layout diagram generation system 900 discussed below for Figure 9 discussion.

[0064] In some embodiments, one or more operations in method 700 are a subset of the operations or methods of forming an IC device. In some embodiments, one or more operations in method 700 are a subset of the operations of an IC manufacturing flow, such as the manufacturing system 1000 and the IC manufacturing process discussed below for Figure 10 discussion.

[0065] In some embodiments, the operation or method 700 is performed in the order described in Figure 7 . In some embodiments, the operation or method 700 is performed simultaneously and / or in an order different from the order described in Figure 7 . In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations or methods 700.

[0066] In operation 702A, in some embodiments, the layout plan of an IC device (also referred to as the IC layout in some embodiments) is accessed (e.g., retrieved) from a storage device. This layout plan includes two SRAM macros adjacent to an SRAM channel. The SRAM channel includes a local distribution network coupled to a first power distribution network via one or more network power switches.

[0067] At operation 702B, in some embodiments, the local distribution network (e.g., configured to distribute voltage VVDD) and one or more network power switches (e.g., power switch PSW) are removed from the SRAM channel.

[0068] In operation 702C, in some embodiments, a special voltage region is created in the SRAM channel by placing a plurality of logic circuits in the SRAM channel. Each logic circuit includes a series arrangement of logic gates and power switches electrically. The power switches are electrically connected to a first power distribution network and a second power distribution network. The first and second power distribution networks are configured to distribute a supply voltage and a reference voltage, such as the voltages TVDD and TVSS discussed above.

[0069] In some embodiments, creating the special voltage region includes creating a memory channel 300C, which includes an example of the IC layout / device 100B discussed above for Figure 3 discussion.

[0070] At operation 704, a cell placement operation is performed. In some embodiments, performing the cell placement operation includes placing one or more examples of the IC layout / devices 100A - 100C discussed above for Figure 1A-1C discussion.

[0071] At operation 706, in some embodiments, a clock signal path routing operation is performed. Performing the routing operation includes configuring a plurality of conductive regions / segments in the IC layout / device, thereby establishing electrical connections to each cell.

[0072] At operation 708, in some embodiments, a power supply and signal path routing operation is performed.

[0073] At operation 710A, in some embodiments, a signoff operation is performed. Performing the signoff operation includes verifying that the IC layout design complies with a plurality of predetermined design criteria, such as one or more electromigration, resistance-based voltage drop, and / or timing criteria.

[0074] In some embodiments, operation 710A includes one or more iterations of the signoff operation after each performance of one or more of the operations 710B - 710D discussed below.

[0075] In some embodiments, operation 710A includes storing the IC layout diagram in a storage device (e.g., after verifying that the IC layout design complies with the plurality of predetermined design criteria, for example, after one or more iterations of operations 710B - 710D have been performed).

[0076] In some embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in an IC Layout Diagram Library, such as the layout diagram library Figure 9 909 of the IC layout diagram generation system 900 discussed below.

[0077] At operation 710B, in some embodiments, one or more instances that do not meet the predetermined design criteria are identified, for example, by determining that a voltage level from a circuit simulation meets or exceeds a predetermined threshold level. Identifying one or more instances includes identifying one or more locations in the IC layout diagram corresponding to these instances.

[0078] At operation 710C, in some embodiments, one or more cells including a power switch are used to replace one or more cells at one or more locations determined in operation 700B. Using one or more replacement cells includes establishing electrical connections between the first and second power distribution networks and the one or more replacement cells.

[0079] In some embodiments, using one or more replacement cells includes using one or more of those in the IC layout diagrams 100A - 100C discussed above Figure 1A-1C above.

[0080] At operation 710D, in some embodiments, a daisy chain configuration is configured, or an existing daisy chain is reconfigured to include one or more replacement cells as discussed above for Figure 6 above.

[0081] By performing all the operations of some or method 700, an IC layout diagram is generated, wherein one or more instances of cells include power switches arranged in series and logic gates, thereby enabling the above for IC layout diagrams / structures 100 and 200.

[0082] Figure 8A and 8B are flowcharts of methods 800A and 800B for generating an IC layout diagram according to some embodiments. Method 800A includes operations 802 - 812, in some embodiments, method 800B includes operation 804, and in some embodiments, it is a subset of operations or method 800A, 806, 810, and 812.

[0083] In some embodiments, generating an IC layout includes generating all or some of one or more of the IC layouts 100A - 600 discussed for Figure 1A-6 discussed for one or more of the IC layouts 100A - 600.

[0084] In some embodiments, some or all of the methods 800A and / or 800B are implemented by a processor of a computer. In some embodiments, some or all of the methods 800A and / or 800B, are implemented by the processor 902 of the IC layout generation system 900 discussed for Figure 9 discussed for the IC layout generation system 900.

[0085] In some embodiments, one or more operations in the methods 800A and / or 800B are a subset of the operations or methods for forming an IC device. In some embodiments, one or more operations in the methods 800A and / or 800B are a subset of the operations of an IC manufacturing flow, e.g., the manufacturing system 1000 discussed for Figure 10 discussed and the IC manufacturing flow discussed for

[0086] In some embodiments, the operations of the methods 800A and / or 800B are performed in accordance with Figure 8A and 8B shown order. In some embodiments, the operations of the methods 800A and / or 800B are performed simultaneously and / or in an order different from the order depicted in Figure 8A and 8B In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations of the methods 800A and / or 800B.

[0087] At operation 802, in some embodiments of method 800A, a first logic cell is modified by adding a first power switch and a first logic gate in series, the first power switch including a first control terminal. Modifying the first logic cell includes storing the modified first logic cell in a storage device, e.g., the cell library 907 of the IC layout generation system 900 discussed for Figure 9 discussed for the IC layout generation system 900.

[0088] In some embodiments, modifying the first logic cell includes generating one of the IC layouts 100A - 100C discussed for Figure 1A-1C discussed above.

[0089] At operation 804, in some embodiments, a plurality of logic cells are placed in an IC layout, each logic cell of the plurality of logic cells including a series arrangement of a power switch and a logic gate. In some embodiments, placing the plurality of logic cells in the IC layout includes placing one or more of the IC layouts 100A - 100C discussed for Figure 1A-1C discussed above and / or placing one or more of the IC layouts 100A - 100C discussed for Figure 4One or more of the IC layouts 400 discussed.

[0090] In some embodiments, placing the plurality of logic cells in an IC layout includes placing the plurality of logic cells in one of the IC layouts 200, 300, 500, or 600 discussed above for Figure 2 , 3 , 5, and 6.

[0091] In some embodiments, placing the plurality of logic cells in an IC layout includes performing one or more of the operations 702A - 704 discussed above for Figure 7 .

[0092] In some embodiments, placing the plurality of logic cells in an IC layout includes retrieving the plurality of logic cells from a storage device, such as the cell library 907 of the IC layout generation system 900 discussed below for Figure 9 . In some embodiments, retrieving the plurality of logic cells from a storage device includes retrieving the logic cells modified in operation 802 of method 800A.

[0093] In operation 806, in some embodiments, electrical connections are established among the logic cells of the plurality of logic cells. The logic cells include a series arrangement of a power switch and a logic gate. Establishing the electrical connections includes: establishing a first electrical connection between a first power distribution network and a first end of the series arrangement of each logic cell of the plurality of logic cells, establishing a second electrical connection between a second power distribution network and a second end of the series arrangement of each logic cell of the plurality of logic cells, and establishing a third electrical connection between a power gating signal network and a control terminal of the power switch of each logic cell of the plurality of logic cells.

[0094] In some embodiments, establishing the electrical connections includes establishing electrical connections between the power distribution networks PDN1, PDN2, and an instance of gating the network PSN power - on signal into the IC layout 100 as discussed above for Figure 2 .

[0095] In operation 808, in some embodiments of method 800A, it is determined that a resistance - based voltage drop corresponding to the logic cells of a previously placed IC layout exceeds a predetermined limit. And, the logic cells include series power switches. For example, in response to this determination, one of the IC layouts 100A - 100C or 400 discussed above for Figure 1C , 4 will be used to replace the previously placed logic cells.

[0096] In some embodiments, replacing the previously placed logic cells in an IC layout includes performing the above - mentioned operations for Figure 7One or more of operations 710A - 710D discussed.

[0097] In some embodiments, replacing a previously placed logic cell with a logic cell including a series power switch includes establishing an electrical connection to a logic cell including a series power switch (e.g., via performing operation 806 discussed above). In some embodiments, replacing a previously placed logic cell includes removing a previously established electrical connection between the previously placed logic cell and a local power distribution network coupled to a power distribution network via a network power switch.

[0098] At operation 810, in some embodiments, an IC layout is stored in a storage device. In some embodiments, storing the IC layout in a storage device includes storing the IC layout in an IC layout library, such as layout library 909 for the IC layout diagram generation system 900 discussed below Figure 9 for the layout diagram of the system 900th generation of the IC layout discussed.

[0099] In some embodiments, storing the IC layout in a storage device includes storing the IC layout in a non - volatile computer - readable memory or cell library (e.g., a database), and / or includes storing the IC layout on a network. In some embodiments, storing the IC layout in a storage device includes storing the IC layout on network 914 for the IC layout generation system 900 discussed below Figure 9 for the IC layout diagram discussed.

[0100] At operation 812, in some embodiments, one or more manufacturing operations are performed based on the IC layout. In some embodiments, performing one or more manufacturing operations includes performing one or more photolithographic exposures based on the IC layout. The following discussion Figure 10 is about performing one or more manufacturing operations based on the IC layout, such as one or more photolithographic exposures.

[0101] By performing all operations of some or methods 800A and / or 800B, an IC layout is generated, where one or more instances of cells include power switches arranged in series with logic gates, thereby enabling the above - mentioned advantages for IC layouts / structures 100 and 200.

[0102] Figure 9 is a block diagram of an (EDA) system 900 according to some embodiments. EDA system 900 can be used to perform some or all of methods 700 and / or 800 discussed above.

[0103] In some embodiments, the EDA system 900 includes an Automatic Placement and Routing (APR) system. The layout diagrams according to one or more embodiments described herein may be implemented via, for example, the system 900 according to multiple embodiments.

[0104] In some embodiments, the EDA system 900 is a general-purpose computing device. The general-purpose computing device includes a hardware processor 902 and a non-transitory computer-readable storage medium 904. The storage medium 904 is encoded with, for example, computer program code 906, that is, a set of executable instructions. Executing the instructions 906 via the hardware processor 902 (at least in part) represents an EDA tool. The EDA tool implements a part or all of the methods described herein according to one or more embodiments (hereinafter, the processes and / or methods mentioned).

[0105] The processor 902 is electrically coupled to the computer-readable storage medium 904 via a bus 908. The processor 902 is also electrically coupled to an Input Output (I / O) interface 910 via the bus 908. A network interface 912 is also electrically connected to the processor 902 via the bus 908. The network interface 912 is connected to a network 914 such that the processor 902 and the computer-readable storage medium 904 can be connected to external components via the network 914. The processor 902 is configured to execute the computer program code 906 encoded in the computer-readable storage medium 904 so that the system 900 can be used to implement a part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 902 is a Central Processing Unit (CPU), a multi-processor, a distributed processing system, an Application Specific Integrated Circuit (ASIC), and / or a suitable processing unit.

[0106] In one or more embodiments, the computer-readable storage medium 904 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 904 includes semiconductor memory or solid-state memory, magnetic tape, removable computer floppy disk, Random Access Memory (RAM), Read-Only Memory (ROM), hard disk, and / or optical disk. In one or more embodiments using an optical disk, the computer-readable storage medium 904 includes a Compact Disc Read-Only Memory (CD-ROM), a Compact Disc Read / Write (CD-R / W), and / or a Digital Video Disc (DVD).

[0107] In one or more embodiments, storage medium 904 stores computer program code 906. The medium 904 storing the computer program code 906 is configured such that system 900 (where such implementation represents (at least in part) an EDA tool) can be used to implement part or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 904 also stores information that helps implement part or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 904 stores a cell library 907 of IC layout cells, including such cells as disclosed herein. In one or more embodiments, the storage medium 904 stores one or more layout diagrams 909 corresponding to one or more layouts disclosed herein.

[0108] EDA system 900 includes an I / O interface 910. The I / O interface 910 is coupled to an external circuit. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor direction keys for transmitting information and commands to the processor 902.

[0109] EDA system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 allows the system 900 to communicate with a network 914 to which one or more other computer systems are connected. The network interface 912 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, WCDMA, etc.; or a wired network interface such as Ethernet, USB, or IEEE - 1364, etc. In one or more embodiments, part or all of the processes and / or methods mentioned are implemented in two or more systems 900.

[0110] System 900 is configured to receive information at the I / O interface 910. The information received via the I / O interface 910 includes one or more of instructions, data, design rules, a library of standard cells, and / or other parameters processed by the processor 902. The information is transmitted to the processor 902 via the bus 908. EDA system 900 is configured to receive information related to a user interface (UI) at the I / O interface 910. The information is stored as UI942 in the computer - readable medium 904.

[0111] In some embodiments, part or all of the processes and / or methods mentioned are implemented as independent software applications executed by a processor. In some embodiments, part or all of the processes and / or methods mentioned are implemented as software applications that are part of an additional software application. In some embodiments, part or all of the processes and / or methods mentioned are implemented as plugins of software applications. In some embodiments, at least one of the processes and / or methods mentioned is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods mentioned are implemented as software applications used by the EDA system 900. In some embodiments, tools such as those available from CADENCE DESIGN SYSTEMS, Inc. or other suitable layout generation tools are used to generate a layout diagram including standard cells.

[0112] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or storage units such as optical discs (e.g., DVDs), magnetic discs such as hard disks, semiconductor memories (such as ROM, RAM), memory cards, etc.

[0113] Figure 10 is a block diagram of an integrated circuit (IC) manufacturing system 1000 and an IC manufacturing process associated therewith. In some embodiments, based on the layout diagram, the manufacturing system 1000 is used to manufacture at least one component in (A) one or more semiconductor masks or (B) at least one layer of a semiconductor integrated circuit.

[0114] In Figure 10In the IC manufacturing system 1000, entities such as a Design House 1020, a Mask House 1030, and an IC manufacturer / fabricator (Fab) 1050 interact with each other in the design, development, and manufacturing cycle and / or manufacturing-related services. The IC device 1060. The entities in the system 1000 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet, the Internet, etc. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the Design House 1020, the Mask House 1030, and the IC Fab 1050 are owned by a larger company. In some embodiments, two or more of the Design House 1020, the Mask House 1030, and the IC Fab 1050 coexist in a common facility and use common resources.

[0115] The Design House (or design team) 1020 generates an IC design layout 1022, for example, including one or more of the IC layouts 100A - 600 discussed above for Figure 1A-6 The IC design layout 1022 includes various geometric patterns designed for the IC device 1060. The geometric patterns correspond to patterns of metal oxides or semiconductor layers, which constitute various components of the IC device 1060 to be manufactured. The various layers combine to form various IC features. For example, a portion of the IC design layout 1022 includes a semiconductor substrate (such as a silicon chip) and various material layers disposed on the semiconductor substrate. The Design House 1020 implements an appropriate design process to form the IC design layout 1022. The design process includes one or more of logic design, physical design, or placement and routing. The IC design layout 1022 is presented in one or more data files having geometric patterns. For example, the IC design layout 1022 can be represented in the GDSII file format or the DFII file format.

[0116] The mask mechanism 1030 includes data preparation 1032 and mask fabrication 1044. The mask mechanism 1030 fabricates one or more masks 1045 from the IC design layout 1022 for the various layers used to fabricate the IC device 1060. The mask mechanism 1030 performs mask data preparation 1032, in which the IC design layout 1022 is converted into a representative data file (RDF). The mask data preparation 1032 provides the RDF to the mask fabrication 1044. The mask fabrication 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1045 or a semiconductor wafer 1053. The design layout 1022 is manipulated by the mask data preparation 1032 to conform to the specific characteristics of the mask writer and / or the requirements of the IC foundry 1050. In Figure 10 this, the mask data preparation 1032 and the mask fabrication 1044 are shown as separate elements. In some embodiments, the mask data preparation 1032 and the mask fabrication 1044 may be collectively referred to as mask data preparation.

[0117] In some embodiments, the mask data preparation 1032 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. The OPC adjusts the IC design layout 1022. In some embodiments, the mask data preparation 1032 includes further resolution enhancement technology (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0118] In some embodiments, the mask data preparation 1032 includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout 1022 that has undergone the process in the OPC. These rules include certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for the lithography implementation effects during mask fabrication 1044, which may undo some of the modifications made by the OPC to meet the mask creation rules.

[0119] In some embodiments, lithography process checking (LPC) is included in mask data preparation 1032, which simulates the processes to be implemented by the IC foundry 1050 to fabricate the IC device 1060. LPC simulates such processes based on the IC design layout 1022 to create a simulated fabricated device, such as the IC device 1060. The process parameters in the LPC simulation can include parameters associated with the various processes of the IC manufacturing cycle, parameters associated with the tools used for IC manufacturing, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc. or combinations thereof. In some embodiments, after establishing the simulated fabricated device via LPC, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 1022.

[0120] It should be understood that the above description of mask data preparation 1032 has been simplified for the purpose of clarity. In some embodiments, additional features, such as logic operations (LOP), are included in data preparation 1032 to modify the IC design layout 1022 according to the manufacturing rules. Additionally, the processes applied to the IC design layout 1022 during data preparation 1032 can be implemented in various different orders.

[0121] After mask data preparation 1032 and during mask fabrication 1044, a mask 1045 or a set of masks 1045 is fabricated based on the modified IC design layout 1022. In some embodiments, mask fabrication 1044 includes performing one or more photolithography exposures based on the IC design layout 1022. In some embodiments, an electron beam (e-beam) or a mechanism of multiple electron beams is used to form patterns on a mask (photomask or reticle) 1045 based on the modified IC design layout 1022. The mask 1045 can be formed via a variety of techniques. In some embodiments, the mask 1045 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on a chip is blocked by the opaque regions and passes through the transparent regions. In one example, the binary mask version of the mask 1045 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1045 is formed using a phase shift technique. In the phase shift mask (PSM) version of the mask 1045, each feature in the pattern formed on the phase shift mask is configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 1044 is used in various processes. As shown by way of example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer 1053 and in an etching process to form various etched regions in the semiconductor wafer 1053 and / or other suitable processes.

[0122] An IC foundry 1050 is an IC manufacturing business that includes one or more manufacturing facilities for the manufacture of various different IC products. In some embodiments, the IC foundry 1050 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing for the interconnect and packaging (back-end) of IC products (back-end-of-line (BEOL) manufacturing), and a third manufacturing facility may provide other services for a foundry business.

[0123] IC foundry 1050 includes manufacturing tools 1052 configured to perform various manufacturing operations on semiconductor wafer 1053 such that IC devices 1060 are manufactured according to a mask (e.g., mask 1045). In various embodiments, manufacturing tools 1052 include one or more of a chip stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etch system, a chip cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0124] IC foundry 1050 manufactures IC devices 1060 using mask(s) 1045 fabricated by mask mechanism 1030. Thus, IC foundry 1050 uses IC design layout 1022 at least indirectly to manufacture IC devices 1060. In some embodiments, semiconductor wafer 1053 is fabricated by IC foundry 1050 using mask(s) 1045 to form IC devices 1060. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 1053 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0125] In some embodiments, an IC device includes a first interconnect structure configured to distribute a supply voltage, a second interconnect structure configured to distribute a reference voltage, a third interconnect structure configured to distribute a first power gating signal, and a plurality of logic circuits. Each logic circuit of the plurality of logic circuits includes a power switch. The power switch is serially coupled to a logic gate between the first interconnect structure and the second interconnect structure. And, the power switch includes a control terminal coupled to the third interconnect structure. In some embodiments, the logic gate of each logic circuit of the plurality of logic circuits includes one or more of an inverter, a buffer, a transmission gate, an AND gate, a NAND gate, an OR gate, a NOR gate, or an exclusive OR gate. In some embodiments, the power switch of the first logic circuit of the plurality of logic circuits includes: a PMOS transistor coupled between the logic gate and the first interconnect structure, wherein the control terminal includes the gate of the PMOS transistor. In some embodiments, the power switch of the first logic circuit of the plurality of logic circuits includes: an NMOS transistor coupled between the logic gate and the second interconnect structure, wherein the control terminal includes the gate of the NMOS transistor. In some embodiments, the plurality of logic circuits includes a memory channel coupled between a first and a second memory macro, and the logic gate of each logic circuit of the plurality of logic circuits includes an inverter. In some embodiments, the first logic circuit of the plurality of logic circuits includes a multi-bit synchronizer flip-flop circuit, the multi-bit synchronizer flip-flop includes a plurality of single-bit synchronizer flip-flops, wherein the power switch is the first power switch of the plurality of power switches of the multi-bit synchronizer flip-flop circuit, the logic gate is the first logic gate of the plurality of logic gates of the multi-bit synchronizer flip-flop circuit, each power switch of the plurality of power switches is serially coupled to a corresponding logic gate, the corresponding logic gate is located between the first and the second interconnect structures, and each of the plurality of single-bit synchronizer flip-flops includes the corresponding logic gate of the plurality of logic gates.In some embodiments, the third internal wiring structure is further configured to distribute a second power gating signal that is complementary to the first power gating signal. The first logic circuit of the plurality of logic circuits includes: the power switch includes a PMOS transistor, and the PMOS transistor is coupled between the logic gate and the first internal wiring structure; and the control terminal includes the gate of the PMOS transistor, and the gate of the PMOS transistor is configured to receive the first power gating signal. The second logic circuit of the plurality of logic circuits includes: the power switch includes an NMOS transistor, and the NMOS transistor is coupled between the logic gate and the second internal wiring structure; and the control terminal includes the gate of the NMOS transistor, and the gate of the NMOS transistor is configured to receive the second power gating signal.

[0126] In some embodiments, a method of generating an integrated circuit layout diagram includes: placing a plurality of logic cells in the integrated circuit layout diagram, wherein each logic cell of the plurality of logic cells includes a series arrangement of a power switch and a logic gate; establishing a first electrical connection, wherein the first electrical connection is between a first power distribution network and a first end of the series arrangement of each logic cell of the plurality of logic cells; establishing a second electrical connection, wherein the second electrical connection is between a second power distribution network and a second end of the series arrangement of each logic cell of the plurality of logic cells; establishing a third electrical connection, wherein the third electrical connection is between a power gating signal network and a control terminal of the power switch of each logic cell of the plurality of logic cells; and storing the integrated circuit layout diagram in a storage device, wherein the integrated circuit layout diagram includes the plurality of logic cells. In some embodiments, the method of generating an integrated circuit layout diagram further includes: adding, in series, a first power switch in series with a first logic gate to modify a first logic cell, the first power switch including a first control terminal; storing the modified first logic cell in a first storage device, the first storage device being the storage device or another storage device; and receiving, from the first storage device, the modified first logic cell, wherein the modified first logic cell is a logic cell of the plurality of logic cells, and the series arrangement of the power switch and the logic gate of the logic cell of the plurality of logic cells includes the first power switch in series with the first logic gate. In some embodiments, the method of generating an integrated circuit layout diagram further includes: making a determination that a resistance-based voltage drop corresponding to a previously placed logic cell of the integrated circuit layout diagram exceeds a predetermined limit, wherein placing the plurality of logic cells in the integrated circuit layout diagram includes: in response to the determination, replacing the previously placed logic cell with a logic cell of the plurality of logic cells. In some embodiments, wherein the first electrical connection established between the first power distribution network and the first end of the series arrangement of each logic cell of the plurality of logic cells includes: removing a previously established electrical connection therebetween, the previously established electrical connection being between the previously placed logic cell and a third power distribution network coupled to the first power distribution network via a network power switch. In some embodiments, wherein the integrated circuit layout diagram includes a plurality of memory macros, placing the plurality of logic cells in the integrated circuit layout diagram includes: placing the plurality of logic cells between a first memory macro and a second memory macro of the plurality of memory macros, and the logic gate of each logic cell of the plurality of logic cells includes an inverter configured to couple a corresponding first boundary cell of the first memory macro to a corresponding second boundary cell of the second memory macro.In some embodiments, a first logic cell of the plurality of logic cells includes: a multi-bit synchronous flip-flop circuit including a plurality of single-bit synchronous flip-flops, wherein the series arrangement is a first series arrangement of a plurality of series arrangements of corresponding power switches and corresponding logic gates of the multi-bit synchronous flip-flop circuit, each of the plurality of single-bit synchronizer flip-flops includes a respective logic gate of the plurality of logic gates, establishing the first electrical connection includes: establishing the first electrical connection between the first power distribution network and a first end of each of the plurality of series arrangements, establishing the second electrical connection includes: establishing the second electrical connection between the second power distribution network and a second end of each of the plurality of series arrangements, and establishing the third electrical connection includes: establishing the third electrical connection between the power gating signal network and a control terminal of each power switch of each of the plurality of series arrangements. In some embodiments, wherein the first power distribution network is configured to distribute a supply voltage, the second power distribution network is configured to distribute a reference voltage, the first electrical connection established between the first power distribution network and the first end of the series arrangement of the first logic cell of the plurality of logic cells includes: establishing the first electrical connection to the power switch including a PMOS transistor, and the third electrical connection established between the power gating signal network and the control terminal of the power switch of the first logic cell of the plurality of logic cells includes establishing the third electrical connection to the gate of the PMOS transistor. In some embodiments, wherein the second electrical connection established between the second power distribution network and the second end of the series arrangement of the second logic cell of the plurality of logic cells includes establishing the second electrical connection to the power switch including an NMOS transistor, and the third electrical connection established between the power gating signal network and the control terminal of the power switch of the second logic cell of the plurality of logic cells includes establishing the third electrical connection to the gate of the NMOS transistor.

[0127] In some embodiments, an electronic design automation system includes: a processor; and a non-transitory computer-readable storage medium including computer program code for one or more programs, the non-transitory computer-readable storage medium and the computer program code being configured to, with the processor, cause the processor to: place a first logic cell and a second logic cell in an integrated circuit layout, wherein the second logic cell includes a series arrangement of a power switch and a logic gate; wire a first electrical connection and a second electrical connection of each of a first power distribution network and a second power distribution network to the first logic cell, wherein the first power distribution network is coupled to a third power distribution network via a network power switch, and the third power distribution network is configured to distribute one of a supply voltage or a reference voltage; wire a third electrical connection and a fourth electrical connection of each of the second power distribution network and the third power distribution network to the second logic cell; and store the integrated circuit layout in a storage device, the integrated circuit layout including the plurality of logic cells. In some embodiments, wherein the non-transitory computer-readable storage medium and the computer program code are configured to, with the processor, further cause the processor to: place the second logic cell by replacing a third logic cell with the second logic cell classified as an isolation cell. In some embodiments, wherein before wiring the first electrical connection and the second electrical connection to the first logic cell, the non-transitory computer-readable storage medium and the computer program code are configured to, with the processor, further cause the processor to: place a plurality of second logic cells in the integrated circuit layout, wherein each second logic cell of the plurality of second logic cells includes a series arrangement of a power switch and a logic gate; and wire a plurality of fifth electrical connections and a plurality of sixth electrical connections of each of the second power distribution network and the third power distribution network to the plurality of second logic cells. In some embodiments, wherein the non-transitory computer-readable storage medium and the computer program code are configured to, with the processor, further cause the processor to: wire the third electrical connection and the fourth electrical connection by adding the network power switch and the second logic cell in a daisy chain arrangement. In some embodiments, wherein the non-transitory computer-readable storage medium and the computer program code are configured to, with the processor, further cause the processor to: wire a fifth electrical connection of a power gating signal network to a control terminal of the power switch of the second logic cell.

[0128] The foregoing general description and examples enable those skilled in the art to better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, characterized in that, Comprising: A first internal wiring structure configured to distribute a power supply voltage; A second internal wiring structure configured to distribute a reference voltage; A third internal wiring structure configured to distribute a first power gating signal; And A plurality of logic circuits, wherein each logic circuit of the plurality of logic circuits comprises: A power switch serially coupled between a logic gate between the first internal wiring structure and the second internal wiring structure, Wherein the power switch comprises a control terminal coupled to the third internal wiring structure.

2. The integrated circuit device according to claim 1, wherein Wherein the logic gate in each logic circuit of the plurality of logic circuits comprises one or more of an inverter, a buffer, a transmission gate, and a gate, a NAND gate, an OR gate, a NOR gate, and an exclusive OR gate.

3. The integrated circuit device according to claim 1, characterized in that, Wherein the power switch of the first logic circuit of the plurality of logic circuits comprises: A PMOS transistor coupled between the logic gate and the first internal wiring structure, Wherein the control terminal comprises the gate of the PMOS transistor.

4. The integrated circuit device according to claim 1, wherein Wherein the power switch of the first logic circuit of the plurality of logic circuits comprises: An NMOS transistor coupled between the logic gate and the second internal wiring structure, Wherein the control terminal comprises the gate of the NMOS transistor.

5. The integrated circuit device according to claim 1, wherein Wherein The plurality of logic circuits includes a memory channel coupled between a first and a second memory macro, and The logic gate in each logic circuit of the plurality of logic circuits includes an inverter.

6. The integrated circuit device according to claim 1, wherein Wherein the first logic circuit of the plurality of logic circuits includes a multi-bit synchronizer flip-flop circuit, the multi-bit synchronizer flip-flop includes a plurality of single-bit synchronizer flip-flops, wherein The power switch is the first power switch of the plurality of power switches of the multi-bit synchronizer flip-flop circuit, The logic gate is the first logic gate of the plurality of logic gates of the multi-bit synchronizer flip-flop circuit, Each of the plurality of power switches is serially coupled to a corresponding logic gate located between the first and second internal wiring structures and the second internal wiring structure, and Each of the plurality of single-bit synchronizer flip-flops includes the corresponding logic gate of the plurality of logic gates.

7. The integrated circuit device according to claim 1, wherein Wherein The third internal wiring structure is further configured to distribute a second power gating signal complementary to the first power gating signal, The first logic circuit of the plurality of logic circuits includes: The power switch includes a PMOS transistor coupled between the logic gate and the first internal wiring structure; and The control terminal includes the gate of the PMOS transistor, and the gate of the PMOS transistor is configured to receive the first power gating signal, and The second logic circuit of the plurality of logic circuits includes: The power switch includes an NMOS transistor coupled between the logic gate and the second internal wiring structure; and The control terminal includes the gate of the NMOS transistor, and the gate of the NMOS transistor is configured to receive the second power gating signal.

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