Display panel

Abstract

Provided is a display panel including: a base substrate; a circuit element layer provided on the base substrate; a pixel defining layer disposed on the circuit element layer and including a light emitting opening; a light emitting element disposed on the circuit element layer and including a first electrode, a second electrode facing the first electrode, and a functional layer disposed between the first electrode and the second electrode; the metal pattern layer is arranged on the pixel defining layer; and a low thermal conductive layer disposed between the pixel defining layer and the metal pattern layer, thereby having excellent display quality.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0117412, filed on September 5, 2023, the entire contents of which are incorporated herein by reference. Technical field

[0003] An embodiment relates to a display panel and a method of manufacturing a display panel. More specifically, the embodiment relates to a display panel including a light - emitting element having a common layer and a method of manufacturing the display panel. Background art

[0004] Various display devices are being developed for multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation systems, gaming consoles, and wearable devices. Such display devices may include a display panel for displaying an image. The display panel uses so - called self - emissive display elements to display an image by emitting light from a light - emitting material including an organic compound, quantum dots, etc. in a light - emitting layer disposed between electrodes facing each other.

[0005] For example, recently, as the demand for high definition and portability of multimedia electronic devices has increased, there is a need for a display panel that can reduce its size and provide excellent high - resolution display quality. Summary of the utility model

[0006] This embodiment provides a display panel having excellent display quality.

[0007] The embodiment also provides a high - resolution display panel having excellent display quality.

[0008] The embodiment also provides a method of manufacturing a display panel, which can improve the display quality by not only minimizing damage to the light - emitting layer and the common layer in the light - emitting region but also effectively disconnecting an organic film provided as the common layer in an adjacent light - emitting region.

[0009] However, the embodiments are not limited to the embodiments set forth herein. The above and other embodiments will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0010] One embodiment provides a display panel, comprising: a base substrate; a circuit element layer disposed on the base substrate; a pixel defining layer disposed on the circuit element layer and including a light - emitting opening; a light - emitting element disposed on the circuit element layer and including a first electrode, a second electrode facing the first electrode, and a functional layer disposed between the first electrode and the second electrode; a metal pattern layer disposed on the pixel defining layer; and a low - thermal - conductivity layer disposed between the pixel defining layer and the metal pattern layer.

[0011] In one embodiment, the low thermal conductivity layer may have a thermal conductivity of about 1.0 W / mK or less.

[0012] In one embodiment, the functional layer may not overlap with the metal pattern layer.

[0013] In one embodiment, the functional layer may include a light-emitting layer and an organic layer arranged on at least one of the upper and lower parts of the light-emitting layer, wherein the organic layer may overlap with the light-emitting opening and the portion of the pixel defining layer adjacent to the light-emitting opening, and be spaced apart from the metal pattern layer.

[0014] In one embodiment, the low thermal conductivity layer may include a polymer amorphous carbon film.

[0015] In one embodiment, the polymer amorphous carbon film has sp 3 The ratio of carbon bonds may be in the range of about 50% to about 70%.

[0016] In one embodiment, the low thermal conductivity layer may have a refractive index of about 1.75 or less at a wavelength of about 550 nm and a thermal conductivity of about 1.2 g / cm 3 to about 1.6g / cm 3 density within the range of .

[0017] In one embodiment, in a cross section perpendicular to the base substrate, a first width of the metal pattern layer in one direction may be smaller than a second width of the pixel defining layer in the same direction.

[0018] In one embodiment, the first width may be about 1 / 2 or less of the second width.

[0019] In one embodiment, the width of the metal pattern layer in one direction may be smaller than the width of the low thermal conductivity layer in the direction.

[0020] In one embodiment, the low thermal conductivity layer may cover the upper surface and side surfaces of the pixel defining layer.

[0021] In one embodiment, the low thermal conductivity layer may be disposed on an upper surface of the pixel defining layer, and a side surface of the pixel defining layer may be covered by the functional layer.

[0022] In one embodiment, a concave portion may be formed on an upper surface of the pixel defining layer, and the low thermal conductive layer may be disposed in the concave portion.

[0023] In one embodiment, a first recessed portion may be formed on an upper surface of the pixel defining layer, the low thermal conductivity layer may be disposed in the first recessed portion, a second recessed portion may be formed on an upper surface of the low thermal conductivity layer, and the metal pattern layer may be disposed in the second recessed portion.

[0024] In one embodiment, a display panel divided in a plan view into a plurality of light emitting regions spaced apart from each other and a peripheral region disposed between the plurality of light emitting regions may include: a base substrate; a circuit element layer disposed on the base substrate; a pixel defining layer disposed on the circuit element layer and including a light emitting opening overlapping with each of the plurality of light emitting regions; a plurality of light emitting elements including a first electrode disposed on the circuit element layer, a second electrode facing the first electrode, and a functional layer disposed between the first electrode and the second electrode; a metal pattern layer corresponding to the peripheral region and disposed on the pixel defining layer; and a low thermal conductivity layer directly disposed between the pixel defining layer and the metal pattern layer.

[0025] In one embodiment, the first electrodes of the plurality of light emitting elements may overlap with each of the plurality of light emitting regions, the second electrodes may be provided as a common layer extending over the plurality of light emitting elements, and the functional layer may not overlap with the metal pattern layer and may be disposed in the plurality of light emitting regions and a portion of the peripheral region adjacent to the plurality of light emitting regions.

[0026] In one embodiment, the functional layer may include: a light emitting layer; a hole transport region disposed between the first electrode and the light emitting layer; and an electron transport region disposed between the light emitting layer and the second electrode, wherein the light emitting layer may be disposed in the light emitting opening, and at least one of the hole transport region and the electron transport region may be disposed in the light emitting opening and extend above an upper surface of the pixel defining layer adjacent to the light emitting opening.

[0027] In one embodiment, the plurality of light emitting regions may include a first light emitting region, a second light emitting region, and a third light emitting region that emit light in different wavelength ranges, and the plurality of light emitting elements may include a first light emitting layer overlapping with the first light emitting region, a second light emitting layer overlapping with the second light emitting region, and a third light emitting layer overlapping with the third light emitting region, wherein the first light emitting layer, the second light emitting layer, and the third light emitting layer may include different light emitting materials, and the plurality of light emitting elements may include the same hole transport region and the same electron transport region for each other.

[0028] In one embodiment, at least one edge portion of the hole transport region and the electron transport region, which is disposed to extend above the upper surface of the pixel defining layer, may be spaced apart from the metal pattern layer.

[0029] In one embodiment, in a plan view, a metal layer boundary line defined by the edge portion and an edge portion of the metal pattern layer may be located in the peripheral region, and the edge portion may be closer to the plurality of light emitting regions than the metal layer boundary line.

[0030] In one embodiment, the low thermal conductivity layer may include a polymer type amorphous carbon film.

[0031] In one embodiment, the proportion of sp 3 carbon bonds in the polymer type amorphous carbon film may be in the range of about 50% to about 70%, and the low thermal conductivity layer may have a refractive index of about 1.75 or less at a wavelength of about 550 nm and a density in the range of about 1.2 g / cm 3 to about 1.6 g / cm 3 range.

[0032] In one embodiment, in a cross-section perpendicular to the substrate substrate, a first width of the metal pattern layer in one direction may be smaller than each of a second width of the upper surface of the pixel defining layer adjacent to the metal pattern layer and a third width of the upper surface of the low thermal conductivity layer adjacent to the metal pattern layer in the direction.

[0033] In one embodiment, in a plan view, the size of the metal pattern layer may be smaller than the size of the pixel defining layer.

[0034] In one embodiment, a method of manufacturing a display panel may include: forming a first electrode on a circuit element layer; forming a pixel defining layer on the circuit element layer; forming a low thermal conductivity layer on the pixel defining layer; forming a metal pattern layer on the low thermal conductivity layer to overlap with the pixel defining layer; providing a preliminary functional layer to overlap with the pixel defining layer and the first electrode; forming a functional layer by applying a current to the metal pattern layer to remove a portion of the preliminary functional layer that overlaps with the metal pattern layer; forming a second electrode to cover the functional layer and the metal pattern layer; and forming a encapsulation layer on the second electrode.

[0035] In one embodiment, the metal pattern layer may be a joule heating wire, and forming the functional layer by removing the portion of the preliminary functional layer may include: removing the portion of the preliminary functional layer by sublimating the portion of the preliminary functional layer with heat generated in the metal pattern layer.

[0036] In one embodiment, the formation of the low thermal conductivity layer may include forming a polymer-type amorphous carbon film using a deposition facility with a hydrocarbon gas.

[0037] In one embodiment, the metal pattern layer may have a width smaller than the width of the low thermal conductivity layer in one direction.

[0038] In one embodiment, the functional layer may be formed not to overlap with the metal pattern layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings are included to provide a further understanding of the inventive concept of the present disclosure and are incorporated into and constitute a part of the specification. The drawings illustrate embodiments and, together with the specification, are used to explain the principles of the inventive concept of the present disclosure. In the drawings:

[0040] Figure 1A is a schematic perspective view of an electronic device according to one embodiment;

[0041] Figure 1B is an exploded schematic perspective view of an electronic device according to one embodiment;

[0042] Figure 2A is a schematic perspective view of an electronic device according to one embodiment;

[0043] Figure 2B is an exploded schematic perspective view of an electronic device according to one embodiment;

[0044] Figure 3 is a schematic cross-sectional view of a display panel according to one embodiment;

[0045] Figure 4 is a schematic plan view of a display panel according to one embodiment;

[0046] Figure 5 is a schematic plan view of a part of a display panel according to one embodiment;

[0047] Figure 6 is a schematic cross-sectional view of a part of a display panel according to one embodiment;

[0048] Figure 7 is a schematic cross-sectional view of a part of a display panel according to one embodiment;

[0049] Figure 8A is a schematic cross-sectional view of a light-emitting element according to one embodiment;

[0050] Figure 8B is a schematic cross-sectional view of a light-emitting element according to one embodiment;

[0051] Figure 9is a schematic cross-sectional view illustrating a part of a display panel according to an embodiment;

[0052] Figure 10 is a schematic cross-sectional view illustrating a part of a display panel according to an embodiment;

[0053] Figure 11 is a schematic plan view of a part of a display panel according to an embodiment;

[0054] Figure 12 is a schematic cross-sectional view of a part of a display panel according to an embodiment;

[0055] Figure 13 is a schematic cross-sectional view of a part of a display panel according to an embodiment;

[0056] Figure 14 is a schematic cross-sectional view of a part of a display panel according to an embodiment;

[0057] Figure 15 is a schematic cross-sectional view of a part of a display panel according to an embodiment; and

[0058] Figures 16A to 16H illustrate steps of a method of manufacturing a display panel according to an embodiment, respectively. Specific Embodiments

[0059] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable terms that are non-limiting examples of the apparatus or method disclosed herein. However, it will be apparent that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, the various embodiments need not be exclusive and need not limit the present disclosure. For example, the specific shapes, configurations, and characteristics of one embodiment may be used or implemented in another embodiment.

[0060] Unless otherwise specified, the illustrated embodiments should be understood to provide features of the present disclosure. Accordingly, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged, and / or rearranged in other ways without departing from the scope of the present disclosure.

[0061] The use of cross-hatching and / or shading in the figures is generally used to clarify the boundaries between adjacent elements. For this reason, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for a particular material, material property, size, ratio, commonality between the illustrated elements, and / or any other characteristic, attribute, property, etc. of the elements, unless otherwise stated. Additionally, in the figures, for clarity and / or descriptive purposes, the dimensions and relative dimensions of elements may be exaggerated. When embodiments can be implemented differently, the specific process orders may be performed in an order different from that described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to that described. Also, like reference numerals denote like elements.

[0062] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connected" can refer to physical, electrical, and / or fluid connections with or without intervening elements. For the purposes of this disclosure, "at least one of A and B" can be understood to mean only A, only B, or any combination of A and B. Also, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0063] Although terms such as "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure.

[0064] Spatial relative terms such as "beneath", "below", "under", "lower", "above", "upper", "on top of", "higher" and "side" (e.g., as in "side wall") may be used herein for descriptive purposes to describe, for example, the relationship of one element to another element as illustrated in the figures. Except for the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device during use, operation and / or manufacturing. For example, if the device in the figures is turned over, an element described as "beneath" or "below" another element or feature would then be oriented "above" the other element or feature. Thus, the term "beneath" can encompass both an orientation above and below. In addition, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatial relative descriptors used herein should be interpreted accordingly.

[0065] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, the terms "comprises" and / or "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as terms of degree, and as such, are used to interpret the inherent deviations of measured, calculated and / or provided values that would be recognized by a person of ordinary skill in the art.

[0066] Various embodiments are described herein with reference to sectional views and / or exploded views that are schematic illustrations of embodiments and / or intermediate structures. As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments disclosed herein are not necessarily to be construed as limited to the particular illustrated regional shapes, but include shape deviations resulting, for example, from manufacturing. In this manner, the regions illustrated in the figures are schematic in nature and the shapes of these regions may not reflect the actual shape of the regions of the device, and as such, are not necessarily intended to be limiting.

[0067] In accordance with the convention in the art, some embodiments are described and illustrated in the drawings in the form of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing technologies or other manufacturing technologies. In the case where the blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware or as a combination of dedicated hardware performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) performing other functions. Moreover, each block, unit, and / or module of some embodiments can be physically divided into two or more interacting and discrete blocks, units, and / or modules without departing from the scope of the present disclosure. In addition, the blocks, units, and / or modules of some embodiments can be physically combined into more complex blocks, units, and / or modules without departing from the scope of the present disclosure.

[0068] Hereinafter, embodiments will be described with reference to the drawings.

[0069] Figure 1A is a schematic perspective view of an electronic device according to an embodiment. Figure 1B is an exploded schematic perspective view of an electronic device according to an embodiment. Figure 2A is a schematic perspective view of an electronic device according to an embodiment, and Figure 2B is an exploded schematic perspective view of an electronic device according to an embodiment.

[0070] An electronic device DD according to an embodiment can be activated according to an electrical signal and display an image. For example, the electronic device DD can be a small or medium-sized device such as a monitor, laptop computer, personal digital terminal, car navigation unit, game console, smart phone, tablet computer, and camera, as well as a large device such as a television and an external billboard. However, these are presented only as examples and are not limited to any one embodiment as long as they do not depart from the concept of the present disclosure.

[0071] In Figure 1A and Figure 1B an electronic device DD according to an embodiment is illustrated as a smart phone. For example, Figure 2A and Figure 2B illustrate that an electronic device HMD according to an embodiment is a wearable display device.

[0072] An electronic device DD according to an embodiment may be rigid or flexible. The term "flexible" refers to the property of being bendable. For example, the flexible electronic device DD may include a bendable device, a rollable device, or a foldable device.

[0073] Figure 1A The following figures illustrate a first direction DR1 to a third direction DR3, and the directions represented by the first to third directions DR1, DR2, and DR3 described herein are relative concepts and may be converted to other directions. In the description, the first direction DR1 and the second direction DR2 may be orthogonal to each other, and the third direction DR3 may be a normal direction with respect to the plane defined by the first direction DR1 and the second direction DR2.

[0074] The thickness direction of the electronic device DD may be parallel to the third direction DR3, which is the normal direction with respect to the plane defined by the first direction DR1 and the second direction DR2. In the description, the front (or upper) surface and the rear (or lower) surface of the components of the electronic device DD may be defined based on the third direction DR3. The front (or upper) surface and the rear (or lower) surface of each component of the electronic device DD may face each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3. The separation distance between the front surface and the rear surface defined along the third direction DR3 may correspond to the thickness of the component.

[0075] In the description, the expression "on a plane" or "in a plan view" may be defined as being observed in the third direction DR3. In the description, the expression "in a cross-section" may be defined as being observed in the first direction DR1 or the second direction DR2. The directions represented by the first to third directions DR1, DR2, and DR3 are relative concepts and may be converted to other directions.

[0076] Reference Figure 1A and Figure 1B , an electronic device DD according to an embodiment may display an image IM through a display surface FS. The image IM may include a still image and a moving image. Figure 1A Illustrate a viewing window and an icon as examples of the image IM. The display surface FS for displaying the image IM may correspond to the front surface of the electronic device DD.

[0077] Reference Figure 1B , an electronic device DD according to an embodiment may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to form the exterior of the electronic device DD.

[0078] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define (or form) the display surface FS of the electronic device DD. The display surface FS may include a transmissive region TA and a bezel region BZA. The transmissive region TA may be an optically transparent region. For example, the transmissive region TA may have a visible light transmittance of about 90% or greater.

[0079] Compared with the transmissive region TA, the bezel region BZA may have a relatively low light transmittance. The bezel region BZA may define (or form) the shape of the transmissive region TA. The bezel region BZA may be adjacent to the transmissive region TA and surround the transmissive region TA. In another example, the bezel region BZA may be omitted. The window WP may include at least one functional layer such as an anti-fingerprint layer, a hard coat, and an anti-reflection layer, but the embodiments are not limited thereto.

[0080] The display module DM may be disposed below the window WP. The display module DM may generate an image IM. The image IM generated by the display module DM may be displayed on the display surface IS of the display module DM and may be visually recognized by a user from the outside through the transmissive region TA.

[0081] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be activated according to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be covered by the bezel region BZA and may not be visually recognized from the outside.

[0082] The housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide an internal space. The display module DM may be accommodated in the internal space.

[0083] The housing HAU may include a material having relatively high rigidity. For example, the housing HAU may include a frame and / or a plate made of glass, plastic, metal, or a combination thereof. The housing HAU may reliably protect the components of the electronic device DD accommodated in the internal space from external impacts.

[0084] Reference Figure 1B , according to an embodiment, the display module DM may include a display panel DP and an input sensor ISL. For example, according to an embodiment, the electronic device DD may further include a protection member disposed on the lower surface of the display panel DP, or an anti-reflection member and / or an optical member disposed on the upper surface of the input sensor ISL.

[0085] The input sensor ISL can obtain coordinate information of an external input. The input sensor ISL can have a multi-layer structure. The input sensor ISL can include a single-layer conductive layer or a multi-layer conductive layer. The input sensor ISL can include a single-layer insulating layer or a multi-layer insulating layer. The input sensor ISL can sense an external input, for example, in a capacitive manner. In the present disclosure, the operation mode of the input sensor ISL is not limited thereto, and in one embodiment, the input sensor ISL can sense an external input in an electromagnetic induction manner or a pressure sensing manner. The input sensor ISL can be disposed (e.g., directly disposed) on the encapsulation layer TFE of the display panel DP to be described later (see Figure 3 ). In the description, the expression "component A is directly disposed on component B" means that no adhesive layer is disposed between component A and component B. In another embodiment, the input sensor ISL can be omitted.

[0086] Figure 2A is a schematic perspective view of an electronic device HMD according to an embodiment. Figure 2B is an exploded schematic perspective view of a part of an electronic device HMD according to an embodiment.

[0087] In Figure 2A and Figure 2B The electronic device HMD illustrated according to an embodiment can be activated according to an electrical signal and is a wearable device. The wearable device can be a device worn on a user's body and can include a head-mounted display (HMD) device that implements extended reality (XR). Figure 2A and Figure 2B illustrate that the electronic device HMD is a head-mounted display device, but the embodiment is not limited thereto.

[0088] In Figure 2A and Figure 2B The electronic device HMD illustrated according to an embodiment is a display device worn on a user's head. The electronic device HMD can provide an image in a state where the user's actual peripheral vision is blocked. A user wearing the electronic device HMD can more easily immerse in virtual reality.

[0089] The electronic device HMD can include a main body unit HS, a strap STR, a padding part PP, and a display panel DP. For example, the electronic device HMD can include various sensors and cameras.

[0090] The main body unit HS can be worn on a user's head. The display panel DP for displaying an image, an acceleration sensor, etc. can be accommodated in the main body unit HS. The acceleration sensor can detect the movement of the user and send the detected signal to the display panel DP. Accordingly, the display panel DP can provide an image corresponding to a change in the user's gaze. Thus, the user can experience virtual reality similar to actual reality.

[0091] In the main unit HS, components with various functions other than those described above can be accommodated. For example, a control unit for adjusting volume or screen brightness can be additionally provided outside the main unit HS. The control unit can be provided in the form of physical buttons, touch sensors, etc. For example, a proximity sensor for determining whether the user is wearing the device can be accommodated in the main unit HS. For example, an external display panel can be further provided in the main unit HS.

[0092] The main unit HS can be divided into a main body portion HS-1 and a cover portion HS-2. Figure 2B An example of the form in which the main body portion HS-1 and the cover portion HS-2 are separated from each other is illustrated, but the embodiments are not limited thereto. For example, the main body portion HS-1 and the cover portion HS-2 can be provided as an integrated unit and may not be separated from each other.

[0093] The display panel DP can be provided between the main body portion HS-1 and the cover portion HS-2. Each of the display panels DP can provide an image through the display area DA. Each of the display panels DP can include a non-display area NDA surrounding the display area DA. In one embodiment, the non-display area NDA can be provided only on one side of the display area DA, or can be omitted.

[0094] In Figure 2B an example of displaying a left-eye image and a right-eye image through separate display panels DP is illustrated, but the embodiments are not limited thereto. In another example, the left-eye image and the right-eye image can be displayed through a single display panel. The display panel DP can be driven by a separate driving unit. However, without limitation, the display panel DP can be driven by a single driving unit. The display panel DP can generate an image corresponding to the input image data.

[0095] The strap STR can be coupled to the main unit HS such that the main unit HS can be easily worn by the user. The strap STR can include a main strap portion STR1 and an upper strap portion STR2.

[0096] The main strap portion STR1 can be worn along the user's head circumference. The main strap portion STR1 can fix the main unit HS to the user such that the main unit HS can be in close contact with the user's head. The upper strap portion STR2 can connect the main unit HS and the main strap portion STR1 to each other along the upper portion of the user's head. The upper strap portion STR2 can prevent the main unit HS from falling off. For example, the upper strap portion STR2 can distribute the load of the main unit HS to further improve the wearing comfort of the user.

[0097] As long as the main unit HS is fixed to the user, the strap STR can be modified to be other than Figure 2AVarious forms other than the form exemplified. For example, in another embodiment, the upper strap portion STR2 may be omitted. In another embodiment, the strap STR may be modified into various forms, such as a helmet coupled to the main body unit HS or temple pieces coupled to the main body unit HS.

[0098] The cushioning portion PP may be provided between the main body unit HS and the user's head. The cushioning portion PP may be made of a material having a freely deformable shape. For example, the cushioning portion PP may be formed of a polymer resin (e.g., polyurethane, polycarbonate, polypropylene, and polyethylene) or a sponge made by foaming and molding a rubber solution, urethane-based material, or acrylic-based material. However, the embodiments are not limited thereto.

[0099] The cushioning portion PP may serve to bring the main body unit HS into close contact with the user, thereby improving the user's wearing comfort. The cushioning portion PP may be detachable from the main body unit HS. In another embodiment, the cushioning portion PP may be omitted.

[0100] The optical system OL may be provided inside the main body portion HS-1 of the main body unit HS. The optical system OL may magnify the image provided from the display panel DP. Each of the display panels DP may display an image in a third direction DR3 through a display area DA parallel to a plane defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The optical system OL may be spaced apart from the display panel DP in the third direction DR3. The optical system OL may be provided between the display panel DP and the user's eyes. The optical system OL may include a right-eye optical system OL_R and a left-eye optical system OL_L. The left-eye optical system OL_L may magnify the image and provide the image to the user's left pupil, and the right-eye optical system OL_R may magnify the image and provide the image to the user's right pupil.

[0101] The left-eye optical system OL_L and the right-eye optical system OL_R may be spaced apart from each other in the first direction DR1. The distance between the right-eye optical system OL_R and the left-eye optical system OL_L may be adjusted in response to the distance between the user's two eyes. For example, the distance between the optical system OL and the display panel DP may be adjusted according to the user's eyesight.

[0102] The optical system OL may be a convex aspherical lens. For example, the optical system OL may be a pancake lens, but the embodiments are not limited thereto. In this embodiment, each of the left-eye optical system OL_L and the right-eye optical system OL_R is described as being composed of only one lens, but the embodiments are not limited thereto. For example, each of the left-eye optical system OL_L and the right-eye optical system OL_R may include a plurality of lenses.

[0103] Included in accordance with the referenceFigures 1A to 2B The display panels DP in the described electronic device DD and the electronic device HMD of the embodiment can be an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micro LED display panel, or a nano LED display panel. In this embodiment, the display panel DP is described as an organic light-emitting display panel, but the embodiment is not limited thereto.

[0104] Figure 3 FIG. 5 is a schematic cross-sectional view of a display panel DP according to an embodiment. The display panel DP according to an embodiment may include a substrate BL, a circuit element layer D-CL provided on the substrate BL, a display element layer D-OL, and a packaging layer TFE. The display panel DP may include a display area DA and a non-display area NDA. The display element layer D-OL may be provided to correspond to (or may overlap with) the display area DA. However, the embodiment is not limited thereto, and at least a part of the display element layer D-OL may be provided in the non-display area NDA.

[0105] The substrate BL may be a support substrate on which the circuit element layer D-CL and the display element layer D-OL are provided. The substrate BL may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc. The substrate BL may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate. For example, the substrate BL may be a single-crystalline silicon substrate, but the embodiment is not limited thereto. In the description, the display area DA and the non-display area NDA may be considered to be defined on the substrate BL, and the components provided on the substrate BL may also be considered to be provided to overlap with the display area DA or the non-display area NDA.

[0106] The circuit element layer D-CL may include at least one insulating layer and circuit elements. The circuit elements may include signal lines, pixel driving circuits, etc. The circuit element layer D-CL may be formed by processes such as coating and deposition to form insulating layers, semiconductor layers, and conductive layers, and then patterning the insulating layers, semiconductor layers, and conductive layers by a photolithography process.

[0107] The display element layer D-OL may include light-emitting elements. The light-emitting elements may include a light-emitting layer that emits light, etc.

[0108] The packaging layer TFE may include thin films. Some thin films may be provided to improve optical efficiency, and other thin films may be provided to protect the light-emitting elements.

[0109] The encapsulation layer TFE may be a thin film encapsulation layer. The encapsulation layer TFE may be a single layer or multiple layers stacked on top of each other. The encapsulation layer TFE may include at least one insulating layer. The encapsulation layer TFE according to an embodiment may include at least one inorganic film (hereinafter referred to as an inorganic encapsulation film). For example, the encapsulation layer TFE according to an embodiment may include at least one organic film (hereinafter referred to as an organic encapsulation film) and at least one inorganic encapsulation film.

[0110] The inorganic encapsulation film may protect the light emitting element ED (see Figure 6 ) from the effects of moisture / oxygen, and the organic encapsulation film may protect the light emitting element ED (see Figure 6 ) from foreign substances such as dust particles. The inorganic encapsulation film may include silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide, but the embodiment is not limited thereto. The organic encapsulation film may include acrylic compounds, epoxy compounds, etc. The organic encapsulation film may include a photo-polymerizable organic material, but the embodiment is not limited thereto.

[0111] Figure 4 is a schematic plan view of a display panel DP according to an embodiment. The display panel DP may include a substrate BL divided into a display area DA and a non-display area NDA, as described in reference .

[0112] The display panel DP may include pixels PX disposed in the display area DA and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a driving circuit GDC and a pad portion PLD disposed in the non-display area NDA.

[0113] The pixels PX may be arranged in a first direction DR1 and a second direction DR2. The pixels PX may include pixel rows extending in the first direction DR and arranged in the second direction DR2, and pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0114] The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL may be connected to a corresponding pixel in the pixels PX, and each of the data lines DL may be connected to a corresponding pixel in the pixels PX. The power line PL may be electrically connected to the pixels PX. The control signal line CSL may be connected to the driving circuit GDC to provide a control signal to the driving circuit GDC.

[0115] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the generated gate signal to the gate lines GL. The gate driving circuit may further output another control signal to the pixel driving circuit.

[0116] The pad portion PLD may be a portion to which a flexible circuit board is connected. The pad portion PLD may include pixel pads D-PD, and the pixel pads D-PD may be pads for connecting a flexible circuit board to a display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line in the signal lines SGL. The pixel pads D-PD may be connected to corresponding pixels PX through the signal lines SGL. For example, any one of the pixel pads D-PD may be connected to a driving circuit GDC.

[0117] For example, the pad portion PLD may further include input pads. The input pads may be pads for connecting a flexible circuit board to an input sensor ISL (see Figure 3 ). However, the present invention is not limited thereto, and the input pads may be provided in the input sensor ISL (see Figure 1B ) and connected to the pixel pads D-PD and a separate circuit board. In another example, the input sensor ISL (see Figure 1B ) may be omitted and the input pads may not be included.

[0118] Figure 1B is an enlarged schematic plan view of a part of a display panel DP according to an embodiment. Figure 5 Illustrates a part of a display area DA (see ) observed from a display surface IS (see Figure 5 ) of a display module DM (see Figure 1B ). Figure 1B Illustrates the arrangement of light-emitting regions PXA-R, PXA-G, and PXA-B in a display panel DP (see Figure 1B ) according to an embodiment.

[0119] A display panel DP according to an embodiment may include light-emitting regions PXA-R, PXA-G, and PXA-B spaced apart from each other in a plan view and a peripheral region NPXA provided between the light-emitting regions PXA-R, PXA-G, and PXA-B.

[0120] A display panel DP according to an embodiment may include three types of light-emitting regions PXA-R, PXA-G, and PXA-B that are distinguishable from each other. In one embodiment, Figure 5 the three types of light-emitting regions PXA-R, PXA-G, and PXA-B illustrated in

[0121] The display area DA may include a first light-emitting area PXA-R, a second light-emitting area PXA-G, and a third light-emitting area PXA-B that emit light in different wavelength ranges and are spaced apart from each other on a plane (or in a plan view). For example, the display area DA may include a peripheral area NPXA. The peripheral area NPXA may be referred to as a non-light-emitting area. Refer to Figure 3 , the first light-emitting area PXA-R may correspond to a red pixel R, the second light-emitting area PXA-G may correspond to a green pixel G, and the third light-emitting area PXA-B may correspond to a blue pixel B.

[0122] The peripheral area NPXA may be disposed around the first to third light-emitting areas PXA-R, PXA-G, and PXA-B. The peripheral area NPXA may set (or define) the boundaries of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B. The peripheral area NPXA may surround the first to third light-emitting areas PXA-R, PXA-G, and PXA-B. In the peripheral area NPXA, a structure (such as a pixel definition layer PDL (see )) for preventing color mixing in the first to third light-emitting areas (e.g., the first to third pixel areas) PXA-R, PXA-G, and PXA-B may be provided so as to correspond to the peripheral area NPXA.

[0123] Since the display panel DP according to an embodiment includes a metal pattern layer JHL (see Figure 5 ) that overlaps with the pixel definition layer PDL and a low thermal conductivity layer PTL (see Figure 5 ) disposed below the metal pattern layer JHL, and the functional layers FL (see Figure 6 ) may not be connected to each other at a portion corresponding to the peripheral area NPXA, leakage current can be prevented from being transmitted to adjacent light-emitting areas PXA-R, PXA-G, and PXA-B. For example, the functional layers FL (see Figure 7 ) disposed in the light-emitting areas PXA-R, PXA-G, and PXA-B may have excellent film characteristics to prevent damage. Therefore, the display panel DP according to an embodiment may have excellent display quality.

[0124] The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may respectively correspond to areas that emit light provided by light-emitting elements ED1, ED2, and ED3 (see Figure 7 ). The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be classified (or distinguished) according to the color of light emitted toward the outside of the display module DM (see Figure 6 ).

[0125] The first light-emitting region to the third light-emitting regions PXA-R, PXA-G, and PXA-B may respectively provide first color light to third color light having different colors. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, the examples of the first color light to the third color light are not limited thereto.

[0126] Each of the first light-emitting region to the third light-emitting regions PXA-R, PXA-G, and PXA-B may be defined as a region where the upper surface of the first electrode AE (see Figure 6 ) of the light-emitting element is exposed through a light-emitting opening OH (see Figure 7 ) to be described later.

[0127] Each of the first light-emitting region to the third light-emitting regions PXA-R, PXA-G, and PXA-B may be provided in plural and may be repeatedly arranged in a specific layout in the display region DA. For example, the first light-emitting region PXA-R and the third light-emitting region PXA-B may be alternately arranged along a first direction DR1 to form a "first group". The second light-emitting region PXA-G may be arranged along the first direction DR1 to form a "second group". Each of the "first group" and the "second group" may be provided in plural, and the "first group" and the "second group" may be alternately arranged with each other along a second direction DR2.

[0128] One second light-emitting region PXA-G may be spaced apart from one first light-emitting region PXA-R or one third light-emitting region PXA-B in a fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0129] Figure 1B Illustrate the layout forms of the first light-emitting region to the third light-emitting regions PXA-R, PXA-G, and PXA-B, but the embodiments are not limited thereto. For example, the first light-emitting region to the third light-emitting regions PXA-R, PXA-G, and PXA-B may be arranged in various forms. In one embodiment, the first light-emitting region to the third light-emitting regions PXA-R, PXA-G, and PXA-B may have a layout form. In another example, the first light-emitting region to the third light-emitting regions PXA-R, PXA-G, and PXA-B may have a stripe layout form or (Diamond ) layout form.

[0130] The first light-emitting region to the third light-emitting regions PXA-R, PXA-G, and PXA-B may have various shapes on a plane (or in a plan view). For example, the first light-emitting region to the third light-emitting regions PXA-R, PXA-G, and PXA-B may have a polygonal, circular, or elliptical shape.Figure 6 Illustrate a first light-emitting region PXA-R and a third light-emitting region PXA-B having a quadrilateral shape (or a rhombus shape) and a second light-emitting region PXA-G having an octagonal shape on a plane (or in a plan view).

[0131] The first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have the same shape on a plane (or in a plan view), or at least some of them may have a different shape from others. Figure 6 Illustrate a first light-emitting region PXA-R and a third light-emitting region PXA-B having the same shape and a second light-emitting region PXA-G having a shape different from the shapes of the first light-emitting region PXA-R and the third light-emitting region PXA-B on a plane (or in a plan view).

[0132] At least some of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have different areas (or sizes) from each other on a plane (or in a plan view). In one embodiment, the area (or size) of the first light-emitting region PXA-R that emits red light may be larger than the area (or size) of the second light-emitting region PXA-G that emits green light and smaller than the area (or size) of the third light-emitting region PXA-B that emits blue light. However, the size relationship between the areas (or sizes) of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B that emit different colors of light is not limited thereto and may vary according to the design of the display panel DP of an embodiment. For example, without being limited thereto, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have the same area (or the same size) on a plane (or in a plan view).

[0133] For example, the shape, area (or size), and arrangement of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B of the display panel DP according to an embodiment may be designed in various ways according to the color of the emitted light or the size and configuration of the display panel DP included in the electronic device, and the embodiment is not limited to Figure 5 the embodiment illustrated in. For example, in one embodiment, in addition to the first to third light-emitting regions PXA-R, PXA-G, and PXA-B, the display panel DP may further include a light-emitting region that emits white light.

[0134] Figure 5 is a schematic cross-sectional view of a partial region of the display panel DP according to an embodiment. Figure 5 is a schematic cross-sectional view of a partial region of the display panel DP according to an embodiment, and illustrates portions corresponding to the light-emitting regions PXA-R, PXA-G, and PXA-B. Figure 5Can be corresponding to Figure 6 A schematic cross-sectional view of a portion of line II', and Figure 7 Can be corresponding to Figure 6 Schematic cross-sectional view of a portion along line II-II'.

[0135] Figure 5 The example corresponds to the first light emitting region PXA-R (see Figure 7 ) and a cross section of a portion of the periphery of the first light emitting region PXA-R. However, Figure 5 The cross section illustrated in FIG. 5 is not limited to the first light emitting region PXA-R and the peripheral region thereof, and may be a portion corresponding to any one of the light emitting regions included in the display panel DP.

[0136] refer to Figure 6 , the display panel DP may include a base substrate BL, a circuit element layer D-CL, a display element layer D-OL, and an encapsulation layer TFE.

[0137] The circuit element layer D-CL may include a buffer layer BFL, a transistor TR, a signal transmission region SCL, first to fifth insulating layers 10 , 20 , 30 , 40 , and 50 , an upper electrode pattern EE, and connection electrodes CNE1 and CNE2 .

[0138] A buffer layer BFL may be disposed on the base substrate BL. The buffer layer BFL may improve the bonding strength between the base substrate BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0139] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, not limited thereto, the semiconductor pattern may include amorphous silicon or metal oxide. Figure 5 Only a portion of the semiconductor pattern is illustrated, and the semiconductor pattern may be further provided in the light emitting regions PXA-R, PXA-G, and PXA-B (see FIG. Figure 6 ). The semiconductor pattern may be arranged in a specific pattern throughout the light-emitting regions PXA-R, PXA-G, and PXA-B. The semiconductor pattern may have different electrical characteristics depending on whether it is doped. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0140] The first region may have higher conductivity than the second region and may substantially serve as an electrode or a signal line. The second region may substantially correspond to the active region (or channel region) of the transistor. For example, a part of the semiconductor pattern may be the active region of the transistor, another part of the semiconductor pattern may be the source region or drain region of the transistor, and still another part of the semiconductor pattern may be a conductive region.

[0141] The source region S-D, active region A-D, and drain region D-D of the transistor TR may be formed of a semiconductor pattern. Figure 6 Illustrate a part of the signal transmission region SCL formed of a semiconductor pattern. For example, the signal transmission region SCL may be connected to the drain region D-D of the transistor TR in a plane (or in a plan view).

[0142] The first insulating layer to the fifth insulating layers 10, 20, 30, 40, and 50 may be disposed above the buffer layer BFL. The first insulating layer to the fifth insulating layers 10, 20, 30, 40, and 50 may be an inorganic layer or an organic layer.

[0143] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source region S-D, active region A-D, and drain region D-D of the transistor TR disposed on the buffer layer BFL and the signal transmission region SCL. The gate G-D of the transistor TR may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G-D. The upper electrode pattern EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the upper electrode pattern EE.

[0144] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 passing through the first insulating layer to the third insulating layers 10, 20, and 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0145] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0146] The display element layer D-OL may be disposed on the circuit element layer D-CL. The display element layer D-OL may include a light-emitting element ED, a pixel defining layer PDL, a metal pattern layer JHL, and a low thermal conductivity layer PTL.

[0147] The light-emitting element ED may include a first electrode AE, a second electrode CE facing the first electrode AE, and a functional layer FL disposed between the first electrode AE and the second electrode CE.

[0148] The first electrode AE may be disposed on the circuit element layer D-CL. The first electrode AE may overlap with each of the plurality of light-emitting regions PXA-R, PXA-G, and PXA-B. In one embodiment, the first electrode AE may be disposed on the fifth insulating layer 50 of the circuit element layer D-CL. The first electrode AE may be connected to the second connection electrode CNE2 through a connection contact hole CNT-3 defined in (or passing through) the fifth insulating layer 50. Accordingly, the first electrode AE may be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and thus electrically connected to the corresponding circuit element. The first electrode AE may include a single-layer structure or a multi-layer structure.

[0149] The first electrode AE may be an anode or a cathode. For example, the first electrode AE may be a pixel electrode. The second electrode CE may be a cathode or an anode. The second electrode CE may be a common electrode. For example, when the first electrode AE is an anode, the second electrode CE may be a cathode, and when the first electrode AE is a cathode, the second electrode CE may be an anode.

[0150] The functional layer FL may include a light-emitting layer and an organic layer provided on at least one of the upper and lower portions of the light-emitting layer. The functional layer FL may include at least one light-emitting structure. The functional layer FL may include at least one organic layer provided in common in the light-emitting regions PXA-R, PXA-G, and PXA-B (see Figure 6 )). For example, the functional layer FL may include a common layer provided in common to the light-emitting regions PXA-R, PXA-G, and PXA-B (see ) and a light-emitting layer patterned to correspond to each of the light-emitting regions PXA-R, PXA-G, and PXA-B. The common layer may be at least one organic layer that may overlap with the light-emitting opening OH and a portion of the pixel defining layer PDL adjacent to the light-emitting opening OH, and is spaced apart from the metal pattern layer JHL. For example, the common layer may perform a hole transport function or an electron transport function. The configuration of the functional layer FL will be described in more detail later.

[0151] For example, the light-emitting element ED according to one embodiment may further include a capping layer disposed on the second electrode CE. The capping layer may include multiple layers or a single layer.

[0152] The display element layer D-OL may include a pixel defining layer PDL disposed on the circuit element layer D-CL. The light-emitting opening OH may be defined in the pixel defining layer PDL (or may pass through the pixel defining layer PDL). The light-emitting opening OH of the pixel defining layer PDL may expose at least a portion of the first electrode AE. In one embodiment, the pixel defining layer PDL may cover the edge portion of the first electrode AE.

[0153] The pixel defining layer PDL may have a single-layer structure or a multi-layer structure. The pixel defining layer PDL may be formed of a polymer resin. For example, the pixel defining layer PDL may be formed by including an acrylate resin or a polyimide resin. For example, in addition to the polymer resin, the pixel defining layer PDL may be formed by further including an inorganic material. For example, the pixel defining layer PDL may be formed by including a light-absorbing material, or may be formed by including a black pigment or a black dye. The pixel defining layer PDL formed by including a black pigment or a black dye may achieve a black pixel defining layer. In the case of forming the pixel defining layer PDL, carbon black or the like may be used as the black pigment or the black dye, but the embodiments are not limited thereto.

[0154] For example, the pixel defining layer PDL may be formed of an inorganic material. For example, the pixel defining layer PDL may be formed of an inorganic material such as silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ).

[0155] The encapsulation layer TFE may be disposed on the second electrode CE of the light-emitting element ED. In another example, in the case where the light-emitting element ED includes a capping layer, the encapsulation layer TFE may be disposed on the capping layer. The encapsulation layer TFE may cover the light-emitting element ED.

[0156] Figure 5 is a schematic cross-sectional view of a part of a display panel DP according to an embodiment. The display panel DP may include a substrate BL, a circuit element layer D-CL, a display element layer D-OL, and an encapsulation layer TFE stacked in a third direction DR3. Regarding the substrate BL, the circuit element layer D-CL, the display element layer D-OL, and the encapsulation layer TFE, the content overlapping with that described in Figure 6 will not be described again, and for the sake of convenience of description, the differences will be described.

[0157] Refer to Figure 5, the display panel DP may include a first light-emitting region to a third light-emitting region PXA-R, PXA-G, and PXA-B that are distinguishable from each other, and a peripheral region NPXA disposed between the first light-emitting region to the third light-emitting region PXA-R, PXA-G, and PXA-B.

[0158] The light-emitting regions PXA-R, PXA-G, and PXA-B may be defined by being partitioned by a pixel defining layer PDL. In one embodiment, the first light-emitting region to the third light-emitting region PXA-R, PXA-G, and PXA-B of the display panel DP may be defined as partial regions corresponding to the portions of the first electrode AE exposed by the light-emitting openings OH, respectively.

[0159] The display element layer D-OL may include a pixel defining layer PDL and light-emitting elements ED1, ED2, and ED3 partitioned by the pixel defining layer PDL. The display element layer D-OL may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3. The first light-emitting element ED1 may emit red light, the second light-emitting element ED2 may emit green light, and the third light-emitting element ED3 may emit blue light.

[0160] The first light-emitting element ED1 may include a first pixel electrode AE1, a first functional layer FL1, and a second electrode CE. The second light-emitting element ED2 may include a second pixel electrode AE2, a second functional layer FL2, and a second electrode CE. The third light-emitting element ED3 may include a third pixel electrode AE3, a third functional layer FL3, and a second electrode CE. Each of the first pixel electrode to the third pixel electrode AE1, AE2, and AE3 may be referred to as a first electrode.

[0161] Figure 5 and Figure 7 Each of them is a schematic cross-sectional view illustrating a light-emitting element according to an embodiment. Figure 6 Each of the first light-emitting element to the third light-emitting element ED1, ED2, and ED3 in Figure 7 or Figure 8A may have the composition of the light-emitting element embodiments illustrated in

[0162] Referring to Figure 8B , according to an embodiment, the light-emitting element ED may include a first electrode AE, a functional layer FL, and a second electrode CE, and the functional layer FL may include a hole transport region HTR, a light-emitting layer EML, and an electron transport region ETR. According to an embodiment, the light-emitting element ED may include a single light-emitting structure, which is a stacked structure of a hole transport region HTR, a light-emitting layer EML, and an electron transport region ETR. For example, Figure 7Each of the first functional layer to the third functional layer FL1, FL2, and FL3 of the first light-emitting element to the third light-emitting element ED1, ED2, and ED3 illustrated in [Example] may include a single light-emitting structure, which is a stacked structure of a hole transport region HTR, a light-emitting layer EML, and an electron transport region ETR.

[0163] In the light-emitting element ED, the first electrode AE may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The first electrode AE may be formed of a metal material, a metal alloy, or a conductive compound. The first electrode AE may contain at least one selected from the group consisting of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn, a compound selected from two or more of them, a mixture selected from two or more of them, or an oxide thereof.

[0164] When the first electrode AE is a transmissive electrode, the first electrode AE may be composed of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). When the first electrode AE is a semi-transmissive electrode or a reflective electrode, the first electrode AE may contain Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca (a stacked structure of LiF and Ca), LiF / Al (a stacked structure of LiF and Al), Mo, Ti, W, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). In another example, the first electrode AE may have a multilayer structure including: a reflective film or a semi-transmissive film formed of the above materials; and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the first electrode AE may have a three-layer structure of ITO / Ag / ITO, but the embodiments are not limited thereto. For example, the embodiments are not limited thereto, and the first electrode AE may contain the metal materials described above, a combination of two or more metal materials selected from the metal materials described above, oxides of the metal materials described above, etc.

[0165] The second electrode CE may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. When the second electrode CE is a transmissive electrode, the second electrode CE may be made of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO).

[0166] In the case where the second electrode CE is a transmissive electrode or a reflective electrode, the second electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, Yb, W, or a compound or mixture containing them (e.g., AgMg, AgYb, or MgYb). In another example, the second electrode CE may have a multilayer structure including a reflective film or a semi-transmissive film formed of the above materials, and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the second electrode CE may include the above-described metal materials, a combination of two or more metal materials selected from the above-described metal materials, oxides of the above-described metal materials, etc.

[0167] The light-emitting layer EML may include a light-emitting material. The light-emitting layer EML may have a single-layer structure made of a single material, a single-layer structure made of different materials, or a multilayer structure composed of multiple layers made of different materials. The light-emitting layer may include a fluorescent or phosphorescent material. In a light-emitting element ED according to an embodiment, the light-emitting layer EML may include an organic light-emitting material, an organometallic complex, a quantum dot, etc. as the light-emitting material.

[0168] For example, the light-emitting layer EML included in the first to third functional layers FL1, FL2, and FL3 (see Figure 8A ) may emit light in different wavelength ranges. Each of the first to third functional layers FL1, FL2, and FL3 (see Figure 8B ) may include a light-emitting layer EML containing different light-emitting materials.

[0169] Figure 8A The exemplary light-emitting element ED includes a single light-emitting layer EML, but the light-emitting element ED may further include an auxiliary light-emitting layer for improving the light-emitting efficiency in addition to a main light-emitting layer containing a light-emitting material that emits light of a selected color. For example, in one embodiment, the light-emitting layer EML may have a stacked structure of sub-light-emitting layers having different light-emitting material compositions.

[0170] The light-emitting element ED may include a hole transport region HTR disposed between the first electrode AE and the light-emitting layer EML. The hole transport region HTR may include at least one of a hole injection layer HIL, a hole transport layer HTL, an auxiliary light-emitting layer, and an electron blocking layer. For example, the hole transport region HTR may include a hole injection layer HIL and a hole transport layer HTL stacked in sequence on the first electrode AE.

[0171] For example, the light-emitting layer EML included in the first to third functional layers FL1, FL2, and FL3 (see Figure 7) The hole transport region HTR in () can be formed simultaneously in the same process step. It includes in the first functional layer to the third functional layer FL1, FL2, and FL3 (see Figure 7 ) The hole transport region HTR in () can be formed of the same material. It includes in the first functional layer to the third functional layer FL1, FL2, and FL3 (see Figure 7 ) The hole transport region HTR in () can be provided by using the same material in the same process step and then disconnected by the metal pattern layer JHL, so that the hole transport region HTR can be separately provided in each of the first functional layer to the third functional layer FL1, FL2, and FL3 (see Figure 8A ) Each of them.

[0172] The light-emitting element ED can include an electron transport region ETR provided between the light-emitting layer EML and the second electrode CE. The electron transport region ETR can include at least one of a hole blocking layer, an electron transport layer ETL, and an electron injection layer EIL. For example, the electron transport region ETR can include an electron transport layer ETL and an electron injection layer EIL provided on the light-emitting layer EML, but the embodiments are not limited thereto. The electron transport region ETR can have a single-layer structure made of a single material, a single-layer structure made of different materials, or a multi-layer structure composed of multiple layers made of different materials.

[0173] For example, the electron transport region ETR included in the first functional layer to the third functional layer FL1, FL2, and FL3 (see Figure 7 ) can be formed simultaneously in the same process step. The electron transport region ETR included in the first functional layer to the third functional layer FL1, FL2, and FL3 (see Figure 7 ) can be formed of the same material. The electron transport region ETR included in the first functional layer to the third functional layer FL1, FL2, and FL3 (see Figure 7 ) can be provided by using the same material in the same process step and then disconnected by the metal pattern layer JHL, so that the electron transport region ETR can be separately provided in each of the first functional layer to the third functional layer FL1, FL2, and FL3 (see Figure 7 ) Each of them.

[0174] Refer to Figure 7 , The light-emitting element ED-a according to an embodiment can include a first electrode AE, a functional layer FL-a, and a second electrode CE, and the functional layer FL-a can include a light-emitting structure EU-B and EU-T. The light-emitting structures EU-B and EU-T can respectively include a light-emitting layer EML-B and EML-T. Accordingly, the functional layer FL-a can include the light-emitting layers EML-B and EML-T. For example, the light-emitting element ED-a according to an embodiment can be a light-emitting element having a tandem structure including the light-emitting layers EML-B and EML-T separated from each other.

[0175] The light-emitting element ED-a according to an embodiment may further include a charge generation layer CGL. When a voltage is applied to the light-emitting element ED-a, the charge generation layer CGL may generate charges (electrons and holes) by forming a complex through a redox reaction. The charge generation layer CGL may supply the generated charges to each of the adjacent light-emitting structures EU-B and EU-T. The charge generation layer CGL may improve the efficiency of the current generated in each of the adjacent light-emitting structures EU-B and EU-T, and may serve to control the charge balance between the adjacent light-emitting structures EU-B and EU-T.

[0176] The charge generation layer CGL may have a layer structure in which an n-type charge generation layer n-CGL and a p-type charge generation layer p-CGL are combined with each other.

[0177] The n-type charge generation layer n-CGL may supply electrons to the adjacent light-emitting structures EU-B and EU-T. The n-type charge generation layer n-CGL may be a layer in which a base material is doped with an n-dopant. The p-type charge generation layer p-CGL may supply holes to the adjacent light-emitting structures EU-B and EU-T. The p-type charge generation layer p-CGL may be a layer in which a base material is doped with a p-dopant.

[0178] The light-emitting element ED-a may include a first light-emitting structure EU-B and a second light-emitting structure EU-T provided on the first light-emitting structure EU-B. The charge generation layer CGL may be provided between the first light-emitting structure EU-B and the second light-emitting structure EU-T.

[0179] The first light-emitting structure EU-B may include a first hole transport region HTR-B, a first light-emitting layer EML-B, and a first electron transport region ETR-B, and the second light-emitting structure EU-T may include a second hole transport region HTR-T, a second light-emitting layer EML-T, and a second electron transport region ETR-T.

[0180] Reference Figure 7 The description of the provided hole transport region HTR may equally apply to the first hole transport region HTR-B and the second hole transport region HTR-T. For example, in the light-emitting element ED-a according to an embodiment, the first hole transport region HTR-B and the second hole transport region HTR-T may have the same structure and be formed of the same material. However, the embodiment is not limited thereto, and the first hole transport region HTR-B and the second hole transport region HTR-T may have different stacking structures, or the first hole transport region HTR-B and the second hole transport region HTR-T may include different hole transport materials.

[0181] Reference Figure 7The description of the provided emission layer EML can be equally applied to the first emission layer EML-B and the second emission layer EML-T. For example, in a light-emitting element ED-a according to an embodiment, the first emission layer EML-B and the second emission layer EML-T may have the same structure and be formed of the same material. However, the embodiment is not limited thereto, and the first emission layer EML-B and the second emission layer EML-T may have different stacked structures, or the first emission layer EML-B and the second emission layer EML-T may include different light-emitting materials. For example, each of the first emission layer EML-B and the second emission layer EML-T may include stacked sub-emission layers or stacked auxiliary emission layers.

[0182] Reference Figure 7 The description of the provided electron transport region ETR can be equally applied to the first electron transport region ETR-B and the second electron transport region ETR-T. For example, in a light-emitting element ED-a according to an embodiment, the first electron transport region ETR-B and the second electron transport region ETR-T may have the same structure and be formed of the same material. However, the embodiment is not limited thereto, and the first electron transport region ETR-B and the second electron transport region ETR-T may have different stacked structures, or the first electron transport region ETR-B and the second electron transport region ETR-T may include different electron transport materials.

[0183] For example, the light-emitting structures EU-B and EU-T included in the first to third functional layers FL1, FL2, and FL3 (see Figure 8B ) may emit light in different wavelength ranges. The first to third functional layers FL1, FL2, and FL3 (see Figure 8A ) may include emission layers EML-B and EML-T, each of the emission layers EML-B and EML-T containing different light-emitting materials.

[0184] The first hole transport region HTR-B included in the first to third functional layers FL1, FL2, and FL3 (see Figure 8A ) may be formed simultaneously in the same process step. The first hole transport region HTR-B included in the first to third functional layers FL1, FL2, and FL3 (see Figure 8A ) may be provided in the same process step using the same material and then disconnected by a metal pattern layer JHL so that the first hole transport region HTR-B can be separately provided in each of the first to third functional layers FL1, FL2, and FL3 (see Figure 7 ). For example, the first to third functional layers FL1, FL2, and FL3 (see Figure 7) The second hole transport region HTR-T in can be provided in the same process step using the same material and then disconnected by the metal pattern layer JHL, such that the second hole transport region HTR-T can be separately provided in each of the first to third functional layers FL1, FL2, and FL3 (see Figure 7 ) thereof.

[0185] For example, the first electron transport region ETR-B included in the first to third functional layers FL1, FL2, and FL3 (see Figure 7 ) can be formed simultaneously in the same process step. The first electron transport region ETR-B can be provided in the same process step using the same material and then disconnected by the metal pattern layer JHL, such that the first electron transport region ETR-B can be separately provided in each of the first to third functional layers FL1, FL2, and FL3 (see Figure 7 ) thereof. For example, the second electron transport region ETR-T included in the first to third functional layers FL1, FL2, and FL3 (see Figure 7 ) can be formed simultaneously in the same process step. The second electron transport region ETR-T can be provided in the same process step using the same material and then disconnected by the metal pattern layer JHL, such that the second electron transport region ETR-T can be separately provided in each of the first to third functional layers FL1, FL2, and FL3 (see Figure 7 ) thereof.

[0186] The charge generation layer CGL included in the first to third functional layers FL1, FL2, and FL3 (see Figure 7 ) can be formed simultaneously in the same process step. The charge generation layer CGL included in the first to third functional layers FL1, FL2, and FL3 (see Figure 7 ) can be formed in the same process step using the same material and then disconnected by the metal pattern layer JHL, such that the charge generation layer CGL can be separately provided in each of the first to third functional layers FL1, FL2, and FL3 (see Figure 7 ) thereof.

[0187] Referring again to Figure 7, the functional layers FL1, FL2, and FL3 of the light-emitting elements ED1, ED2, and ED3 can extend into the light-emitting regions PXA-R, PXA-G, and PXA-B and the peripheral regions NPXA adjacent to the light-emitting regions PXA-R, PXA-G, and PXA-B. For example, the functional layers FL1, FL2, and FL3 of the light-emitting elements ED1, ED2, and ED3 can be disposed in the portions of the plurality of light-emitting regions PXA-R, PXA-G, and PXA-B and the peripheral region NPXA that are adjacent to the plurality of light-emitting regions PXA-R, PXA-G, and PXA-B.

[0188] A display panel DP according to an embodiment may include a metal pattern layer JHL. The metal pattern layer JHL may overlap with the pixel defining layer PDL. The metal pattern layer JHL may not overlap with the entire upper surface (e.g., the entire upper surface) of the pixel defining layer PDL, and may overlap only with a part of the upper surface of the pixel defining layer PDL.

[0189] The metal pattern layer JHL may be a Joule heating wire that generates heat when a current is supplied. When a current flows through the metal pattern layer JHL, heat of about 400 °C or higher may be generated. The metal pattern layer JHL may be formed of a metal material having high resistance characteristics. For example, the metal pattern layer JHL may contain molybdenum (Mo), titanium (Ti), or tungsten (W). For example, the metal pattern layer JHL may be formed of a metal material containing molybdenum (Mo). However, the embodiment is not limited thereto, and any metal material may be used for the metal pattern layer JHL without limitation as long as it is a metal material that generates heat of about 90 °C or higher and is capable of removing organic materials when a current is provided.

[0190] Figure 7 Illustratively, in the display panel DP according to an embodiment, the metal pattern layer JHL may be provided to correspond to the peripheral regions NPXA respectively and may be spaced apart from each other in a cross-section. However, the embodiment is not limited thereto, and at least a part of the metal pattern layer JHL provided to correspond to the peripheral regions NPXA may be connected to each other in order to easily supply current to the metal pattern layer JHL. For example, the metal pattern layer JHL may overlap with the peripheral region NPXA and be provided as an integral part connected to each other.

[0191] The metal pattern layer JHL may be provided in such a manner that the organic layers provided as a common layer in the adjacent light-emitting regions PXA-R, PXA-B, and PXA-G are disconnected from each other in some regions. In one embodiment, the common layer may be a hole transport region HTR, HTR-T, and HTR-B (see Figure 7 and Figure 7 ), an electron transport region ETR, ETR-T, and ETR-B (see Figure 7 andFigure 7 ) or a charge generation layer CGL (see Figure 8A ).

[0192] When the common layers are connected to each other between the light-emitting regions PXA-R, PXA-B, and PXA-G, leakage current may occur through the common layers. Therefore, color mixing may occur between the light-emitting regions PXA-R, PXA-B, and PXA-G. Therefore, by disconnecting the common layers, the display quality can be improved. For example, for the disconnection of the common layers, there is a method of using the step difference of the structure by separately providing a structure on the pixel definition layer PDL, but in one embodiment, by using a metal pattern layer JHL that generates heat by a Joule heating method without introducing (or forming) a separate structure, a structure in which the common layers are disconnected from each other can be easily formed.

[0193] For example, since the organic layer is patterned by using the metal pattern layer JHL without introducing (or forming) a separate structure, although the size of the light-emitting region (e.g., pixel region) is small, a disconnected organic layer can be provided, and thus, according to one embodiment, the display panel DP can have high-resolution characteristics. The display panel DP according to one embodiment can be used in a miniaturized electronic device or the like and can have ultra-high-resolution characteristics.

[0194] The display panel DP according to one embodiment may include a low thermal conductivity layer PTL disposed below the metal pattern layer JHL. The low thermal conductivity layer PTL may be disposed (e.g., directly disposed) below the metal pattern layer JHL. The low thermal conductivity layer PTL may overlap with the metal pattern layer JHL (e.g., the entire metal pattern layer JHL). The low thermal conductivity layer PTL may be disposed (e.g., directly disposed) between the pixel definition layer PDL and the metal pattern layer JHL.

[0195] The low thermal conductivity layer PTL can prevent the heat generated in the metal pattern layer JHL from being transferred to the light-emitting regions PXA-R, PXA-G, and PXA-B. The low thermal conductivity layer PTL can suppress the heat generated in the metal pattern layer JHL from being transferred to the functional layer FL provided in the light-emitting regions PXA-R, PXA-G, and PXA-B, and can prevent the functional layer FL from being damaged, thereby improving the light-emitting efficiency and quality of the light-emitting elements ED1, ED2, and ED3.

[0196] The low thermal conductivity layer PTL may have a thermal conductivity of about 1.0 W / mK or less. For example, the thermal conductivity of the low thermal conductivity layer PTL may be about 0.5 W / mK or less. For example, the thermal conductivity of the low thermal conductivity layer PTL may be about 0.28 W / mK.

[0197] The low thermal conductivity layer PTL may include a polymer-type amorphous carbon film. In the polymer-type amorphous carbon film, sp 3The proportion of carbon bonds can be in the range of about 50% to about 70%. For example, in the polymer-type amorphous carbon film forming the low thermal conductivity layer PTL, the sp 3 proportion of carbon bonds can be about 60%. For example, the low thermal conductivity layer PTL can have a refractive index of about 1.75 or less at a wavelength of about 550 nm and a density in the range of about 1.2 g / cm 3 to about 1.6 g / cm 3 For example, the low thermal conductivity layer PTL can be formed of a polymer-type amorphous carbon film having about 60% sp 3 carbon bonds, a refractive index of about 1.64 at a wavelength of about 550 nm, and a density of about 1.3 g / cm 3 .

[0198] In one embodiment, the low thermal conductivity layer PTL can be formed of a polymer-type amorphous carbon film having about 50% to about 70% sp 3 carbon bonds, a refractive index of about 1.75 or less at a wavelength of about 550 nm, and a density in the range of about 1.2 g / cm 3 to about 1.6 g / cm 3 , thereby having low thermal conductivity characteristics.

[0199] In one embodiment, a deposition facility can be used to form the low thermal conductivity layer PTL. The low thermal conductivity layer PTL can be formed by providing a hydrocarbon gas and using a chemical vapor deposition (CVD) facility. For example, the low thermal conductivity layer PTL can be formed by providing C2H4 gas as a source.

[0200] In a display panel DP according to an embodiment, the functional layers FL1, FL2, and FL3 of the light-emitting elements ED1, ED2, and ED3 may not overlap with the metal pattern layer JHL. The functional layers FL1, FL2, and FL3 may be disposed in the light-emitting openings OH corresponding to the light-emitting regions PXA-R, PXA-G, and PXA-B, respectively, and may be partially disposed to extend above the pixel defining layer PDL adjacent to the light-emitting opening OH.

[0201] The first to third functional layers FL1, FL2, and FL3 disposed in the light-emitting regions PXA-R, PXA-G, and PXA-B may be disconnected by the metal pattern layer JHL and may be separated from each other. The first to third functional layers FL1, FL2, and FL3 may be respectively disposed in the light-emitting regions PXA-R, PXA-G, and PXA-B, and may overlap at least a part of the peripheral region NPXA adjacent to the light-emitting regions PXA-R, PXA-G, and PXA-B, but may not overlap with the metal pattern layer JHL.

[0202] Figure 8B is Figure 8AAn enlarged schematic view of the region "AA". The region "AA" is selected from the second light-emitting region PXA-G and the peripheral region NPXA adjacent to the second light-emitting region PXA-G, but Figure 8B The structures illustrated in

[0203] Figure 8B can be similarly applied to other light-emitting regions and their adjacent regions. Take the case where the exemplary functional layer FL includes a hole transport region HTR, a light-emitting layer EML, and an electron transport region ETR as an example. The light-emitting layer EML of the functional layer FL can be provided by patterning in the light-emitting opening OH. For example, the light-emitting layer EML can be patterned and provided in the light-emitting opening OH, which is defined to correspond to Figure 9 each of the light-emitting regions PXA-R, PXA-G, and PXA-B illustrated in

[0204] Referring again to Figure 7 , the hole transport region HTR and the electron transport region ETR of the functional layer FL can be provided in the light-emitting opening OH and can be partially provided above the pixel defining layer PDL by extending from the portion of the functional layer FL provided in the light-emitting opening OH. In one embodiment, at least one of the hole transport region HTR and the electron transport region ETR can be provided in the light-emitting opening OH and extend above the upper surface US-PD of the pixel defining layer PDL adjacent to the light-emitting opening OH. The hole transport region HTR and the electron transport region ETR extending above the pixel defining layer PDL can be on the low thermal conductivity layer PTL. In one embodiment, at least one edge portion of the hole transport region HTR and the electron transport region ETR provided to extend above the upper surface US-PD of the pixel defining layer PDL can be spaced apart from the metal pattern layer JHL.

[0205] Figure 9 is an enlarged schematic cross-sectional view of a part of a display panel DP according to an embodiment. Figure 9 Illustrates a partial region including the light-emitting element ED and the pixel defining layer PDL adjacent to the light-emitting element ED. [[ID=2,1]]

[0206] In one embodiment, the low thermal conductivity layer PTL can cover the pixel defining layer PDL. The low thermal conductivity layer PTL can cover the upper surface US-PD and the side surface SS-PD of the pixel defining layer PDL.

[0207] In one embodiment, in a cross-section perpendicular to the substrate BL, a first width W of the metal pattern layer JHL in one direction (e.g., the horizontal direction) JH [[ID=,7]]can be smaller than a second width W of the pixel defining layer PDL in this direction PD . For example, the first width W of the metal pattern layer JHL JH can bePD is about 1 / 2 or less. For example, the second width W of the pixel defining layer PDL PD may be in the range of about 4 μm to about 5 μm, and the first width W of the metal pattern layer JHL JH may be in the range of about 1 μm to about 2 μm. For example, in one embodiment, the second width W of the pixel defining layer PDL PD may be about 2 μm, and the first width W of the metal pattern layer JHL JH may be about 1 μm or less. For example, the second width W of the pixel defining layer PDL to be compared therewith PD may be the width of the upper portion of the pixel defining layer PDL disposed adjacent to the metal pattern layer JHL.

[0208] In one embodiment, since the metal pattern layer JHL has a width smaller than the width of the pixel defining layer PDL, although heat is generated from the metal pattern layer JHL, the heat transferred to the organic layer provided in the light emitting regions PXA-R, PXA-B, and PXA-G separated by the pixel defining layer PDL can be reduced. For example, in a display panel DP according to an embodiment, since the low thermal conductivity layer PTL is disposed in contact with (e.g., directly in contact with) the metal pattern layer JHL so as to overlap with the metal pattern layer JHL (e.g., the entire metal pattern layer JHL), it is possible to minimize damage to the organic layer in the light emitting region while including the common layer disconnected by the metal pattern layer JHL, thereby having excellent display quality. For example, the organic layer may be a hole transport region, an electron transport region, a charge generation layer, etc.

[0209] Reference Figure 7 , the edge portion EDP of the functional layer FL extending to be disposed above the pixel defining layer PDL may be disposed (e.g., directly disposed) on the low thermal conductivity layer PTL. For example, the edge portion EDP of the functional layer FL may be spaced apart from the metal pattern layer JHL. For example, the shape and the arrangement position of the edge portion EDP of the functional layer FL are not limited to Figure 9 the shapes and the arrangement positions illustrated in etc. The shape and the arrangement position of the edge portion EDP of the functional layer FL can be adjusted by changing the Joule heating conditions in the metal pattern layer JHL.

[0210] The upper surface of the low thermal conductivity layer PTL exposed without being covered by the functional layer FL may be covered by the second electrode CE. The second electrode CE may cover the functional layer FL and the metal pattern layer JHL.

[0211] In one embodiment, each of the metal pattern layer JHL and the low thermal conductivity layer PTL may be formed to have a thickness in the range of several thousand angstroms For example, each of the metal pattern layer JHL and the low thermal conductivity layer PTL may have about The thickness. However, the embodiments are not limited thereto.

[0212] Figure 10 is a schematic plan view schematically illustrating a part of a display panel DP according to an embodiment. Figure 10 Illustrates a part of the display area.

[0213] Figure 10 Illustrates the layout relationship of the edge portions EDP of the light-emitting region PXA, the metal pattern layer JHL, the low thermal conductivity layer PTL, and the functional layer FL in a plane (or in a plan view). In Figure 10 the outer peripheral portion of the light-emitting region PXA may correspond to the peripheral region NPXA (see Figure 11 ). The metal pattern layer JHL and the low thermal conductivity layer PTL may be provided in the peripheral region NPXA (see Figure 11 ).

[0214] In one embodiment, the low thermal conductivity layer PTL may overlap with the region where the metal pattern layer JHL is provided (e.g., the entire region), and may be provided to a region further extending toward the light-emitting region PXA. When observed in a plane (or in a plan view) defined by the first direction DR1 and the second direction DR2, the area (or size) of the low thermal conductivity layer PTL may be larger than the area (or size) of the metal pattern layer JHL.

[0215] When observed in a plane (or in a plan view), the metal layer boundary line JBL defined by the edge portion EDP of the functional layer FL and the edge portion of the metal pattern layer JHL may be located in the peripheral region, and the edge portion EDP may be closer to the light-emitting region PXA than the metal layer boundary line JBL.

[0216] For example, in the outer portion of the light-emitting region PXA may be the portion where the pixel defining layer PDL is provided (see [[ID= ), and the area (or size) of the metal pattern layer JHL in the plan view may be smaller than the area (or size) of the pixel defining layer PDL. For example, the metal pattern layer JHL may be spaced apart from the light-emitting region PXA, and in the case where the area (or size) of the metal pattern layer JHL is smaller than the area (or size) of the pixel defining layer PDL (see ​ ), the metal pattern layer JHL may overlap with the pixel defining layer PDL (see ​ ) to prevent damage to the organic layer in the light-emitting region PXA. For example, since the edge portion EDP of the functional layer FL is set not to overlap with the metal pattern layer JHL, and the functional layer FL is separated from the peripheral region NPXA (see ​ ), quality degradation due to leakage current can be prevented, and the display panel DP can have excellent display quality.

[0217] ​ Each of them is a schematic cross-sectional view illustrating a part of a display panel DP according to an embodiment. In the description of the display panel DP according to an embodiment described with reference to ​ In the description of the display panel DP according to an embodiment, a description similar (or substantially the same) to the description provided with reference to ​ will not be provided again, and for convenience of description, the differences will be explained.

[0218] ​ The display panel DP-a according to an embodiment illustrated in may include a low thermal conductivity layer PTL-a, which is provided on the upper surface US-PD of the pixel defining layer PDL and is provided (e.g., directly provided) between the upper surface US-PD of the pixel defining layer PDL and the metal pattern layer JHL.

[0219] In an embodiment, in a cross-section perpendicular to the substrate BL, a first width W of the metal pattern layer JHL in one direction (e.g., the horizontal direction) JH may be smaller than a second width W of the upper surface US-PD of the pixel defining layer PDL adjacent to the metal pattern layer JHL in this direction PD and a third width W of the upper surface of the low thermal conductivity layer PTL-a adjacent to the metal pattern layer JHL in this direction PT .

[0220] In the display panel DP-a according to an embodiment, the side surface SS-PD of the pixel defining layer PDL may be covered by the functional layer FL. For example, a portion of the upper surface US-PD of the pixel defining layer PDL that is not covered by the low thermal conductivity layer PTL-a may also be covered by the functional layer FL.

[0221] In an embodiment, the third width W of the low thermal conductivity layer PTL-a PT may be smaller than the second width W of the upper surface US-PD of the pixel defining layer PDL PD . For example, the low thermal conductivity layer PTL-a having a width sufficiently larger than the width of the metal pattern layer JHL may overlap with the metal pattern layer JHL (e.g., the entire metal pattern layer JHL), and thus, heat generated from the metal pattern layer JHL can be prevented from being transferred to the functional layer FL.

[0222] ​The exemplary display panel DP-b according to an embodiment may include a low thermal conductivity layer PTL-b disposed (e.g., directly disposed) between the upper surface US-PD of the pixel defining layer PDL and the metal pattern layer JHL. The low thermal conductivity layer PTL-b may overlap with the upper surface US-PD of the pixel defining layer PDL (e.g., the entire upper surface US-PD). For example, in the display panel DP-b according to an embodiment, the side surface SS-PD of the pixel defining layer PDL may be covered by the functional layer FL.

[0223] In one embodiment, the low thermal conductivity layer PTL-b may cover the upper surface US-PD of the pixel defining layer PDL (e.g., the entire upper surface US-PD), thereby preventing heat generated from the metal pattern layer JHL from being transferred to the functional layer FL.

[0224] In ​ and ​ In the illustrated embodiments, the low thermal conductivity layers PTL-a and PTL-b may be deposited on the pixel defining layer PDL and then patterned together with the pixel defining layer PDL in the same process step. In ​ and ​ In the illustrated embodiments, the second electrode CE may be disposed (e.g., directly disposed) on portions of the low thermal conductivity layers PTL-a and PTL-b not covered by the functional layer FL.

[0225] In ​ In the display panel DP-c according to an embodiment illustrated in, a recessed portion UH-PD may be defined (or formed) on the upper surface US-PD of the pixel defining layer PDL. In one embodiment, the low thermal conductivity layer PTL-c may be disposed in the recessed portion UH-PD.

[0226] In one embodiment, a first width W of the metal pattern layer JHL JH may be less than a third width W of the low thermal conductivity layer PTL-c PT . An edge portion of the functional layer FL may be spaced apart from the metal pattern layer JHL and disposed on the low thermal conductivity layer PTL-c. For example, different from that illustrated in the drawings, an edge portion of the functional layer FL may be spaced apart from the metal pattern layer JHL, not overlap with the low thermal conductivity layer PTL-c, and be disposed on the pixel defining layer PDL. An upper surface of the low thermal conductivity layer PTL-c that is exposed and not covered by the functional layer FL may be covered by the second electrode CE. The second electrode CE may cover the functional layer FL and the metal pattern layer JHL.

[0227] In a display panel DP-c according to an embodiment, since the low thermal conductivity layer PTL-c has a width sufficiently larger than the width of the metal pattern layer JHL and overlaps with the metal pattern layer JHL (e.g., the entire metal pattern layer JHL), heat generated from the metal pattern layer JHL can be prevented from being transferred to the functional layer FL, thereby having excellent display quality.

[0228] In ​ the display panel DP-d according to an embodiment illustrated in, a first recessed portion UH-PD may be defined (or formed) on the upper surface US-PD of the pixel defining layer PDL. In an embodiment, the low thermal conductivity layer PTL-d may be disposed in the first recessed portion UH-PD. For example, a second recessed portion UH-PT may be defined (or formed) on the upper surface of the low thermal conductivity layer PTL-d, and the metal pattern layer JHL may be disposed in the second recessed portion UH-PT.

[0229] The low thermal conductivity layer PTL-d may cover the lower surface and the side surface of the metal pattern layer JHL such that the metal pattern layer JHL may not contact the pixel defining layer PDL.

[0230] An edge portion of the functional layer FL may be spaced apart from the metal pattern layer JHL and disposed on the low thermal conductivity layer PTL-d. For example, different from that illustrated in the drawings, an edge portion of the functional layer FL may be spaced apart from the metal pattern layer JHL, not overlap with the low thermal conductivity layer PTL-d, and be disposed on the pixel defining layer PDL. An upper surface of the low thermal conductivity layer PTL-d that is not covered by the functional layer FL and is exposed may be covered by the second electrode CE. The second electrode CE may cover the functional layer FL and the metal pattern layer JHL.

[0231] In the display panel DP-d according to an embodiment, since the low thermal conductivity layer PTL-d has a width sufficiently larger than the width of the metal pattern layer JHL and overlaps with the metal pattern layer JHL (e.g., the entire metal pattern layer JHL), heat generated from the metal pattern layer JHL can be prevented from being transferred to the functional layer FL, thereby having excellent display quality.

[0232] Hereinafter, a method of manufacturing a display device according to an embodiment will be described with reference to ​ Steps of a method of manufacturing a display panel DP according to an embodiment are illustrated. In the description ​ when, the same / similar reference numerals will be used for the same / similar components as those described with reference to ​ and for convenience of description, redundant descriptions will be omitted. ​

[0233] ​A method of manufacturing a display panel DP according to an embodiment may include: forming a first electrode AE on a circuit element layer D-CL; forming a pixel defining layer PDL on the circuit element layer D-CL; forming a low thermal conductivity layer PTL on the pixel defining layer PDL; forming a metal pattern layer JHL overlapping with the pixel defining layer PDL on the low thermal conductivity layer PTL; providing a preliminary functional layer P-FL to overlap with the pixel defining layer PDL and the first electrode AE; forming a functional layer FL by applying a current to the metal pattern layer JHL to remove a portion of the preliminary functional layer P-FL overlapping with the metal pattern layer JHL; forming a second electrode CE to cover the functional layer FL and the metal pattern layer JHL; and forming a encapsulation layer TFE on the second electrode CE.

[0234] ​ Illustrated is forming a first electrode AE on a circuit element layer D-CL and forming a pixel defining layer PDL on the circuit element layer D-CL.

[0235] The circuit element layer D-CL may be formed on a substrate BL, and the first electrode AE may be formed on the circuit element layer D-CL. The first electrode AE may be patterned and provided on the substrate BL.

[0236] After forming the first electrode AE, a pixel defining layer PDL may be formed on the circuit element layer D-CL. A light-emitting opening OH may be defined / formed in (or through) the pixel defining layer PDL. The upper surface of the patterned first electrode AE may be exposed through each of the light-emitting openings OH.

[0237] ​ Illustrated is forming a low thermal conductivity layer PTL on the pixel defining layer PDL. ​ Illustrated in ​ is an embodiment in which the low thermal conductivity layer PTL covers the pixel defining layer PDL. However, the embodiment is not limited thereto, and in an embodiment where the low thermal conductivity layer is provided in a different shape, the low thermal conductivity layer may be formed to at least partially overlap with the pixel defining layer PDL. ​

[0238] The low thermal conductivity layer PTL may be formed of a polymer-type amorphous carbon film. The formation of the low thermal conductivity layer PTL may include forming a polymer-type amorphous carbon film using a hydrocarbon gas with a deposition facility. For example, the low thermal conductivity layer PTL may be formed by using a chemical vapor deposition (CVD) facility and providing C2H4 gas.

[0239] The low thermal conductivity layer PTL may not be provided on the upper surface of the first electrode AE provided in the light-emitting opening OH, and may be formed on the pixel defining layer PDL.

[0240] ​ ​Illustratively form a metal pattern layer JHL. The metal pattern layer JHL may overlap with the pixel defining layer PDL and be formed on the low thermal conductivity layer PTL.

[0241] The metal pattern layer JHL may be a Joule heating wire. When current is supplied to the metal pattern layer JHL, heat can be generated in the metal pattern layer JHL.

[0242] The metal pattern layer JHL may be disposed (e.g., directly disposed) on the low thermal conductivity layer PTL. The metal pattern layer JHL may be formed to have a width smaller than the width of the low thermal conductivity layer PTL. By forming the metal pattern layer JHL such that its lower surface is sufficiently covered by the low thermal conductivity layer PTL, the transfer of heat generated from the metal pattern layer JHL can be blocked by the low thermal conductivity layer PTL having a low thermal conductivity.

[0243] ​ Illustratively provide a preliminary functional layer P-FL. The preliminary functional layer P-FL may be provided / formed to overlap with the first electrode AE and the pixel defining layer PDL. The preliminary functional layer P-FL may be provided to overlap (e.g., completely overlap) with the light emitting regions PXA-R, PXA-G, and PXA-B (see ​ ) and the peripheral region NPXA (see ​ ). For example, the preliminary functional layer P-FL may include at least one of a hole transport region HTR (see ​ ) and an electron transport region ETR (see ​ ). For example, the emission layer EML (see ​ ) of the light emitting element ED (see ​ ) may not be provided as a common layer like the preliminary functional layer P-FL, but may be patterned and provided to be disposed in each of the light emitting openings OH. For example, in the case where the light emitting element has ​ structure, the charge generation layer CGL (see ​ ) may also be provided as the preliminary functional layer P-FL.

[0244] The preliminary functional layer P-FL forming the hole transport region HTR (see ​ ), the emission layer EML patterned and provided to be disposed in each of the light emitting openings OH, and the preliminary functional layer P-FL forming the electron transport region ETR (see ​ ) may be provided in sequence. For example, in the case where the light emitting element has ​In the case of the structure, the preliminary functional layer P-FL forming the hole transport region HTR-B or HTR-T can be sequentially provided in each of the first light-emitting structure EU-B and the second light-emitting structure EU-T, the light-emitting layer EML-B or EML-T that is patterned and provided in each of the light-emitting openings OH, and the preliminary functional layer P-FL forming the electron transport region ETR-B or ETR-T. For example, the charge generation layer CGL (see ​ ) can also be provided as the preliminary functional layer P-FL after providing the first light-emitting structure EU-B.

[0245] ​ and ​ Illustrate forming the functional layer. After providing / forming the preliminary functional layer P-FL, the formation of the functional layer FL can be performed by applying a current to the metal pattern layer JHL to remove the portion of the preliminary functional layer P-FL that overlaps with the metal pattern layer JHL.

[0246] In the case of applying a current to the metal pattern layer JHL, heat HT can be generated in the metal pattern layer JHL. The heat HT generated in the metal pattern layer JHL can be transferred to the adjacent preliminary functional layer P-FL, and a part of the preliminary functional layer P-FL can be removed by the heat HT. A part of the preliminary functional layer P-FL can be sublimated and removed by the heat generated from the metal pattern layer JHL.

[0247] The portion of the preliminary functional layer P-FL that overlaps with the metal pattern layer JHL and the portion of the preliminary functional layer P-FL adjacent to the metal pattern layer JHL can be removed. A partial region of the preliminary functional layer P-FL can be removed through the metal pattern layer JHL, and the functional layer FL can be formed.

[0248] The functional layer FL can be formed not to overlap with the metal pattern layer JHL. For example, in one embodiment, the functional layer FL can be formed to be spaced apart from the metal pattern layer JHL by a selected distance.

[0249] The shape and size of the separated portion SPP between the metal pattern layer JHL and the functional layer FL can vary according to the process conditions for removing the preliminary functional layer P-FL (such as the amount of current supplied to the metal pattern layer JHL, the time for supplying current to the metal pattern layer JHL, and the resistance characteristics of the metal material used for the metal pattern layer JHL).

[0250] Since the method of manufacturing a display panel DP according to an embodiment includes forming a functional layer FL by using a metal pattern layer JHL that generates heat through a Joule heating method to remove a part of a preliminary functional layer P-FL adjacent to the metal pattern layer JHL, patterning can be easily performed such that the functional layers FL can be non-connected to each other in adjacent light-emitting regions PXA-R, PXA-G, and PXA-B (see ​ ). Since the method of manufacturing a display panel DP according to an embodiment includes providing a metal pattern layer JHL and a low thermal conductivity layer PTL, the preliminary functional layer P-FL can be easily disconnected, and damage to the functional layer FL can be minimized or prevented. Therefore, the method can be used to manufacture a display panel DP capable of preventing deterioration of display quality and color mixing that may occur due to leakage current in adjacent light-emitting regions PXA-R, PXA-G, and PXA-B (see ​ ).

[0251] ​ Illustratively, a second electrode CE is formed. The second electrode CE can be formed to cover the functional layer FL and the metal pattern layer JHL. The second electrode CE can also be disposed in a separated portion SPP between the metal pattern layer JHL and the functional layer FL. The second electrode CE can be provided as a common layer in the light-emitting regions PXA-R, PXA-G, and PXA-B (see ​ ) and the peripheral region NPXA. In one embodiment, the second electrode CE can be provided as a common layer extending over a plurality of light-emitting elements ED.

[0252] ​ Illustratively, a packaging layer TFE is formed. The packaging layer TFE can cover the light-emitting element ED. In ​ , the packaging layer TFE is illustrated as one layer, but the packaging layer TFE can be formed to include a plurality of layers including at least one inorganic layer and at least one organic layer.

[0253] A display panel DP according to an embodiment can include a metal pattern layer JHL disposed on a pixel defining layer PDL, a low thermal conductivity layer PTL disposed (e.g., directly disposed) between the pixel defining layer PDL and the metal pattern layer JHL, and a light-emitting element ED including a functional layer FL disposed so as not to overlap with the metal pattern layer JHL. Therefore, the light-emitting regions PXA-R, PXA-B, and PXA-G can have excellent light-emitting characteristics due to the functional layer FL of good quality, and no leakage current occurs between adjacent light-emitting regions PXA-R, PXA-B, and PXA-G due to the disconnected functional layer, thereby having excellent display quality.

[0254] For example, a method of manufacturing a display panel DP according to an embodiment may include: forming a low thermal conductivity layer PTL disposed on a pixel defining layer PDL, forming a metal pattern layer JHL on the low thermal conductivity layer PTL, and forming a functional layer FL by removing a preliminary functional layer P-FL disposed on the metal pattern layer JHL by using heat generated in the metal pattern layer JHL. Accordingly, the functional layer FL can be easily formed to be disconnected between adjacent light emitting regions, and the film quality of the functional layer disposed in the light emitting regions PXA-R, PXA-B, and PXA-G can be maintained excellent. Correspondingly, the method can be used to manufacture a display panel DP having excellent display quality.

[0255] A display panel DP according to an embodiment may include a disconnected organic layer in a non-light emitting region, thereby preventing current leakage between adjacent light emitting regions and having excellent display quality.

[0256] A method of manufacturing a display panel DP according to an embodiment may include forming a low thermal conductivity layer PTL between a metal pattern layer JHL and a pixel defining layer PDL and disconnecting an organic film by using the metal pattern layer JHL. Accordingly, the method can be used to manufacture a display panel DP having excellent display quality.

[0257] In summarizing the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the embodiments without substantially departing from the principles, spirit, and scope of the present disclosure. Accordingly, the disclosed embodiments are used only in a general and descriptive sense and not for purposes of limitation.

Claims

1. A display panel, characterized in that, The display panel includes: a base substrate; a circuit element layer disposed on the base substrate; a pixel defining layer disposed on the circuit element layer and including a light-emitting opening; a light-emitting element disposed on the circuit element layer, the light-emitting element including: a first electrode, a second electrode facing the first electrode, and a functional layer disposed between the first electrode and the second electrode; a metal pattern layer disposed on the pixel defining layer; and a low thermal conductivity layer disposed between the pixel defining layer and the metal pattern layer.

2. The display panel according to claim 1, wherein The low thermal conductivity layer has a thermal conductivity of 1.0 W / mK or less, the low thermal conductivity layer includes a polymer-type amorphous carbon film, The proportion of sp 3 carbon bonds in the polymer-type amorphous carbon film is in the range of 50% to 70%, and The low thermal conductivity layer has a refractive index of 1.75 or less at a wavelength of 550 nm and a density in the range of 1.2 g / cm 3 to 1.6 g / cm 3 of.

3. The display panel according to claim 1, wherein the functional layer does not overlap with the metal pattern layer, the functional layer includes: a light-emitting layer; and an organic layer disposed on at least one of an upper portion and a lower portion of the light-emitting layer, the organic layer overlaps with the light-emitting opening and a portion of the pixel defining layer adjacent to the light-emitting opening, and is spaced apart from the metal pattern layer.

4. The display panel according to claim 1, wherein In a cross-section perpendicular to the base substrate, a first width of the metal pattern layer in one direction is smaller than a second width of the pixel defining layer in the direction, the first width is 1 / 2 or less of the second width, and the first width of the metal pattern layer in the direction is smaller than a width of the low thermal conductivity layer in the direction.

5. The display panel according to claim 1, wherein The low thermal conductivity layer covers an upper surface and a side surface of the pixel defining layer; or the low thermal conductivity layer is disposed on the upper surface of the pixel defining layer, and a side surface of the pixel defining layer is covered by the functional layer.

6. The display panel according to claim 1, wherein a recessed portion is formed on the upper surface of the pixel defining layer, and the low thermal conductivity layer is disposed in the recessed portion; or a first recessed portion is formed on the upper surface of the pixel defining layer, the low thermal conductivity layer is disposed in the first recessed portion, a second recessed portion is formed on the upper surface of the low thermal conductivity layer, and the metal pattern layer is disposed in the second recessed portion.

7. A display panel is divided into a plurality of light-emitting regions spaced apart from each other and a peripheral region provided between the plurality of light-emitting regions, characterized in that, The display panel includes: a base substrate; a circuit element layer disposed on the base substrate; a pixel defining layer disposed on the circuit element layer and including a light-emitting opening overlapping with each of the plurality of light-emitting regions; a plurality of light-emitting elements, including: a first electrode disposed on the circuit element layer, a second electrode facing the first electrode, and a functional layer disposed between the first electrode and the second electrode; a metal pattern layer disposed in the peripheral region and disposed on the pixel defining layer; and a low thermal conductivity layer disposed between the pixel defining layer and the metal pattern layer.

8. The display panel according to claim 7, wherein the first electrode of the plurality of light-emitting elements overlaps with each of the plurality of light-emitting regions; the second electrode is provided as a common layer extending over the plurality of light-emitting elements; the functional layer does not overlap with the metal pattern layer, and is disposed in the plurality of light-emitting regions and a portion of the peripheral region adjacent to the plurality of light-emitting regions, the functional layer includes: a light-emitting layer; A hole transport region, disposed between the first electrode and the light-emitting layer; and An electron transport region, disposed between the light-emitting layer and the second electrode, The light-emitting layer is disposed in the light-emitting opening; and At least one of the hole transport region and the electron transport region is disposed in the light-emitting opening and extends above the upper surface of the pixel defining layer adjacent to the light-emitting opening, The plurality of light-emitting regions include a first light-emitting region, a second light-emitting region, and a third light-emitting region that emit light in different wavelength ranges; The plurality of light-emitting elements include a first light-emitting layer overlapping with the first light-emitting region, a second light-emitting layer overlapping with the second light-emitting region, and a third light-emitting layer overlapping with the third light-emitting region, The first light-emitting layer, the second light-emitting layer, and the third light-emitting layer contain different light-emitting materials; The plurality of light-emitting elements include the same hole transport region and the same electron transport region for each other, At least one edge portion of the hole transport region and the electron transport region that is set to extend above the upper surface of the pixel defining layer is spaced apart from the metal pattern layer, In a plan view, a metal layer boundary line defined by the edge portion and the edge portion of the metal pattern layer is disposed in the peripheral region; and The edge portion is closer to the plurality of light-emitting regions than the metal layer boundary line.

9. The display panel according to claim 7, wherein The low thermal conductivity layer includes a polymer-type amorphous carbon film, The proportion of sp 3 carbon bonds in the polymer-type amorphous carbon film is in the range of 50% to 70%; and The low thermal conductivity layer has a refractive index of 1.75 or less at a wavelength of 550 nm and a density in the range of 1.2 g / cm 3 to 1.6 g / cm 3 of density.

10. The display panel according to claim 7, wherein In a cross-section perpendicular to the substrate, a first width of the metal pattern layer in one direction is smaller than each of a second width of the upper surface of the pixel defining layer adjacent to the metal pattern layer in the direction and a third width of the upper surface of the low thermal conductivity layer adjacent to the metal pattern layer in the direction, and In a plan view, the size of the metal pattern layer is smaller than the size of the pixel defining layer.

Images