Integrated component

Abstract

In some embodiments, the disclosure relates to an integrated component comprising: a substrate; a semiconductor layer on the substrate and including a first structure as one of a sound port, a sealed cavity, or a proof mass, and a second structure as one of a sound port, a sealed cavity, or a proof mass, wherein the second structure is a sound port, a sealed cavity, or a proof mass different from the first structure; the piezoelectric layer is located on the semiconductor layer and overlies the first structure and the second structure. An air gap extends from an upper surface of the piezoelectric layer into the semiconductor layer, wherein the first structure and a portion of the piezoelectric layer overlying the first structure are separated from the second structure and a portion of the piezoelectric layer overlying the second structure by the air gap.

Description

Technical Field

[0001] An embodiment of the utility model relates to an integrated component. Background Art

[0002] Many modern electronic components include sensors. Sensors capable of detecting sound, pressure, and acceleration are used for a variety of purposes. Some components incorporate multiple different types of sensors and use them to collect a variety of data. Some sensors use piezoelectric materials to convert strain into an electrical signal. This signal is sometimes sent to an application-specific integrated circuit (ASIC). Utility Model Content

[0003] An embodiment of the present invention provides an integrated component comprising: a substrate; a semiconductor layer located on the substrate and comprising a first structure serving as one of a sound port, a sealed cavity or a proof mass block, and a second structure serving as one of a sound port, a sealed cavity or a proof mass block, wherein the second structure is a sound port, a sealed cavity or a proof mass block different from the first structure; a piezoelectric layer located on the semiconductor layer and overlying the first structure and the second structure; an air gap extending from the upper surface of the piezoelectric layer into the semiconductor layer, wherein the first structure and a portion of the piezoelectric layer overlying the first structure are separated from the second structure and a portion of the piezoelectric layer overlying the second structure by the air gap.

[0004] In some embodiments, the integrated component further comprises: an insulating pillar positioned within the semiconductor layer, wherein the air gap comprises a first region having a first width and flush with the insulating pillar, and a second region having a second width between the first region and the upper surface of the semiconductor layer, wherein an outer sidewall of the insulating pillar is exposed at the first region, and wherein the first width is greater than the second width. In some embodiments, the integrated component further comprises: a third structure positioned within the semiconductor layer, wherein the third structure comprises an acoustic port, a sealed cavity, or a proof mass distinct from the first and second structures, such that the acoustic port, the sealed cavity, and the proof mass are positioned within the semiconductor layer. In some embodiments, the integrated component further comprises: an insulating pillar positioned within the semiconductor layer, wherein when one of the first or second structures is an acoustic port, one or more arms overlie the acoustic port and are separated from the semiconductor layer by the insulating pillar. In some embodiments, the one or more arms are positioned directly above the acoustic port and are separated from each other by an additional air gap. In some embodiments, when one of the first or second structures comprises a sealed cavity, the piezoelectric layer comprises an opening extending through the piezoelectric layer and aligned with the sealed cavity. In some embodiments, the integrated component further comprises an insulating pillar within the semiconductor layer, wherein when one of the first structure or the second structure is a proof mass block, the semiconductor layer comprises a first portion and a second portion, the first portion comprising the proof mass block and a first arm attached to the proof mass block, the second portion extending below the first portion, and the first portion being separated from the second portion by the insulating pillar.

[0005] An embodiment of the present invention provides an integrated component including: a substrate having a first part and a second part; a first sensor is located on the first part of the substrate, the first sensor having a first movable structure, the first movable structure being one of the first arm coupled to the inspection mass block, the cap covering the sealed cavity, or the one or more arms covering the sound port extending through the substrate; a second sensor is located on the second part of the substrate, the second sensor having a second movable structure, the second movable structure being one of the first arm coupled to the inspection mass block, the cap covering the sealed cavity, or the one or more arms covering the sound port extending through the substrate, the second movable structure being different from the first movable structure; an application-specific integrated circuit (ASIC) is configured to receive a first signal and a second signal from the first sensor and the second sensor, respectively; a package surrounds the substrate and the application-specific integrated circuit, the package having a port connecting the internal area of the package to the surrounding environment outside the package.

[0006] In some embodiments, when the first movable structure is one or more arms overlying the acoustic port extending through the substrate, the port of the package is located directly below the acoustic port to directly couple the acoustic port to the ambient environment outside the package. In some embodiments, a semiconductor layer is located below the first movable structure and the second movable structure; wherein, when the first movable structure and the second movable structure are one or more arms overlying the acoustic port extending through the substrate and a cap overlying a sealed cavity, an air gap between the one or more arms and the semiconductor layer couples the ambient environment outside the package to the cap overlying the sealed cavity. In some embodiments, the port and the acoustic port of the package are centered about a first axis extending through the port and the acoustic port of the package, and wherein the second movable structure is offset from the port such that the package extends between the ambient environment and the second movable structure. In some embodiments, the integrated component further comprises an air gap located between the first movable structure and the second movable structure, the air gap comprising a first region having a first width directly between the first movable structure and the second movable structure and a second region having a second width located below the first region, wherein the second width is greater than the first width. In some embodiments, the integrated component further comprises: a semiconductor layer, wherein the first movable structure and the second movable structure are flush with and overly the semiconductor layer; and an insulating pillar coupling one of the first movable structure or the second movable structure to the semiconductor layer. In some embodiments, the integrated component further comprises: a piezoelectric layer overlying the first movable structure and the second movable structure, wherein the piezoelectric layer is configured to convert strain in the first movable structure and the second movable structure into a first signal and a second signal, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A-Figure 1C Some embodiments of an integrated chip having a piezoelectric micromachined ultrasonic transducer (PMUT), a pressure sensor, and an accelerometer on a common substrate are shown in cross-sectional and top views.

[0009] Figure 2 Cross-sectional views of some embodiments of a package holding an integrated chip having a PMUT, a pressure sensor, and an accelerometer on a substrate are shown.

[0010] Figure 3A-Figure 3E Cross-sectional views of some additional embodiments of integrated chips having two or more sensors in a semiconductor layer on a substrate are shown.

[0011] Figure 4-Figure 19 Cross-sectional views of some embodiments of a method of forming an integrated chip having a PMUT, a pressure sensor, and an accelerometer on a substrate are shown.

[0012] Figure 20 A flow chart illustrating some embodiments of a method of forming an integrated chip having two or more sensors on a substrate, the two or more sensors being separated by an air gap. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and similar terms, may be used herein to describe the relationship of one device or feature illustrated in the figures to another device or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. Elements may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] Sensors are used to acquire a variety of different data in integrated components. In some components, multiple different types of sensors can be used to perform all the functions expected of the component. Some components achieve this by including multiple different sensor chips in a single package. Different sensor chips are connected to different ASICs via wire bonding. However, multiple wire bonds introduce parasitic electrical effects (e.g., parasitic capacitance and parasitic resistance) between the wire bonds, the sensor chips, and the integrated circuit. In addition, as consumers expect components and products to become smaller and smaller, the ability to include multiple sensor chips in a single package may be limited by the available space in the component. Forming multiple sensors on a single chip can reduce the number of wire bonds used and can reduce the space used by the sensor chips, although separate processes using separate chip designs can be very expensive.

[0016] The present disclosure provides an integrated process for forming multiple different sensors on a chip. The sensors are formed by forming multiple insulating layers within a semiconductor layer. A piezoelectric layer is formed on the semiconductor layer to convert the strain caused by the sensor into an electrical signal. The multiple insulating layers are used as sacrificial layers and etching stop layers in the formation of two or more structures. The two or more structures combined with the piezoelectric layer include two or more different sensors overlying a common substrate. In addition, the air gap between the two or more sensors reduces the interference caused by the movement of the two or more structures. Since the formation of the insulating layer, the piezoelectric layer and the semiconductor layer are all processes shared by different sensors, the proposed method reduces the number of steps required to form multiple sensors on a substrate. In addition, compared with an integrated component with multiple separate sensor chips, a chip with multiple sensors can reduce testing costs because the number of chips to be tested is reduced.

[0017] Figure 1A-Figure 1C Some embodiments of an integrated chip having a piezoelectric micromachined ultrasonic transducer (PMUT), a pressure sensor, and an accelerometer on a common substrate are shown in cross-sectional view 100a and top views 100b, 100c. Figure 1B and Figure 1C The top views 100b, 100c may be, for example, along Figure 1A The line A-A' in the figure is intercepted.

[0018] Semiconductor layer 104 overlies substrate 102. Piezoelectric layer 106 is located on semiconductor layer 104. Two or more sensors 116a-116c are integrated into semiconductor layer 104 and piezoelectric layer 106. In some embodiments, two or more sensors 116a-116c include a piezoelectric micromachined ultrasonic transducer (PMUT) 116a, a pressure sensor 116b, and an accelerometer 116c. In other embodiments, two or more sensors 116a-116c include two different sensors among PMUT 116a, pressure sensor 116b, and / or accelerometer 116c. Each of the two or more sensors 116a-116c includes a movable structure of two or more movable structures 120 and a portion of piezoelectric layer 106 overlying the movable structure. In some embodiments, the two or more moving structures 120 include one or more arms 117 within the PMUT 116a, a first arm 118 within the accelerometer 116c, and a cap 119 within the pressure sensor 116b.

[0019] PMUT 116a includes an acoustic port 113, one or more arms 117, and a first portion 106a of piezoelectric layer 106 overlying one or more arms 117. Pressure sensor 116b includes a sealed cavity 112, a cap 119 overlying sealed cavity 112, and a second portion 106b of piezoelectric layer 106 overlying cap 119. Accelerometer 116c includes a proof mass 115, a first arm 118, and a third portion 106c of piezoelectric layer 106 overlying first arm 118. In addition to or in lieu of PMUT 116a, a microphone may extend over acoustic port 113 as one or more arms. Embodiments described below that include PMUT 116a may also include a microphone extending over acoustic port 113.

[0020] In some embodiments, one or more arms 117 of the PMUT 116a and the first arm 118 of the accelerometer 116c are separated from the semiconductor layer 104 by a plurality of insulating pillars 108. In some embodiments, the plurality of insulating pillars 108 further separate the PMUT 116a and the accelerometer 116c from the sealed cavity 112.

[0021] Two or more moving structures 120 are separated by an air gap 114. Air gap 114 is configured to reduce interference between the two or more moving structures 120, thereby reducing noise in the signals emitted by the two or more sensors 116a-116c. Air gap 114 has a first region having a first width extending directly between the two or more moving structures 120, and a second region having a second width extending below the first region. The second region is flush with the insulating pillar 108 and exposes the sidewalls of the insulating pillar 108. The first width is smaller than the second width. In some embodiments, the first width is between 2 microns and 100 microns, between 2.5 microns and 90 microns, between 3 microns and 60 microns, etc. A plurality of conductive lines 109 are embedded in the piezoelectric layer 106, and a plurality of contacts 110 are coupled to the plurality of conductive lines 109 and extend across the outer surface of the piezoelectric layer 106.

[0022] like Figure 1B As shown in the top view 100b of FIG. 1 , one or more arms 117 and the first arm 118 are isolated from the semiconductor layer 104 by the air gap 114. The isolation of the one or more arms 117 and the first arm 118 results in a greater degree of motion, which can be used to measure incoming sound waves or acceleration of the component. The greater degree of motion further causes the piezoelectric layer (see FIG. 1 ) to Figure 1A 106) and the first and third parts (see Figure 1A 106a, 106c) are subjected to a greater amount of strain, resulting in a stronger signal output from the two or more sensors 116a-116c. In addition, one or more arms are separated from each other by an air gap. Figure 1C As shown in top view 100c, a portion of the semiconductor layer 104 including the pressure sensor 116b may be separated from the rest of the semiconductor layer 104 by an air gap 114 that continuously surrounds the portion of the semiconductor layer 104 including the pressure sensor 116b.

[0023] Integrating two or more sensors 116a-116c onto substrate 102 can reduce the space occupied by the sensors in the finished product, thereby increasing the number of applications in which the sensors can be used. Integrating two or more sensors 116a-116c onto substrate 102 can also reduce the cost of applications using the sensors because a single sensor chip can be formed and used instead of two or more sensor chips. The cost of adding an additional step in the process flow to form two or more sensors 116a-116c on the same substrate 102 is significantly lower than the cost of forming two separate sensor chips for the same application. Components using multiple separate chips also require independent testing of the individual chips using different tests and potentially multiple test environments. Sensor chips with two or more sensors 116a-116c can reduce the number of tests that need to be run, further reducing costs.

[0024] Figure 2 A cross-sectional view 200 of some embodiments of a package holding an integrated chip having a PMUT, a pressure sensor, and an accelerometer on a substrate is shown.

[0025] The package 208 surrounds the substrate 102 and further surrounds an application-specific integrated circuit (ASIC) 202. The ASIC 202 is coupled to the contacts 110 in the piezoelectric layer 106 via a plurality of wire bonds 204. The ASIC 202 is configured to read and process signals emitted by two or more sensors 116a-116c. In designs using multiple separate sensor chips, multiple separate ASIC chips are also used to read and process the signals from the sensors. The two or more sensors 116a-116c on the substrate 102 can be coupled to the ASIC 202, which can include circuitry for reading and processing the signals from the two or more sensors 116a-116c, thereby reducing the number of ASIC chips used and further reducing the minimum size of the ASIC chip. In some embodiments, a second insulating post 210 is located on the substrate 102 below the accelerometer 116c.

[0026] Package 208 includes port 206. In some embodiments, in which one of the two or more sensors 116a-116c is a PMUT 116a, port 206 is located directly below an acoustic port 113 extending through substrate 102. That is, port 206 and acoustic port 113 are centered about an axis extending through port 206 and acoustic port 113. This alignment of port 206 and acoustic port 113 allows acoustic port 113 to directly receive mechanical waves transmitted in the ambient environment outside package 208, thereby enhancing the sensitivity of PMUT 116a. In embodiments that include pressure sensor 116b and / or accelerometer 116c, pressure sensor 116b and accelerometer 116c are offset from port 206 to mitigate the effects of mechanical waves on the signals emitted by pressure sensor 116b and / or accelerometer 116c.

[0027] Furthermore, port 206 is located directly below acoustic port 113, resulting in increased sensitivity for PMUT 116a while also creating a path through the air gap between acoustic port 113 and one or more arms that couples the interior of package 208 to the ambient environment outside of package 208. This coupling of the interior of package 208 with the exterior of package 208 results in pressure sensor 116b having a sealed cavity 112 on one side of cap 119 and an area coupled to the ambient environment on the opposite side of cap 119. This configuration allows for more accurate readings from pressure sensor 116b because the air pressure inside package 208 is substantially the same as the air pressure in the ambient environment, without requiring the use of more than one port 206 in package 208.

[0028] Figure 3A-Figure 3E Cross-sectional views 300a-300e of some additional embodiments of an integrated chip having two or more sensors in a semiconductor layer on a substrate are shown.

[0029] In some embodiments, as Figure 3A and Figure 3B As shown in cross-sectional views 300a and 300b of FIG, two or more sensors 116a-116c may include a PMUT 116a, a pressure sensor 116b, and an accelerometer 116c arranged in any order. For example, the PMUT 116a may be located between the accelerometer 116c and the pressure sensor 116b, as shown in FIG. Figure 3A Alternatively, the accelerometer 116c may be located between the PMUT 116a and the pressure sensor 116b, as shown in FIG. Figure 3B In some embodiments, two or more sensors 116a-116c are not arranged linearly. For example, a first sensor (e.g., PMUT 116a) may be offset from a second sensor (e.g., a pressure sensor) in a first direction, while a third sensor (e.g., accelerometer 116c) may be offset from the second sensor in a second direction perpendicular to the first direction.

[0030] In some embodiments, as Figure 3C 、 Figure 3D and Figure 3E As shown in cross-sectional views 300c, 300d, and 300e of FIG, the two or more sensors 116a-116c may include any combination of two different sensors (e.g., PMUT 116a, pressure sensor 116b, or accelerometer 116c). For example, the two or more sensors 116a-116c may be a PMUT 116a and an accelerometer 116c (e.g., Figure 3C As shown), pressure sensor 116b and PMUT 116a (as shown Figure 3D), or pressure sensor 116b and accelerometer 116c (as shown Figure 3E shown). Figure 3C 、 Figure 3D and Figure 3E The embodiment shown in further reduces the amount of space occupied by the package in applications where one of the two or more sensors 116a-116c is not used.

[0031] Figure 4-Figure 19 Some embodiments of the method of forming an integrated chip having a PMUT, a pressure sensor, and an accelerometer on a substrate are shown in cross-sectional views 400-1900. Figure 4-Figure 19 is described in terms of methods, but it should be understood that Figure 4-Figure 19 The structure disclosed in is not limited to this method, but can exist independently as a structure independent of this method.

[0032] like Figure 4 As shown in the cross-sectional view 400 of FIG, a substrate 102 is provided. A first sacrificial layer 402 is formed on the substrate 102. The first sacrificial layer 402 is formed by depositing a first conformal sacrificial layer on the first side 102f of the substrate 102. In some embodiments, the first conformal sacrificial layer is formed using one of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other suitable deposition process, or a combination thereof. In some embodiments, the first conformal sacrificial layer is or includes an oxide (e.g., SiO2), etc. The first conformal sacrificial layer is then covered with a first mask layer 406, which is then patterned. In some embodiments, the first mask layer 406 is or includes a hard mask, a photoresist, etc.

[0033] After patterning the first mask layer 406, a first etching process 404 is performed to remove the portion of the first conformal sacrificial layer exposed by the first mask layer 406 and leave the first sacrificial layer 402. In some embodiments, the first etching process 404 is a dry etching process (e.g., plasma etching). The first mask layer 406 is then removed to leave the first sacrificial layer 402 on the substrate 102.

[0034] like Figure 5As shown in cross-sectional view 500 of FIG, a first semiconductor layer 502 is formed over the substrate 102 and the first sacrificial layer 402. The first semiconductor layer 502 includes a first portion 504a and a second portion 504b. In another embodiment, the first semiconductor layer 502 additionally includes a third portion 504c. In some embodiments, the first sacrificial layer 402 is located within one of the first portion 504a, the second portion 504b, or the third portion 504c. In some embodiments, the first semiconductor layer 502 is or includes polysilicon, etc. The first semiconductor layer 502 is formed using epitaxy, a deposition process (e.g., CVD, PVD, ALD), some other suitable deposition process, or a combination thereof. After forming the first semiconductor layer 502, a planarization process (e.g., a chemical mechanical planarization (CMP) process) is performed to provide the first semiconductor layer 502 with a substantially planar upper surface.

[0035] like Figure 6 As shown in cross-sectional view 600 of FIG, a second sacrificial layer 602 is formed on the first semiconductor layer 502. The second sacrificial layer 602 is formed by depositing a second conformal sacrificial layer on the first semiconductor layer 502. In some embodiments, the second conformal sacrificial layer is formed using CVD, PVD, ALD, some other suitable deposition process, or a combination thereof. In some embodiments, the second conformal sacrificial layer is or includes an oxide (e.g., SiO2). The second conformal sacrificial layer is then covered with a second mask layer 606, which is then patterned. In some embodiments, the second mask layer 606 is or includes a hard mask, a photoresist, or the like.

[0036] After patterning the second mask layer 606, a second etching process 604 is performed to remove the portion of the second conformal sacrificial layer exposed by the second mask layer 606. In some embodiments, the second etching process 604 is a dry etching process (e.g., plasma etching). The second mask layer 606 is then removed to leave the second sacrificial layer 602 on the first semiconductor layer 502. In some embodiments, the second sacrificial layer 602 has an opening above the center portion of the first sacrificial layer 402.

[0037] like Figure 7As shown in cross-sectional view 700 of FIG, a second semiconductor layer 702 is formed over the first semiconductor layer 502 and the second sacrificial layer 602. The second semiconductor layer 702 includes a first portion 704a and a second portion 704b. In another embodiment, the second semiconductor layer 702 further includes a third portion 704c. The first portion 704a, the second portion 704b, and the third portion 704c are located directly above the first portion 504a, the second portion 504b, and the third portion 504c of the first semiconductor layer 502, respectively. In some embodiments, the second semiconductor layer 702 is or includes polysilicon, etc. The second semiconductor layer 702 is formed using epitaxy, a deposition process (e.g., CVD, PVD, ALD), some other suitable deposition process, or a combination thereof. After forming the second semiconductor layer 702, a planarization process (e.g., a chemical mechanical planarization (CMP) process) is performed to ensure that the second semiconductor layer 702 has a substantially flat upper surface. The first semiconductor layer 502 and the second semiconductor layer 702 together form the semiconductor layer 104. In some embodiments, the semiconductor layer 104 is or includes one of silicon (Si), silicon-germanium (SiGe), and the like.

[0038] like Figure 8 As shown in cross-sectional view 800 of FIG, a third etching process 802 is performed on semiconductor layer 104 according to the pattern of third mask layer 804. In some embodiments, third etching process 802 is a dry etching process (e.g., plasma etching). Third etching process 802 creates a plurality of trenches 806 extending to first portion 602a of second sacrificial layer 602 in the region of the integrated component. The region of the integrated component is the region where sealed cavity 112 will be formed during the process of forming pressure sensor 116b.

[0039] like Figure 9 As shown in the cross-sectional view 900 of FIG, a fourth etching process 902 is performed on the semiconductor layer 104 to remove the first portion 602a of the second sacrificial layer 602. In some embodiments, the fourth etching process 902 is a wet etching process or a vapor etching process configured to etch the material of the second sacrificial layer 602 at a greater rate than the material of the semiconductor layer 104. The fourth etching process 902 creates an unsealed cavity 904 within the semiconductor layer 104.

[0040] like Figure 10As shown in the cross-sectional view 1000 of FIG, a sealed cavity 112 is formed. The sealed cavity 112 is formed by conformal deposition of the same material as the semiconductor layer 104, filling the plurality of trenches 806. In some embodiments, the conformal deposition is or includes CVD, PVD, ALD, some other suitable deposition process, or a combination thereof. In some embodiments, when the sealed cavity 112 is sealed, the conformal deposition process partially fills the sealed cavity 112 such that the thickness of the sealed cavity 112 is less than the thickness of the second sacrificial layer 602. In some embodiments, the pressure of the sealed cavity 112 is, for example, 1 mTorr to 1000 mTorr.

[0041] like Figure 11 As shown in the cross-sectional view 1100 of , a first piezoelectric layer 1102 and a first conductive layer 1104 are formed on the semiconductor layer 104. The first piezoelectric layer 1102 and the first conductive layer 1104 are formed separately using one of CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing. After the first conductive layer 1104 is deposited, it is patterned. The patterning of the first conductive layer 1104 is performed using a fifth etching process 1106 and a fourth mask layer 1108. The fourth mask layer 1108 is or includes a hard mask or photoresist, and in some embodiments, is patterned using an additional etching step or photolithography. In some embodiments, the fifth etching process 1106 is dry etching (e.g., plasma dry etching). The fourth mask layer 1108 is then removed.

[0042] like Figure 12 As shown in the cross-sectional view 1200 of , a second piezoelectric layer 1202 and a second conductive layer 1204 are formed on the first piezoelectric layer 1102 and the first conductive layer 1104. The second piezoelectric layer 1202 and the second conductive layer 1204 are separately formed using one of CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing. After the second conductive layer 1204 is deposited, it is patterned. The patterning of the second conductive layer 1204 is performed using a sixth etching process 1206 and a fifth mask layer 1208. The fifth mask layer 1208 is or includes a hard mask or photoresist, and in some embodiments, is patterned using an additional etching step or photolithography. In some embodiments, the sixth etching process 1206 is dry etching (e.g., plasma dry etching). The fifth mask layer 1208 is then removed. The first conductive layer 1104 and the second conductive layer 1204 together form a plurality of conductive lines 109.

[0043] like Figure 13As shown in cross-sectional view 1300 of FIG, a third piezoelectric layer 1302 is formed to cover the second conductive layer 1204. The first piezoelectric layer 1102, the second piezoelectric layer 1202, and the third piezoelectric layer 1302 together form the piezoelectric layer 106. In some embodiments, the piezoelectric layer 106 is or includes one of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), and the like. In some embodiments, the first conductive layer 1104 and the second conductive layer 1204 are or include molybdenum (Mo), gold (Au), platinum (Pt), and the like.

[0044] like Figure 14 As shown in cross-sectional view 1400 of FIG, a plurality of etching processes 1406 are performed to produce a first plurality of openings 1402 and a second plurality of openings 1404 extending into the piezoelectric layer 106. The first plurality of openings 1402 extend to the first conductive layer 1104 of the plurality of conductive lines 109, while the second plurality of openings 1404 extend to the second conductive layer 1204 of the plurality of conductive lines 109.

[0045] like Figure 15 As shown in cross-sectional view 1500 of FIG, a plurality of contacts 110 are formed in first plurality of openings 1402 and second plurality of openings 1404. Contacts 110 are formed by depositing a conformal conductive layer over piezoelectric layer 106 and then patterning the conformal conductive layer to remove portions of the conformal conductive layer outside contacts 110. In some embodiments, contacts 110 are or include aluminum-copper alloy (AlCu), another conductive material, or the like. Contacts 110 are coupled to conductive lines 109.

[0046] like Figure 16 As shown in cross-sectional view 1600 of FIG, a sixth mask layer 1604 is formed over the piezoelectric layer 106. The sixth mask layer 1604 includes a hard mask or a photoresist. The sixth mask layer 1604 is then patterned. After the sixth mask layer 1604 is patterned, a seventh etching process 1602 is performed to pattern the piezoelectric layer 106. The seventh etching process 1602 etches through the piezoelectric layer 106 to form a second opening 1606 and expose the semiconductor layer 104.

[0047] like Figure 17As shown in cross-sectional view 1700 of FIG, a seventh mask layer 1704 is formed over the piezoelectric layer 106. Seventh mask layer 1704 includes a hard mask or a photoresist. Seventh mask layer 1704 is then patterned. After patterning seventh mask layer 1704, an eighth etching process 1702 is performed to pattern the second semiconductor layer 702 below the second opening 1606, thereby forming an air gap 114. Eighth etching process 1702 etches into semiconductor layer 104 to expose portions of the second sacrificial layer 602 between first portion 704a and second portion 704b, and between second portion 704b and third portion 704c of the second semiconductor layer. In some embodiments, eighth etching process 1702 further forms an additional air gap 1706 within first portion 704a.

[0048] like Figure 18 As shown in cross-sectional view 1800 of FIG, an eighth mask layer 1804 is formed and patterned on the second side 102s of the substrate 102. A ninth etching process 1802 is then performed to remove portions of the substrate 102 and the semiconductor layer 104 corresponding to the sound port 113 and surrounding the proof mass 115. The ninth etching process 1802 further exposes portions of the first sacrificial layer 402 and the second sacrificial layer 602. In some embodiments, the ninth etching process 1802 is one or more dry etching processes (e.g., plasma dry etching). The first sacrificial layer 402 covers the bottom surface of the proof mass 115 to prevent etching of the proof mass 115. Furthermore, the second sacrificial layer 602 covers the bottom surface of the first arm 118 to prevent etching of the first arm 118.

[0049] like Figure 19 As shown in the cross-sectional view 1900, a tenth etching process 1902 is performed on the integrated component to remove the second sacrificial layer (see Figure 18 602) and the first sacrificial layer (see Figure 18 The tenth etching process 1902 is configured to remove the first sacrificial layer (see Figure 18 402), while only partially removing the second sacrificial layer (see Figure 18 602) to leave the insulating pillar 108 in the semiconductor layer 104. In some embodiments, after the tenth etching process 1902, part of the first sacrificial layer (see Figure 18 402) is retained as the second insulating column (see Figure 2 The tenth etching process 1902 expands the air gap 114 so that the air gap 114 has a wide portion flush with the insulating pillar 108 and a narrow portion separating the wide portion from the surface of the semiconductor layer 104.

[0050] Figure 20Flowchart 2000 illustrates some embodiments of a method of forming an integrated chip having two or more sensors on a substrate, the two or more sensors being separated by an air gap.

[0051] Although the method is illustrated and described below as a series of actions or events, it should be understood that the illustrated order of these actions or events should not be interpreted as restrictive. For example, some actions can occur in different orders and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, not all shown actions are required to realize one or more aspects or embodiments described herein. In addition, one or more actions described herein can be performed in one or more separate actions and / or stages.

[0052] At act 2002 , a first sacrificial layer is positioned over a substrate having a first side and a second side. Figure 4 A cross-sectional view 400 corresponding to some embodiments of act 2002 is shown.

[0053] At act 2004 , a first semiconductor layer having a first portion, a second portion, and a third portion is formed on a first side of a substrate, wherein the third portion is directly above the first sacrificial layer. Figure 5 Cross-sectional view 500 is shown corresponding to some embodiments of act 2004 .

[0054] At act 2006 , a second sacrificial layer comprising a plurality of segments is formed over the first portion, the second portion, and the third portion of the first semiconductor layer, wherein a first segment of the plurality of segments is located over the second portion of the first semiconductor layer. Figure 6 A cross-sectional view 600 corresponding to some embodiments of act 2006 is shown.

[0055] In action 2008, a second semiconductor layer is formed having a first portion, a second portion, and a third portion, the second semiconductor layer overlying a second sacrificial layer, wherein the second portion of the second semiconductor layer overlies the first segment of the second sacrificial layer, and wherein the first portion, the second portion, and the third portion of the second semiconductor layer respectively overly the first portion, the second portion, and the third portion of the first semiconductor layer. Figure 7 A cross-sectional view 700 corresponding to some embodiments of act 2008 is shown.

[0056] At act 2010 , a sealed cavity is formed between the second semiconductor layer and the first semiconductor layer by removing a first segment of the second sacrificial layer. Figures 8-10 Cross-sectional views 800 - 1000 are shown corresponding to some embodiments of act 2010 .

[0057] At act 2012 , a piezoelectric layer is formed over the second semiconductor layer, the piezoelectric layer surrounding the plurality of conductive lines. Figure 11-13 Cross-sectional views 1100 - 1300 are shown corresponding to some embodiments of act 2012 .

[0058] At act 2014 , a plurality of contacts are formed to couple to the plurality of conductive lines. Figure 14-15 Cross-sectional views 1400 - 1500 are shown corresponding to some embodiments of act 2014 .

[0059] In act 2016 , the piezoelectric layer and the second semiconductor layer are etched to form an air gap that separates the first portion, the second portion, and the third portion of the second semiconductor layer and exposes the second sacrificial layer. Figure 16-17 Cross-sectional views 1600 - 1700 are shown corresponding to some embodiments of act 2016 .

[0060] At act 2018 , the substrate and the first semiconductor layer are etched from the second side of the substrate to delineate one or more structures within the first portion and the third portion of the first semiconductor layer, wherein the etching stops at the first sacrificial layer and the second sacrificial layer. Figure 18 A cross-sectional view 1800 corresponding to some embodiments of act 2018 is shown.

[0061] In action 2020 , the first sacrificial layer and the second sacrificial layer are etched to remove portions of the first sacrificial layer and the second sacrificial layer exposed when forming the air gap and delineating one or more structures, thereby expanding the air gaps between the first portion, the second portion, and the third portion of the second semiconductor layer. Figure 19 A cross-sectional view 1900 corresponding to some embodiments of act 2020 is shown.

[0062] Thus, the present disclosure is directed to a method of forming an integrated chip having two or more sensors on a substrate, the two or more sensors being separated by an air gap.

[0063] Therefore, in some embodiments, the present disclosure relates to an integrated component comprising: a substrate; a semiconductor layer located on the substrate and including a first structure that is one of a sound port, a sealed cavity, or a proof mass block, and a second structure that is one of a sound port, a sealed cavity, or a proof mass block, wherein the second structure is a sound port, a sealed cavity, or a proof mass block different from the first structure; a piezoelectric layer located on the semiconductor layer and overlying the first structure and the second structure; an air gap extending from the upper surface of the piezoelectric layer into the semiconductor layer, wherein the first structure and a portion of the piezoelectric layer overlying the first structure are separated from the second structure and a portion of the piezoelectric layer overlying the second structure by the air gap.

[0064] In some embodiments, the integrated component further comprises: an insulating pillar positioned within the semiconductor layer, wherein the air gap comprises a first region having a first width and flush with the insulating pillar, and a second region having a second width between the first region and the upper surface of the semiconductor layer, wherein an outer sidewall of the insulating pillar is exposed at the first region, and wherein the first width is greater than the second width. In some embodiments, the integrated component further comprises: a third structure positioned within the semiconductor layer, wherein the third structure comprises the acoustic port, the sealed cavity, or the proof mass, which is different from the first and second structures, such that the acoustic port, the sealed cavity, and the proof mass are positioned within the semiconductor layer. In some embodiments, the integrated component further comprises: an insulating pillar positioned within the semiconductor layer, wherein, when one of the first or second structures is the acoustic port, one or more arms overlie the acoustic port and are separated from the semiconductor layer by the insulating pillar. In some embodiments, the one or more arms are positioned directly above the acoustic port and separated from each other by an additional air gap. In some embodiments, when one of the first or second structures comprises the sealed cavity, the piezoelectric layer comprises an opening extending through the piezoelectric layer and aligned with the sealed cavity. In some embodiments, the integrated component further comprises an insulating pillar within the semiconductor layer, wherein when one of the first structure or the second structure is the proof mass block, the semiconductor layer comprises a first portion and a second portion, the first portion comprising the proof mass block and a first arm attached to the proof mass block, the second portion extending below the first portion, and the first portion being separated from the second portion by the insulating pillar.

[0065] In other embodiments, the present disclosure relates to an integrated component, including a substrate having a first portion and a second portion; a first sensor located on the first portion of the substrate, the first sensor having a first movable structure, the first movable structure being one of a first arm coupled to a proof mass block, a cap covering a sealed cavity, or one of one or more arms covering an acoustic port extending through the substrate; a second sensor located on the second portion of the substrate, the second sensor having a second movable structure, the second movable structure being one of a first arm coupled to a proof mass block, a cap covering a sealed cavity, or one of one or more arms covering an acoustic port extending through the substrate, the second movable structure being different from the first movable structure; an application-specific integrated circuit (ASIC) configured to receive a first signal and a second signal from the first sensor and the second sensor, respectively; a package surrounding the substrate and the application-specific integrated circuit, the package having a port connecting an internal area of the package to an ambient environment outside the package.

[0066] In other embodiments, when the first movable structure is the one or more arms overlying the acoustic port extending through the substrate, the port of the package is located directly below the acoustic port to directly couple the acoustic port to the ambient environment outside the package. In other embodiments, a semiconductor layer is located below the first and second movable structures; wherein, when the first and second movable structures are the one or more arms overlying the acoustic port extending through the substrate and the cap overlying the sealed cavity, an air gap between the one or more arms and the semiconductor layer couples the ambient environment outside the package to the cap overlying the sealed cavity. In other embodiments, the port and the acoustic port of the package are centered about a first axis extending through the port and the acoustic port of the package, and wherein the second movable structure is offset from the port such that the package extends between the ambient environment and the second movable structure. In other embodiments, the integrated component further comprises: an air gap located between the first and second mobile structures, the air gap comprising a first region having a first width directly between the first and second mobile structures and a second region having a second width located below the first region, wherein the second width is greater than the first width. In other embodiments, the integrated component further comprises: a semiconductor layer, wherein the first and second mobile structures are flush with and overlying the semiconductor layer; and an insulating pillar coupling one of the first and second mobile structures to the semiconductor layer. In other embodiments, the integrated component further comprises: a piezoelectric layer overlying the first and second mobile structures, wherein the piezoelectric layer is configured to convert strain of the first and second mobile structures into the first and second signals, respectively.

[0067] In some further embodiments, the present disclosure relates to a method for forming an integrated device, comprising: forming a first sacrificial layer on a substrate having a first side and a second side; forming a first semiconductor layer having a first portion, a second portion, and a third portion on the first side of the substrate, wherein the third portion is located directly above the first sacrificial layer; forming a second sacrificial layer comprising a plurality of segments on the first portion, the second portion, and the third portion of the first semiconductor layer, wherein the first segment of the plurality of segments is located above the second portion of the first semiconductor layer; forming a second semiconductor layer having a first portion, a second portion, and a third portion to cover the second sacrificial layer, wherein the second portion of the second semiconductor layer covers the first segment of the second sacrificial layer, and wherein the first portion, the second portion, and the third portion of the second semiconductor layer respectively overlie the first portion, the second portion, and the third portion of the first semiconductor layer; removing the second sacrificial layer from the substrate; a first section of a sacrificial layer to form a sealed cavity between the second semiconductor layer and the first semiconductor layer; forming a piezoelectric layer on the second semiconductor layer, the piezoelectric layer surrounding a plurality of wires; forming a plurality of contacts to couple to the plurality of wires; etching the piezoelectric layer and the second semiconductor layer to form an air gap, the air gap separating the first portion, the second portion, and the third portion of the second semiconductor layer and exposing the second sacrificial layer; etching the substrate and the first semiconductor layer from a second side of the substrate to depict one or more structures within the first portion and the third portion of the first semiconductor layer, wherein the etching stops at the first sacrificial layer and the second sacrificial layer; and etching the first sacrificial layer and the second sacrificial layer to remove portions of the first sacrificial layer and the second sacrificial layer exposed when forming the air gap and depicting the one or more structures to expand the air gap between the first portion, the second portion, and the third portion of the second semiconductor layer.

[0068] In yet other embodiments, etching the piezoelectric layer and the second semiconductor layer to form the air gap further forms an additional air gap within the first portion of the second semiconductor layer; wherein etching the substrate and the first semiconductor layer to delineate the one or more structures within the first portion of the first semiconductor layer includes etching an acoustic port directly below the additional air gap; and wherein, when etching the second sacrificial layer, the second sacrificial layer between the additional air gap and the acoustic port is removed to connect the additional air gap to the acoustic port. In yet other embodiments, forming the sealed cavity further comprises etching a plurality of trenches through the second semiconductor layer to expose the first segment of the second sacrificial layer; etching the first segment to form a cavity between the second portion of the first semiconductor layer and the second portion of the second semiconductor layer; and filling the plurality of trenches to form the sealed cavity between the second portion of the first semiconductor layer and the second portion of the second semiconductor layer. In yet other embodiments, when etching the substrate and the first semiconductor layer to delineate the one or more structures within the third portion of the first semiconductor layer, the first sacrificial layer covers a bottom surface of a proof mass delineated by the etching. In yet other embodiments, the substrate is further comprised of a package comprising a port, wherein one of the one or more structures is an acoustic port, and wherein the port is centered about an axis extending through a center of the acoustic port within the first semiconductor layer. In yet other embodiments, the one or more structures comprise an acoustic port in the first portion of the first semiconductor layer and the second semiconductor layer and a proof mass in the third portion, wherein the sealed cavity is directly between the acoustic port and the proof mass, and wherein the sealed cavity, the acoustic port, and the proof mass are separated by the air gap.

[0069] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and variations may be made to this document without departing from the spirit and scope of the present invention.

Claims

1. An integrated component comprising: substrate; a semiconductor layer disposed on the substrate and comprising a first structure that is one of an acoustic port, a sealed cavity, or a proof mass, and a second structure that is one of the acoustic port, the sealed cavity, or the proof mass, wherein the second structure is the acoustic port, the sealed cavity, or the proof mass different from the first structure; The piezoelectric layer is located on the semiconductor layer and covers the first structure and the second structure; as well as An air gap extends from the upper surface of the piezoelectric layer into the semiconductor layer, wherein the first structure and a portion of the piezoelectric layer overlying the first structure are separated from the second structure and a portion of the piezoelectric layer overlying the second structure by the air gap.

2. The integrated component according to claim 1, characterized in that Also includes: The insulating column is located within the semiconductor layer, wherein the air gap includes a first region having a first width and flush with the insulating column and a second region having a second width between the first region and the upper surface of the semiconductor layer, wherein the outer sidewall of the insulating column is exposed in the first region, and wherein the first width is greater than the second width.

3. The integrated component according to claim 1, characterized in that Also includes: A third structure is located within the semiconductor layer, wherein the third structure includes the acoustic port, the sealed cavity, or the proof mass block that is different from the first structure and the second structure, such that the acoustic port, the sealed cavity, and the proof mass block are located within the semiconductor layer.

4. The integrated component according to claim 1, characterized in that Also includes: The insulating column is located in the semiconductor layer, wherein when one of the first structure or the second structure is the sound port, one or more arms cover the sound port and are separated from the semiconductor layer by the insulating column.

5. The integrated component according to claim 4, characterized in that The one or more arms are located directly above the sound port and are separated from each other by additional air gaps.

6. The integrated component according to claim 1, characterized in that When one of the first structure or the second structure includes the sealed cavity, the piezoelectric layer has an opening extending through the piezoelectric layer and aligned with the sealed cavity.

7. An integrated component comprising: The substrate has a first portion and a second portion; a first sensor positioned on the first portion of the substrate, the first sensor having a first moving structure, the first moving structure being one of a first arm coupled to a proof mass, a cap overlying a sealed cavity, or one or more arms overlying an acoustic port extending through the substrate; a second sensor positioned on the second portion of the substrate, the second sensor having a second moving structure, the second moving structure being one of the first arm coupled to the proof mass, the cap overlying the sealed cavity, or the one or more arms overlying the acoustic port extending through the substrate, the second moving structure being different from the first moving structure; The application specific integrated circuit is configured to receive a first signal and a second signal from the first sensor and the second sensor, respectively; as well as A package surrounds the substrate and the ASIC, the package having a port connecting an interior region of the package to an ambient environment outside the package.

8. The integrated component according to claim 7, characterized in that Also includes: An air gap is located between the first moving structure and the second moving structure, the air gap including a first region having a first width directly between the first moving structure and the second moving structure and a second region having a second width below the first region, wherein the second width is greater than the first width.

9. The integrated component according to claim 7, characterized in that: Also includes: a semiconductor layer, wherein the first movable structure is flush with the second movable structure and overlies the semiconductor layer; as well as An insulating pillar couples one of the first mobile structure or the second mobile structure to the semiconductor layer.

10. The integrated component according to claim 7, characterized in that Also includes: The piezoelectric layer covers the first movable structure and the second movable structure, wherein the piezoelectric layer is configured to convert strains of the first movable structure and the second movable structure into the first signal and the second signal, respectively.

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