Intelligent acoustic emission tester

Abstract

An intelligent acoustic emission tester belongs to the field of acoustic emission detection and is characterized by comprising a data processing control unit, a precise analog signal link unit, a man-machine interaction unit and an acoustic emission sensor, cooperative processing is carried out based on the FPGA module and the ARM module, collection, processing, transmission and man-machine interaction functions of acoustic emission signals are completed, collection, parallel processing and transmission storage work of multi-channel acoustic emission signals is completed, universality and a networked remote cooperative monitoring function are considered, and the real-time performance of the system is improved. The problems that an existing acoustic emission testing device cannot complete real-time online monitoring and cannot effectively complete detection on occasions with complex environmental noise sources can be effectively solved, and the acoustic emission testing device has good engineering application value.

Description

Technical Field

[0001] The utility model belongs to the field of acoustic emission detection, in particular to an acoustic emission intelligent tester. Background Art

[0002] Currently, acoustic emission detection technology is widely used. However, due to the high frequency of acoustic emission signals, the amount of data is large, and real-time online monitoring cannot be completed in many applications. In situations where the source of environmental noise is more complex, detection cannot be effectively completed, which greatly restricts the development of acoustic emission detection technology. Summary of the Invention

[0003] The utility model aims to solve the above problems and provides an intelligent acoustic emission tester capable of real-time online monitoring.

[0004] The acoustic emission intelligent tester of the utility model comprises a data processing control unit, a precision analog signal link unit, a human-computer interaction unit and an acoustic emission sensor;

[0005] The data processing control unit includes an FPGA module and an ARM module; the FPGA module and the ARM module are electrically connected;

[0006] The precision analog signal link unit is electrically connected to the aforementioned FPGA module;

[0007] The precision analog signal link unit is provided with a plurality of signal acquisition interfaces;

[0008] The acoustic emission sensor is connected to the precision analog signal link unit via the aforementioned signal acquisition interface;

[0009] The human-computer interaction unit is electrically connected to the aforementioned ARM module. The acoustic emission sensor is used to collect acoustic emission signals generated during operation and convert them into electrical signals for output. The precision analog signal link unit uses the output signal of the acoustic emission sensor as its input signal, and after amplification and other processing, transmits the digital signal to the FPGA module to complete data collection. The FPGA module and ARM module process the collected digital signal and then display, store, and perform subsequent analysis through the human-computer interaction unit.

[0010] Furthermore, in the intelligent acoustic emission tester of the present invention, the precision analog signal link unit includes a variable gain circuit, an anti-aliasing filter, a single-ended to differential circuit, and an analog-to-digital conversion circuit electrically connected in sequence;

[0011] The analog-to-digital conversion circuit is electrically connected to the aforementioned FPGA module;

[0012] The variable gain circuit is connected to the acoustic emission sensor via a signal acquisition interface.

[0013] The precision analog signal link unit first amplifies or attenuates the signal through a variable gain circuit to facilitate processing by the subsequent circuit; secondly, it passes through an anti-aliasing filter to avoid "frequency aliasing" and eliminate the impact of frequency aliasing on valid data in the data acquisition system as much as possible; then, the single-ended signal is converted into a differential signal through a single-ended to differential circuit to enhance the signal's ability to resist common-mode interference; finally, the analog signal conditioned by the previous circuit is converted into a digital signal that can be recognized by the computer system through an analog-to-digital conversion circuit.

[0014] Furthermore, in the intelligent acoustic emission tester of the present invention, the FPGA module and the ARM module are electrically connected via Gigabit Ethernet, so that data is transmitted with extremely low latency, thereby improving the capability and efficiency of real-time online monitoring and processing.

[0015] Furthermore, in the intelligent acoustic emission tester of the present invention, the variable gain circuit is provided with two gain adjustment switches, with a gain adjustment range of 1-500 times. The variable gain circuit adjusts the amplitude of the acoustic emission sensor signal, effectively suppressing common-mode interference of ambient noise on signal transmission.

[0016] Furthermore, in the intelligent acoustic emission tester of the present invention, the anti-aliasing filter is a fourth-order low-pass filter; the anti-aliasing filter circuit includes two operational amplifiers: a first operational amplifier and a second operational amplifier; four resistor elements: R1, R2, R3, R4 and four capacitor elements: C1, C2, C3, C4;

[0017] The output pin of the first operational amplifier is connected to the non-inverting input pin of the second operational amplifier via resistors R3 and R4;

[0018] The output pin of the first operational amplifier is connected to the inverting input pin, the non-inverting input pin is connected to the output pin via a resistor R2 and a capacitor C2, and the non-inverting input pin is grounded via a capacitor C1, and an input signal VIN1 is connected to the non-inverting input pin via a resistor R1 and a resistor R2; the positive power pin is connected to a positive power supply, and the negative power pin is connected to a negative power supply;

[0019] The non-inverting input pin of the second operational amplifier is grounded via a capacitor C3, the inverting input pin is connected to the output pin, and the output pin is connected to the non-inverting input pin via a capacitor C4 and a resistor R4.

[0020] The anti-aliasing filter is used to attenuate or eliminate frequency components greater than the Nyquist sampling rate, thereby reducing the interference of high-frequency interference signals on the system.

[0021] Furthermore, in the intelligent acoustic emission tester of the present invention, the single-ended to differential circuit includes two operational amplifiers: a third operational amplifier and a fourth operational amplifier, eight resistor elements: R5, R6, R7, R8, R9, R10, R11, R12 and three capacitor elements: C5, C6, C7;

[0022] The output terminal of the third operational amplifier is connected to the output terminal of the fourth operational amplifier via the resistor R11, the capacitor C6 and the resistor R12; the output terminal of the third operational amplifier is connected to the inverting input terminal of the fourth operational amplifier via the resistor R9;

[0023] The non-inverting input pin of the third operational amplifier is connected to the input signal VAD1 via a resistor R7, the common mode voltage VCM1 is connected to the non-inverting input pin via a resistor R8, the inverting input pin is grounded via a resistor R5, and is connected to the output pin via a resistor R6, the output pin is connected to the output pin AIN1+ via a resistor R11, and the output pin AIN1+ is grounded via a capacitor C5;

[0024] The non-inverting input pin of the fourth operational amplifier is connected to the common mode voltage VCM1, the inverting input pin is connected to the output pin via a resistor R10, the output pin is connected to the output pin AIN1- via a resistor R12, and the output pin AIN1- is grounded via a capacitor C7;

[0025] The single-ended to differential circuit is used to convert a single-ended signal into a differential signal, thereby meeting the input requirements of a subsequent circuit, and can also offset interference and distortion, thereby improving signal quality.

[0026] Furthermore, in the intelligent acoustic emission tester of the present invention, the analog-to-digital conversion circuit and the FPGA are connected through four groups of LVDS communication interfaces; the four groups of LVDS communication interfaces include a conversion trigger input CNV± signal interface, a clock input CLK± signal interface, a buffered clock output DCO± signal interface, and a data serial output D± signal interface.

[0027] The intelligent acoustic emission tester of the present invention performs collaborative processing based on an FPGA module and an ARM module, completes the acquisition, processing, transmission and human-computer interaction functions of acoustic emission signals, completes the acquisition, parallel processing and transmission and storage of multi-channel acoustic emission signals, takes into account both versatility and networked remote collaborative monitoring functions, can effectively solve the problems that current acoustic emission test equipment cannot complete real-time online monitoring and cannot effectively complete detection in occasions with relatively complex environmental noise sources, and has good engineering application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic block diagram of the structure of the intelligent acoustic emission tester according to an embodiment of the present utility model;

[0029] Figure 2 This is a schematic diagram of the structure of the variable gain circuit according to an embodiment of the present utility model;

[0030] Figure 3 This is a schematic diagram of the anti-aliasing filter circuit structure according to an embodiment of the present utility model;

[0031] Figure 4 This is a schematic diagram of the single-ended to differential circuit structure according to an embodiment of the present utility model;

[0032] Figure 5 This is a schematic diagram of the analog-to-digital conversion circuit structure described in an embodiment of the present utility model. DETAILED DESCRIPTION

[0033] The intelligent acoustic emission tester of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0034] The intelligent acoustic emission tester of the utility model is as follows: Figure 1 As shown, it includes a data processing control unit, a precision analog signal link unit, a human-computer interaction unit and an acoustic emission sensor; the data processing control unit includes an FPGA module and an ARM module; the FPGA module and the ARM module are electrically connected; the precision analog signal link unit is electrically connected to the aforementioned FPGA module; the precision analog signal link unit is provided with several acquisition signal interfaces, i.e., multiple acquisition channels; the acoustic emission sensor is connected to the precision analog signal link unit through the aforementioned acquisition signal interface; the human-computer interaction unit is electrically connected to the aforementioned ARM module.

[0035] The precision analog signal link unit includes a variable gain circuit, an anti-aliasing filter, a single-ended to differential circuit and an analog-to-digital conversion circuit electrically connected in sequence; the analog-to-digital conversion circuit is electrically connected to the aforementioned FPGA module; the variable gain circuit is connected to the aforementioned acoustic emission sensor through a signal acquisition interface.

[0036] In the embodiment of the present disclosure, Figure 2 As shown in the figure, INA849 is used as the front end of the signal conditioning circuit to adjust the sensor signal amplitude. Flexible gain adjustment is performed through two switches, and the gain can be selected as 1, 10, 50, 100, and 500 times. It has the function of converting single-ended signals into differential signals, which can effectively suppress the common-mode interference of environmental noise in signal transmission.

[0037] In order to obtain better filtering characteristics and smaller delay, in the embodiment of the present disclosure, a Butterworth active filter is used to complete the design of the anti-aliasing filter, such as Figure 3As shown, the SGM8302 operational amplifier designed by Shengbang Microelectronics is used to build an anti-aliasing filter. It includes a dual op amp-operational amplifier chip (containing two independent op amps), four resistors: R1, R2, R3, and R4, and four capacitors: C1, C2, C3, and C4. Pin 1 of the operational amplifier is connected to pin 2, and pin 3 is connected to pin 1 through resistor R2 and capacitor C2. Pin 3 is grounded through capacitor C1. The input signal VIN1 is connected to pin 3 through resistor R1 and resistor R2. Pin 1 is connected to pin 5 through resistors R3 and R4. Pin 5 is grounded through capacitor C3. Pin 6 is connected to pin 7. Pin 7 is connected to pin 5 through capacitor C4 and resistor R4. Pin 8 is connected to the positive power supply, and pin 4 is connected to the negative power supply. The capacitor values of C1 and C2 are selected as 10pF and 100pF respectively, the resistor values are R1=2.8kΩ and R2=10kΩ respectively, and the resistance values of the two resistors in the second stage are R3=931Ω and R4=30.1kΩ respectively.

[0038] In the embodiment of the present disclosure, the cutoff frequency of the anti-aliasing filter is 950kHz. When the signal attenuation ratio is -3 dB, the frequency is about 950kHz, and the gain in the passband is 1; when the signal attenuation ratio is -40dB, the frequency is about 4Mhz, which is basically consistent with the theoretical design results, that is, the anti-aliasing filter design meets the requirements.

[0039] The function of the single-ended to differential circuit is to convert the single-ended signal into a differential signal, thereby meeting the input requirements of the subsequent circuit, and can also offset interference and distortion, and improve the quality of the signal. In the embodiment of the present disclosure, a dual op amp - operational amplifier CBM8656 is used to build a single-ended to differential circuit, and the domestic Xinbaiwei company is selected to build the single-ended to differential circuit. CBM8656 provides low noise, low total harmonic distortion and high precision performance for low-voltage applications. In addition, it has rail-to-rail input and output swing capabilities, and can buffer analog-to-digital converters and other wide dynamic range devices in a single power supply system. Among them, VAD is the anti-aliasing filter output voltage, VCM is the common-mode output voltage of the ADC chip, which is used to drive the single-ended to differential circuit to output the differential signal common mode. In this embodiment, VCM is 2.5V, and AIN+ and AIN- are single-ended to differential outputs. As Figure 4As shown, the single-ended to differential circuit consists of a dual operational amplifier - operational amplifier CBM8656 (including two independent operational amplifiers), 8 resistor elements: R5, R6, R7, R8, R9, R10, R11, R12, and 3 capacitor elements: C5, C6, and C7. Among them, the input VAD1 is connected to pin 3 through resistor R7, the common-mode voltage VCM1 is connected to pin 3 through resistor R8, the common-mode voltage VCM1 is connected to pin 5, pin 2 is grounded through resistor R5 and connected to pin 1 through resistor R6, pin 1 is connected to pin 6 through resistor R9, pin 6 is connected to pin 7 through resistor R10, pin 1 is output to pin AIN1+ through resistor R11, pin 7 is output to pin AIN1- through resistor R20, pin AIN1+ is grounded through capacitor C5, pin AIN1- is grounded through capacitor C7, and pin AIN1+ is connected to pin AIN1- through capacitor C6.

[0040] In the embodiment of the present disclosure, Figure 5 As shown, the analog-to-digital conversion circuit uses the ADC designed by the domestic Xinbaiwei Company: CBM79AD60G. As an ADC with serial output and 18-bit accuracy, four pairs of LVDS communication interfaces are set between CBM79AD60G and FPGA, including conversion trigger input CNV± signal, clock input CLK± signal, buffered clock output DCO± signal, and data serial output D± signal. According to the echo clock interface mode timing, this embodiment selects Verilog language to write the ADC driver module, adopts the pipeline working mode, and realizes different acquisition frequencies by controlling the CNV signal timing period T. The counter is generated based on the 100M clock, and 18 clock CLK signals are generated in each sampling period. The serial data D is shifted and registered according to the rising edge of the echo clock DCO to complete one data acquisition.

[0041] In this disclosed embodiment, the intelligent acoustic emission tester described in this embodiment is used to monitor a CNC grinding machine. The grinding wheel system is controlled to operate in the idle, grinding, and collision phases (the grinding wheel rotation is not stopped during the experiment). Real-time acoustic emission data from the grinding machine is collected and processed on the FPGA side. This data is transmitted in real time via an Ethernet interface, and the real-time data waveform and the grinding status of the grinding wheel system are displayed on the display device of the human-computer interface.

[0042] During testing, an acoustic emission sensor is placed at the location to be monitored. It collects the acoustic emission signals generated by the grinding machine system during operation and converts them into electrical signals for output. The precision analog signal link unit first amplifies or attenuates the signal using a variable gain circuit. Next, it passes through an anti-aliasing filter to minimize the impact of frequency aliasing on valid data in the data acquisition system. A single-ended-to-differential circuit then converts the single-ended signal into a differential signal, enhancing its resistance to common-mode interference. Finally, an analog-to-digital conversion circuit converts the analog signal, conditioned by the pre-stage circuit, into a digital signal recognizable by the computer system. The collected digital signals are processed by the FPGA and ARM modules, and then displayed, stored, and subsequently analyzed by the human-computer interface unit. For the specific processing process, operators can write specific execution programs based on actual needs and common knowledge, and run them on the FPGA and ARM modules to complete the data processing and analysis.

[0043] In the disclosed embodiment, after data enters the FPGA, it first undergoes adaptive filtering. In practice, factories often experience significant internal noise interference, such as power supply fluctuations and electromagnetic interference caused by the operation of large equipment. Without addressing this noise, subsequent work cannot be completed. Next, FIR bandpass filtering is performed. In actual use, the grinding wheel's linear speed must be adjusted based on the material being used. Grinding wheels with different speeds generate acoustic emission signals of varying frequencies between the grinding wheel and the workpiece. Bandpass filtering is then necessary to select the operating frequency band. The filtered signal is then evaluated (once per millisecond) for a state value. This value is then compared with a threshold to determine the grinding state. This signal is then transmitted in real time to the grinding machine system's relay, which controls the start and stop of the grinding wheel.

[0044] To facilitate real-time monitoring of multiple grinding wheel systems by remote operators, the collected raw data and status values must be uploaded. By implementing the Gigabit Ethernet UDP transport protocol on the FPGA, the data is transmitted to the remote monitoring platform with extremely low latency. Status values are updated every 1ms, and to obtain accurate time points for the remote monitoring platform, clock synchronization between the FPGA and the host computer is required.

[0045] Similarly, the ARM module can save raw data and status values to a database, allowing on-site and remote operators to browse data over a period of time. The FPGA and ARM communicate via Gigabit Ethernet. Given that data transmission between the two cores is multi-bit signal transmission in asynchronous clock domains, FIFO is used for data buffering on the FPGA side, and DMA is used on the ARM side to complete data transmission.

[0046] This embodiment applies the intelligent acoustic emission tester to the clearance elimination and collision prevention of the grinding wheel grinding machine equipment, and can be extended to complete the real-time control of the grinding wheel operation in the grinding machine system through the relay module that controls the grinding wheel. While improving the processing quality and efficiency of the grinding wheel grinding machine system, it also prevents major accidents that may occur in production and processing, reflecting good engineering application value.

Claims

1. An intelligent acoustic emission tester, characterized by: It includes a data processing control unit, a precision analog signal link unit, a human-computer interaction unit and an acoustic emission sensor; The data processing control unit includes an FPGA module and an ARM module; the FPGA module and the ARM module are electrically connected; The precision analog signal link unit is electrically connected to the aforementioned FPGA module; The precision analog signal link unit is provided with a plurality of signal acquisition interfaces; The acoustic emission sensor is connected to the precision analog signal link unit via the aforementioned signal acquisition interface; The human-computer interaction unit is electrically connected to the aforementioned ARM module.

2. The intelligent acoustic emission tester according to claim 1, characterized in that: The precision analog signal link unit includes a variable gain circuit, an anti-aliasing filter, a single-ended to differential circuit and an analog-to-digital conversion circuit electrically connected in sequence; The analog-to-digital conversion circuit is electrically connected to the aforementioned FPGA module; The variable gain circuit is connected to the acoustic emission sensor via a signal acquisition interface.

3. The intelligent acoustic emission tester according to claim 2, characterized in that: The FPGA module and the ARM module are electrically connected via Gigabit Ethernet.

4. The intelligent acoustic emission tester according to claim 3, characterized in that: The variable gain circuit is provided with two gain adjustment switches, and the gain adjustment range is 1-500 times.

5. The intelligent acoustic emission tester according to claim 4, characterized in that: The anti-aliasing filter is a fourth-order low-pass filter; the anti-aliasing filter circuit includes two operational amplifiers: a first operational amplifier and a second operational amplifier; four resistor elements: R1, R2, R3, R4 and four capacitor elements: C1, C2, C3, C4; The output pin of the first operational amplifier is connected to the non-inverting input pin of the second operational amplifier via resistors R3 and R4; The output pin of the first operational amplifier is connected to the inverting input pin, the non-inverting input pin is connected to the output pin via a resistor R2 and a capacitor C2, and the non-inverting input pin is grounded via a capacitor C1, and the input signal VIN1 is connected to the non-inverting input pin via resistors R1 and R2; the positive power pin is connected to the positive power supply, and the negative power pin is connected to the negative power supply; The non-inverting input pin of the second operational amplifier is grounded via a capacitor C3, the inverting input pin is connected to the output pin, and the output pin is connected to the non-inverting input pin via a capacitor C4 and a resistor R4.

6. The intelligent acoustic emission tester according to claim 5, characterized in that: The single-ended to differential circuit includes two operational amplifiers: a third operational amplifier and a fourth operational amplifier, eight resistor elements: R5, R6, R7, R8, R9, R10, R11, R12 and three capacitor elements: C5, C6, C7; The output terminal of the third operational amplifier is connected to the output terminal of the fourth operational amplifier via the resistor R11, the capacitor C6 and the resistor R12; the output terminal of the third operational amplifier is connected to the inverting input terminal of the fourth operational amplifier via the resistor R9; The non-inverting input pin of the third operational amplifier is connected to the input signal VAD1 via a resistor R7, the common mode voltage VCM1 is connected to the non-inverting input pin via a resistor R8, the inverting input pin is grounded via a resistor R5, and is connected to the output pin via a resistor R6, the output pin is connected to the output pin AIN1+ via a resistor R11, and the output pin AIN1+ is grounded via a capacitor C5; The non-inverting input pin of the fourth operational amplifier is connected to the common mode voltage VCM1, the inverting input pin is connected to the output pin via the resistor R10, the output pin is connected to the output pin AIN1- via the resistor R12, and the output pin AIN1- is grounded via the capacitor C7.

7. The intelligent acoustic emission tester according to claim 6, characterized in that: The analog-to-digital conversion circuit is connected to the FPGA via four groups of LVDS communication interfaces; the four groups of LVDS communication interfaces include a conversion trigger input CNV± signal interface, a clock input CLK± signal interface, a buffered clock output DCO± signal interface, and a data serial output D± signal interface.

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