ATE Loadboard power supply protection circuit

Abstract

The utility model discloses an ATE Loadboard power supply protection circuit. According to the technical scheme, the ATE Loadboard power supply protection circuit comprises a PMOS (P-channel Metal Oxide Semiconductor), an NMOS (N-channel Metal Oxide Semiconductor), a resistance-capacitance device, a diode and a specific circuit topological structure. And the PMOS / NMOS is connected with a resistance-capacitance device and a diode to form a power supply slow start circuit topology, so that an ATE Loadboard power supply protection effect is achieved. According to the utility model, the impact of transient current in the mass production FT test process is suppressed, so that the Loadboard is prevented from being impacted and burnt out by transient current energy in the placement process, the stability of long-time working in the mass production FT test environment is ensured, and mass production accidents caused by power supply problems are avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of ATE mass production testing, in particular to an ATE Loadboard power protection circuit. Background Art

[0002] Chip mass production testing is the final stage of chip quality testing. Its purpose is to ensure that the chips delivered to users have been thoroughly tested and are problem-free within the established test coverage. FT testing is a mass production test step after chip packaging. FT testing requires environments such as a loadboard, kit, and test machine. The loadboard, as the carrier of the test circuit, determines the accuracy, stability, and consistency of the test process and test results through its operational stability. The loadboard connects the test machine's power supply, test channels, relay control, and other test resources to the test circuit of the chip under test. The stability of the power supply determines whether the test circuit can function properly, making protection of the power transmission path crucial.

[0003] During the FT testing and debugging process, the Loadboard will be frequently loaded and unloaded, and since the test machine takes a long time to power on and off, engineers usually load and unload the Loadboard when the test machine is powered on. Since the connection between the Loadboard and the test machine is generally in the form of Pogo Pin and Pad, the contact resistance is unstable at the moment when the Loadboard's Pad contacts the Pogo Pin of the test machine. At the same time, if a large capacitor is mounted on the Loadboard power path, a transient current spike will be generated at the moment of contact. The larger the mounted capacitance, the greater the spike current. The energy impact causes the power supply Pad to be at risk of damage. During multiple tests, the power supply Pad will gradually burn out, causing the Loadboard test circuit to fail to power on, making it impossible to perform normal testing activities, leading to mass production accidents. This patent uses simple devices and circuit topology to achieve slow power-on and fast power-off during the Loadboard loading and unloading process. It is a low-cost, high-stability power protection circuit. Utility Model Content

[0004] In response to the shortcomings and defects of the existing technology, the utility model provides an ATE loadboard power protection circuit, which suppresses the impact of transient current during mass production FT testing, thereby preventing the loadboard from being burned by transient current energy impact during placement, ensuring the stability of the mass production FT test environment for long-term operation, and avoiding mass production accidents caused by power supply problems.

[0005] The purpose of the utility model can be achieved through the following technical solutions:

[0006] An ATE loadboard power protection circuit includes a PMOS, an NMOS, a resistor and capacitor device, and a diode.

[0007] Furthermore, the source of the PMOS Q1 is connected to the Loadboard+15V power supply Pad, the resistor R1 and the capacitor C13 through a circuit trace, the gate of the PMOS Q1 is connected to the capacitor C13, the resistor R2, the resistor R3 and the diode D1 through a circuit trace, and the drain of the PMOS Q1 is connected to the back-end power circuit through a circuit trace.

[0008] Furthermore, the resistor R1 is connected to the Loadboard+15V power supply Pad, the source of the PMOS Q1 and the resistor R2 respectively through circuit wiring.

[0009] Furthermore, the resistor R2 is connected to the resistor R1 , the resistor R3 , the capacitor C13 , the gate of the PMOS Q1 and the diode D1 respectively through circuit wiring.

[0010] Furthermore, the resistor R3 is connected to the resistor R2, the resistor R4, the capacitor C13, the gate of the PMOS Q1 and the diode D1 respectively through circuit wiring.

[0011] Furthermore, the resistor R4 is connected to the resistor R3, the diode D1 and GND respectively through circuit wiring.

[0012] Furthermore, the diode D1 is connected to the resistor R2 , the resistor R3 , the resistor R4 , the capacitor C13 , the gate of the PMOS Q1 and GND respectively through circuit wiring.

[0013] The beneficial technical effects of the present invention are as follows: it is possible to implement slow power startup during Loadboard testing and debugging through simple devices and circuit topology, and to utilize a low-cost circuit solution to stably suppress transient current energy impacts, thereby protecting the power connection pad, providing a safe and stable test circuit power resource, and enabling the power pad to remain in a healthy state during long-term testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0015] Figure 1 This is a positive power supply protection circuit of the utility model, which can realize the slow start of the positive power supply;

[0016] Figure 2 The utility model discloses a negative power supply protection circuit, which can realize the slow start of the negative power supply. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0018] See also Figure 1 In the embodiment of the present invention, the ATE Loadboard power protection circuit includes a PMOS Q1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R9, a capacitor C13, a diode D1, a positive power supply +15V and a reference ground. The circuit topology is as follows: Figure 1 exhibit.

[0019] The PMOS Q1 is a key component in the power supply slow start circuit, which is used to control the on / off of the +15V power supply Pad and the back-end power circuit (R9 simulates the back-end power circuit) and plays the role of a switch. The resistor R1, resistor R2, resistor R3, and resistor R4 form a voltage divider network to provide a suitable operating point for PMOS Q1, such as making Vgs reach the threshold voltage for the PMOS device to turn on when the power is on and not exceeding the maximum gate-source voltage difference. The capacitor C13 is a capacitive component in the circuit to ensure that the gate-source voltage of the PMOS device does not change suddenly, and forms an RC circuit structure with the resistor R3 and the resistor R4. During the power-on process, the capacitor charges slowly, causing the PMOS device to turn on slowly, realizing the power supply slow start mechanism. During the power-off process, the capacitor discharges quickly through the diode D1, avoiding the risk of being unable to suppress transient impact current when the PMOS device is not completely turned off and being put on the Loadboard again in the fast loading and unloading scenario during engineering testing. Resistors R3 and R4, along with resistors R1 and R2, form a voltage divider network to provide the operating point for PMOS Q1. They also form an RC circuit with capacitor C13 to implement a slow-start mechanism. Diode D1 provides a rapid discharge path for capacitor C13 during power-off. The +15V DC source represents the +15V power source provided by the tester, typically via a Pogo pin. Resistor R9 simulates the test board's electrical circuitry.

[0020] When the loadboard is placed, the voltage across capacitor C13 does not change suddenly when the loadboard contacts the tester, so PMOS Q1 does not turn on. After the tester power supply Pogo Pin and the loadboard power pad are connected stably, capacitor C13 is slowly charged through resistors R3 and R4 until the gate-source voltage Vgs of the PMOS device reaches the conduction threshold. The PMOS device then turns on, and the test board power circuit (simulated by R9) begins to operate.

[0021] When removing the loadboard, at the moment the loadboard is separated from the tester, capacitor C13 discharges rapidly through D1, causing the gate-source voltage Vgs of the PMOS device to quickly drop below the conduction threshold. The PMOS device is quickly turned off, avoiding instability during the separation process and multiple contacts between the tester Pogo Pin and the loadboard power pad, which may cause transient current energy shock.

[0022] like Figure 2 In this embodiment, the ATE Loadboard power protection circuit includes a PMOS Q2, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R10, a capacitor C14, a diode D2, a negative power supply -15V and a reference ground. The circuit topology is as follows: Figure 2 Its circuit topology is similar to Figure 1 symmetry, Figure 1 It is a positive power supply slow start protection circuit. Figure 2 This is the negative power supply slow-start protection circuit. Together, the two circuits form the power supply slow-start protection circuit. Because the negative power supply slow-start protection circuit and the positive power supply slow-start protection circuit are symmetrical only in circuit structure, and their components and connections are similar, we will not repeat the circuit's operating principles and functions.

[0023] The above embodiments are illustrations of specific implementation methods of the present invention, rather than limitations of the present invention. Technicians in the relevant technical fields may make various changes and modifications to obtain corresponding equivalent technical solutions without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions should be included in the patent protection scope of the present invention.

Claims

1. An ATE Loadboard power protection circuit, comprising a positive power protection circuit and a negative power protection circuit, wherein the positive power protection circuit and the negative power protection circuit are symmetrical in circuit structure, the positive power protection circuit comprising a PMOS Q1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C13, and a diode D1, characterized in that The source of the PMOS Q1 is connected to the Loadboard+15V power supply Pad, the resistor R1 and the capacitor C13 through a circuit trace, the gate of the PMOS Q1 is connected to the capacitor C13, the resistor R2, the resistor R3 and the diode D1 through a circuit trace, the drain of the PMOS Q1 is connected to the back-end power circuit through a circuit trace, the resistor R1 is respectively connected to the Loadboard+15V power supply Pad, the PMOS Q1 source and the resistor R2 through a circuit trace, the resistor R2 is respectively connected to the resistor R1, the resistor R3, the capacitor C13, the PMOS Q1 gate and the diode D1 through a circuit trace, the resistor R3 is respectively connected to the resistor R2, the resistor R4, the capacitor C13, the PMOS Q1 gate and the diode D1 through a circuit trace, the resistor R4 is respectively connected to the resistor R3, the diode D1 and GND through a circuit trace, the diode D1 is respectively connected to the resistor R2, the resistor R3, the resistor R4, the capacitor C13, the PMOS Q1 gate and the diode D1 through a circuit trace The gate of Q1 is connected to GND, and the capacitor C13 is connected to the Loadboard+15V power supply Pad, the source of PMOS Q1, the gate of PMOS Q1, the resistor R1, the resistor R2, the resistor R3 and the diode through circuit traces.

2. The ATE Loadboard power protection circuit according to claim 1, wherein: The PMOS Q1 is used to control the on / off of the +15V power supply pad and the back-end power circuit, and cooperates with other resistors and capacitors to establish working conditions and realize the circuit functions of slow startup and fast power-off of the power supply.

3. The ATE Loadboard power protection circuit according to claim 1, wherein: The resistors R1, R2, R3, and R4 form a voltage divider network to establish suitable operating conditions for the PMOS Q1 when it is turned on, so that the voltage between the gate and source of the PMOS Q1 is less than the limit operating voltage when powered on and is within a safe operating range, thereby avoiding damage to the PMOS device.

4. The ATE Loadboard power protection circuit according to claim 1, wherein: The capacitor C13 is used as a capacitive device in the circuit to ensure that the voltage between the gate and source of the PMOS device does not change suddenly, and forms an RC circuit structure with the resistors R3 and R4. During the power-on process, the capacitor is slowly charged, thereby realizing slow conduction of the PMOS device.

5. The ATE Loadboard power protection circuit according to claim 1, wherein: The resistors R3 and R4 form an operating point establishment circuit with the resistors R1 and R2 on one hand, and form an RC circuit with C13 on the other hand to achieve slow turn-on of the PMOS device.

6. The ATE Loadboard power protection circuit according to claim 1, characterized in that: The diode D1 is used as a current direction control device and does not work during the power-on process. During the power-off process, the capacitor discharge path passes through the diode D1 instead of the resistors R3 and R4, thereby realizing the function of fast shutdown of the PMOS device.

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