Amplification circuit and radio frequency transceiver chip

Abstract

The embodiment of the utility model provides an amplification circuit and a radio frequency transceiver chip, the amplification circuit comprises one stage of amplification units or multiple stages of amplification units connected in series, and each stage of amplification unit at least comprises an amplification transistor; the bias unit is connected with the grid electrode of the amplification transistor and is used for providing bias current or bias voltage; the detection unit is connected with the signal input end of the amplification circuit and used for detecting the input signal received by the amplification circuit and then outputting a detection signal, and the amplitude of the detection signal is in positive correlation with the power of the input signal; the first end of the switch is connected with the bias unit, the second end of the switch is grounded, the control end of the switch is connected with the signal output end of the detection unit, and the switch is used for controlling the bias unit to be turned on and turned off according to the detection signal.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of radio frequency circuits, and in particular to an amplifier circuit and a radio frequency transceiver chip. Background Art

[0002] To reduce the size and weight of phased array systems and improve overall performance, highly integrated systems often integrate transmit and receive channels on the same array surface, even sharing a common antenna. To meet the demands of long-distance communications or radar detection, phased array systems typically require high transmit power. However, transmitting power entering the receive channel can damage components such as amplifiers on the receiving end. Therefore, effective measures are needed to prevent transmit power leakage into the receive channel and protect receiving-end components from damage. Utility Model Content

[0003] In view of this, the embodiments of the present application hope to provide a stable and effective amplifier circuit and radio frequency transceiver chip.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present application is implemented as follows:

[0005] An embodiment of the present application provides an amplifier circuit, the amplifier circuit comprising:

[0006] One stage or multiple stages of amplifier units connected in series, each stage of the amplifier unit comprising at least one amplifier transistor;

[0007] a bias unit connected to the gate of the amplifying transistor and configured to provide a bias current or a bias voltage;

[0008] a detection unit connected to the signal input terminal of the amplifying circuit, configured to detect the input signal received by the amplifying circuit and output a detection signal, wherein the amplitude of the detection signal is positively correlated with the power of the input signal;

[0009] A switch, wherein a first end is connected to the bias unit, a second end is grounded, and a control end is connected to the signal output end of the detection unit. The switch is used to control the opening and closing of the bias unit according to the detection signal.

[0010] In some embodiments, the bias unit includes a first bias input terminal, a first capacitor, and a first resistor;

[0011] The first bias input terminal is used to provide the bias voltage and is connected to the first end of the switch;

[0012] The first bias input terminal is connected to the gate of the amplifying transistor through the first resistor;

[0013] One end of the first capacitor is connected to the gate of the amplifying transistor, and the other end is grounded.

[0014] In some embodiments, the bias unit further includes a resistor string and a signal selector;

[0015] The resistor string comprises a plurality of second resistors connected in series; one end of the resistor string is connected to a power supply terminal, and the other end is grounded;

[0016] The first input end of the signal selector is connected to the first node in the resistor string; the second input end of the signal selector is connected to the second node in the resistor string, and the voltage of the first node is different from that of the second node; the control end of the signal selector is used to receive a selection signal, and the output end serves as the first bias input end, and is connected to the gate of the amplifying transistor through the first resistor, and is used to output the voltage of the first node or the voltage of the second node as the bias voltage according to the selection signal.

[0017] In some embodiments, the bias unit includes a second bias input terminal, a bias transistor, and a third resistor;

[0018] The second bias input terminal is used to provide the bias current and is connected to the first terminal of the switch;

[0019] The gate of the bias transistor is connected to the control terminal of the amplifying unit through the third resistor, the drain is connected to the second bias input terminal, and the source is grounded.

[0020] In some embodiments, the bias unit further includes a current source, one end of which is connected to a power supply end, and the other end of which serves as the second bias input end and is connected to the drain of the bias transistor.

[0021] In some embodiments, the amplifying circuit further comprises a first DC amplifier, one end of which is connected to the signal output end of the detection unit and the other end of which is connected to the control end of the switch;

[0022] The first DC amplifier is used to amplify the detection signal and control the on and off of the bias unit according to the amplified detection signal.

[0023] In some embodiments, the amplifying circuit further includes: a limiting unit;

[0024] The signal input end of the amplitude limiting unit is connected to the control end of the amplifying unit and the signal input end of the amplifying circuit, and the control end of the amplitude limiting unit is connected to the signal output end of the detection unit;

[0025] The detection signal is also used to control the opening and closing of the limiting unit.

[0026] In some embodiments, the amplifying circuit further includes a second DC amplifier, one end of which is connected to the signal output end of the detection unit and the other end of which is connected to the control end of the limiter unit;

[0027] The second DC amplifier is used to amplify the detection signal and control the opening and closing of the limiter unit according to the amplified detection signal.

[0028] In some embodiments, the amplifying circuit further includes an input matching unit connected between the signal input terminal of the limiting unit and the control terminal of the amplifying unit;

[0029] The input matching unit includes at least one of the following passive elements: a capacitor, an inductor, and a resistor.

[0030] The input matching unit and the limiter unit are used together to match the impedance between the input signal and the control end of the amplifying unit.

[0031] In some embodiments, the detection unit includes a half detection circuit and / or a full detection circuit;

[0032] The full detection circuit is composed of two half detection circuits connected in reverse parallel.

[0033] In some embodiments, the half-detection circuit includes: a detection diode and a detection resistor connected in series, one end of the detection diode is connected to the signal input end of the amplifier circuit, and the other end is connected to the control end of the switch and the detection resistor, and the other end of the detection resistor is grounded.

[0034] The embodiment of the present application further provides a radio frequency transceiver chip, the radio frequency transceiver chip comprising a receiving channel and a transmitting channel;

[0035] The receiving channel includes the above-mentioned amplifying circuit.

[0036] The amplifier circuit provided in an embodiment of the present application comprises a detector unit at the signal input terminal of the amplifier circuit, a bias unit at the control terminal of the amplifier unit (or the gate of the amplifier transistor), and a detection voltage output by the detector unit, which is used to control the on and off of the bias unit via a switch. When the power level of the signal input terminal of the amplifier circuit is high, a low-resistance path to ground is provided by the switch, limiting the amplification function of the amplifier transistor connected to the bias unit, effectively reducing the possibility of breakdown of the amplifier transistor in the amplifier unit, and providing higher protection capabilities for the amplifier circuit and subsequent circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a schematic diagram of the structure of the amplifying transistor in an embodiment of the present application;

[0038] Figure 2 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 1 ;

[0039] Figures 3A-3C A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figures 2 to 4 ;

[0040] Figure 4 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 5 ;

[0041] Figure 5 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 6 ;

[0042] Figure 6 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 7 ;

[0043] Figure 7 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 8 ;

[0044] Figure 8 Schematic diagram 9 of an amplifier circuit provided in an embodiment of the present application;

[0045] Figures 9A-9B A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figures 10 to 11 ;

[0046] Figure 10 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 10 two;

[0047] Figure 11 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 10 three;

[0048] Figure 12 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 10 Four;

[0049] Figure 13 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 10 five;

[0050] Figure 14 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 10 six;

[0051] Figures 15A-15B A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figures 17 to 10 eight;

[0052] Figure 16 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 10 Nine;

[0053] Figure 17 A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 2 ten;

[0054] Figures 18A-18B A schematic diagram of an amplifier circuit provided in an embodiment of the present application Figure 2 November to Figure 2 twelve;

[0055] Figure 19 A schematic diagram of the structure of a radio frequency transceiver chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] The following will be combined with the embodiments of this application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0057] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0058] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0059] During wireless communication, the RF signal received by the antenna is often weak and may be affected by various interferences and noises. Therefore, it is necessary to enhance the received RF signal through an amplifier to improve the signal-to-noise ratio and receiving sensitivity of the RF signal. Specifically, the amplifier can amplify the weak RF signal received at the RF input (RFIN) end and output it to the RF output (RFOUT) end for subsequent circuits or systems to process. The amplification process is usually completed by transistors inside the amplifier. The transistor can be a metal oxide semiconductor (MOS) transistor. For example Figure 1 As shown, a gate oxide layer 104 is included between the gate 101 and the channel (between the source 102 and the drain 103) of the MOS transistor. Common failure modes of MOS transistors include gate oxide breakdown and hot carrier injection. Gate oxide breakdown refers to the formation of a current path in the gate oxide layer 104 when the transistor gate voltage (gate-source voltage or gate-drain voltage) is high, causing the oxide layer performance to degrade, which can accumulate over time and lead to gate damage. Hot carrier injection refers to the generation of hot carriers in the channel when the drain-source voltage of the MOS transistor is high, which scatters in all directions and may destroy the lattice, leading to device degradation or damage. Due to the amplification effect of the amplifier, as the input signal power increases, the signal voltage swing increases. After transistor amplification, the voltage swing is further increased. This results in the MOS transistor failing when a high-power signal is input, causing the transistor terminal voltage in the amplifier circuit to be too high, resulting in irreversible damage to the circuit.

[0060] In view of this, an embodiment of the present application provides an amplifier circuit, such as Figure 2 As shown, the amplifier circuit 200 includes:

[0061] One or more stages of amplifier units 201 connected in series, each stage of amplifier unit 201 comprising at least one amplifier transistor;

[0062] A bias unit 202 connected to the gate of the amplifying transistor and configured to provide a bias current or a bias voltage;

[0063] The detection unit 203 is connected to the signal input terminal of the amplifier circuit (i.e., the aforementioned RFIN terminal), and is used to detect the input signal received by the amplifier circuit and output a detection signal. The amplitude of the detection signal is positively correlated with the power of the input signal.

[0064] The switch SW1 has a first end connected to the bias unit 202 , a second end grounded, and a control end connected to the signal output end of the detection unit 203 . The switch SW1 is used to control the on and off of the bias unit 202 according to the detection signal.

[0065] The bias unit 202 can set an appropriate bias current or voltage for the amplifying transistor in the amplifying unit 201 , so that the amplifying transistor has a stable current or voltage in a working state.

[0066] The detection unit 203 is used to implement power detection. It can output a detection voltage to the bias unit 202 based on the power of the input signal, thereby controlling the on and off of the bias unit 202. The signal amplitude of the detection signal is positively correlated with the power of the input signal. Specifically, when the power of the input signal at the RFIN end is low, the detection unit 203 outputs a small detection voltage. When the power of the input signal at the RFIN end is high, the detection unit 203 outputs a large detection voltage. Switch SW1 controls the closure of switch SW1 based on the detection voltage, providing a low-resistance path to ground. The amplifying transistor no longer has the amplification function, and the input signal is no longer amplified by the amplifying transistor, thereby better protecting the subsequent circuit.

[0067] The amplifier circuit provided in an embodiment of the present application comprises a detector unit at the signal input terminal of the amplifier circuit, a bias unit at the control terminal of the amplifier unit (or the gate of the amplifier transistor), and a detection voltage output by the detector unit, which is used to control the on and off of the bias unit via a switch. When the power level of the signal input terminal of the amplifier circuit is high, a low-resistance path to ground is provided by the switch, limiting the amplification function of the amplifier transistor connected to the bias unit, effectively reducing the possibility of breakdown of the amplifier transistor in the amplifier unit, and providing higher protection capabilities for the amplifier circuit and subsequent circuits.

[0068] Figure 3A FIG. 1 shows a schematic diagram of an amplifier circuit in one embodiment of the present application. Figure 3A As shown, the amplifier circuit includes a first-stage amplifier unit 201. Amplifier unit 201 includes an amplifier transistor M0. The gate of amplifier transistor M0 is connected to the signal input terminal and RFIN terminal of the detector unit 203. The drain of amplifier transistor M0 is connected to the signal output terminal RFOUT of the amplifier circuit, and the source is grounded. A bias unit 202 is connected to the gate of amplifier transistor M0 to provide a stable operating point for amplifier transistor M0.

[0069] Figure 3B FIG. 1 shows a schematic diagram of an amplifier circuit in another embodiment of the present application. Figure 3BAs shown, the amplifier circuit includes a first-stage amplifier unit 201. The amplifier unit 201 includes a first amplifier transistor M1 and a second amplifier transistor M2 connected in series. A bias unit 202 is connected to the second amplifier transistor M2 to provide a stable operating point for the second amplifier transistor M2. In some other embodiments, a bias unit 202 may also be configured at the gate of the first amplifier transistor M1 to provide a stable operating point for the first amplifier transistor M1. It should be noted that the embodiments of the present application do not limit the specific number of amplifier transistors in the amplifier unit. Moreover, a bias unit may be configured at the gate of any amplifier transistor.

[0070] Figure 3C FIG. 1 shows a schematic diagram of an amplifier circuit in another embodiment of the present application. Figure 3C As shown, the amplifier circuit includes two cascaded amplifier stages. Specifically, an input signal flows in from the RFIN terminal, is amplified by the third amplifier transistor M3 and the fourth amplifier transistor M4 connected in series in the first-stage amplifier unit 201a, then flows into the second-stage amplifier unit 201b, is amplified again by the fifth amplifier transistor M5 and the sixth amplifier transistor M6 connected in series therein, and then flows out from the RFOUT terminal. The bias unit 202 includes a first bias unit 202a and a second bias unit 202b. The first bias unit 202a is connected to the gate of the fourth amplifier transistor M4. The second bias unit 202b is connected to the gate of the sixth amplifier transistor M6. The first end of the switch is connected to the first bias unit 202a and the second bias unit 202b, respectively. When the power of the input signal at the RFIN terminal is high, the detector unit 203 outputs a high detection voltage, controlling the switch SW1 to close, providing a low-impedance path to ground. The fourth amplifier transistor M4 and the sixth amplifier transistor M6 no longer have their amplification function, thereby better protecting the subsequent circuits.

[0071] In some other embodiments, a bias unit may also be configured at the gate of the third amplifying transistor M3 and / or the fifth amplifying transistor M5 to provide a stable operating point for the third amplifying transistor and / or the fifth amplifying transistor.

[0072] It should be noted that the embodiments of the present application do not limit the specific structure of the amplifier unit. The amplifier unit can change the number of amplification stages according to actual conditions, and can also change the number of amplification transistors in each stage. In essence, they all amplify the input signal at the RFIN terminal and output the amplified signal at the RFOUT terminal. In addition, the embodiments of the present application do not limit the specific type of amplification transistor. The amplification transistor can be a MOS transistor, a silicon on insulator (SOI) transistor, or a bipolar junction transistor (BJT).

[0073] In some embodiments, as Figure 4 As shown, the bias unit 202 includes a first bias input terminal Vg, a first capacitor Cp and a first resistor Rg;

[0074] The first bias input terminal Vg is used to provide a bias voltage and is connected to the first terminal of the switch SW1;

[0075] The first bias input terminal Vg is connected to the gate of the amplifying transistor through a first resistor Rg;

[0076] One end of the first capacitor Cp is connected to the gate of the amplifying transistor, and the other end is grounded.

[0077] When the power of the input signal at the RFIN terminal is high, the detection unit 203 outputs a large detection voltage, controlling the switch SW1 to close, providing a low-resistance path to ground. The second amplifier transistor M2 no longer has an amplification function, thereby better protecting the subsequent circuits. It should be noted that in some other embodiments, a bias unit may also be configured for the first amplifier transistor M1.

[0078] In some embodiments, as Figure 5 As shown, the bias unit 202 further includes a resistor string 501 and a signal selector SW2;

[0079] The resistor string 501 includes a plurality of second resistors Rp (Rp0 to Rpn) connected in series; one end of the resistor string 501 is connected to a power supply terminal (eg, a digital power supply terminal Vdig), and the other end is grounded;

[0080] The first input of signal selector SW2 is connected to first node N1 in resistor string 501; the second input of the second switch is connected to second node N2 in the resistor string. The voltages of first node N1 and second node N2 are different. The control terminal of signal selector SW2 is used to receive a selection signal EN. The output of signal selector SW2 serves as a first bias input terminal, connected to the gate of the amplifier transistor via a first resistor Rg, and is used to output the voltage of first node N1 or the voltage of second node N2 as a bias voltage based on selection signal EN. When the power of the input signal at RFIN is high, detection unit 203 outputs a high detection voltage, controlling switch SW1 to close. The output of signal selector SW2 (or the first bias input terminal) is grounded via switch SW1, and second amplifier transistor M2 no longer has an amplification function, thereby better protecting subsequent circuits.

[0081] It should be noted that, in some other embodiments, the bias unit may also be configured for the first amplifying transistor M1, and the bias unit 202 may be connected between the first end of the switch SW1 and the gate of the first amplifying transistor M1; or one bias unit may be configured for each amplifying transistor in the amplifying unit.

[0082] In some embodiments, as Figure 6 As shown, the bias unit 202 includes a second bias input terminal Ig, a bias transistor Mp and a third resistor Rb;

[0083] The second bias input terminal Ig is used to provide a bias current and is connected to the first terminal of the switch SW1;

[0084] The gate of the bias transistor Mp is connected to the control terminal of the amplifying unit through the third resistor Rb, the drain is connected to the second bias input terminal Ig, and the source is grounded.

[0085] When the power of the input signal at the RFIN terminal is high, the detection unit 203 outputs a large detection voltage, controlling the switch SW1 to close. The second bias input terminal Ig is grounded via the switch SW1, and the amplifier transistor M0 no longer has an amplification function, thereby better protecting the subsequent circuit. It should be noted that when the amplifier unit includes multiple amplifier transistors, a bias unit can be configured for each amplifier transistor, multiple amplifier transistors, or all amplifier transistors.

[0086] In some embodiments, as Figure 7 As shown, the bias unit 202 further includes a current source Ibias, one end of which is connected to the power supply terminal VDD, and the other end of which serves as a second bias input terminal Ig and is connected to the drain of the bias transistor Mp.

[0087] When the power of the input signal at the RFIN terminal is large, the detection unit 203 outputs a large detection voltage, controls the switch SW1 to be closed, and the second bias input terminal Ig is grounded through the switch SW1. The amplifying transistor M0 no longer has the amplifying function, thereby better protecting the subsequent circuit.

[0088] It should be noted that any amplifying transistor may be configured with a bias unit, and the specific implementation form of the bias unit may be any one of the above embodiments.

[0089] In some embodiments, as Figure 8 As shown, the amplifying circuit further includes a first DC amplifier A1, one end of which is connected to the signal output end of the detection unit 203, and the other end is connected to the control end of the switch SW1;

[0090] The first DC amplifier A1 is used to amplify the detection signal and control the on and off of the bias unit 202 according to the amplified detection signal.

[0091] In some embodiments, as Figures 9A-9BAs shown, the signal input terminal of the first DC amplifier A1 is connected to the signal output terminal of the detection unit 203, and the signal output terminal of the first DC amplifier A1 is connected to the first bias input terminal or the second bias input terminal via switch SW1. When the power of the input signal at the RFIN terminal is high, the detection unit 203 outputs a large detection voltage, controlling switch SW1 to close. The first bias input terminal or the second bias input terminal is grounded via switch SW1, and the amplification transistor (M0 or M2) no longer has an amplification function, thereby better protecting the subsequent circuit.

[0092] In some embodiments, as Figure 10 As shown, the amplifier circuit further includes: a limiting unit 1001;

[0093] The signal input terminal of the limiting unit 1001 is connected to the control terminal of the amplifying unit 201 and the signal input terminal RFIN of the amplifying circuit, and the control terminal of the limiting unit 1001 is connected to the signal output terminal of the detection unit 203;

[0094] The detection signal is also used to control the opening and closing of the limiting unit 1001.

[0095] In a specific embodiment, Figure 11 As shown, the limiting unit 1001 includes a first limiting transistor M7 and a second limiting transistor M8 connected in series. The gate of the first limiting transistor M7 is connected to the signal output terminal of the detection unit 203 via a first limiting resistor R1. The drain, serving as the signal input terminal of the limiting unit 1001, is connected to the gate of the amplifying transistor M0. The source is connected to the drain of the second limiting transistor M8. The gate of the second limiting transistor M8 is connected to the signal output terminal of the detection unit 203 via a second limiting resistor R2, and the source is grounded. When a low-power signal is input, the detection voltage is low, and the first limiting transistor M7 and the second limiting transistor M8 are turned off. When a high-power signal is input, the detection voltage increases, turning on the first limiting transistor M7 and the second limiting transistor M8, forming a low-impedance RF path to ground. The high-power signal is released from the limiting transistor to ground, reducing the power reaching the gate of the amplifying transistor, thereby reducing the voltage swing at the amplifying transistor terminal and achieving a protective function.

[0096] It should be noted that the signal input terminal of the limiter unit can be directly connected to the control terminal of the amplifier unit, or the input terminal of the limiter unit can be connected to the control terminal of the amplifier unit through other electronic components. However, the RF signal received by the signal input terminal enters the control terminal of the amplifier unit through the signal input terminal of the limiter unit and is amplified by the amplifier transistor.

[0097] In addition, for an amplifier circuit including multiple stages of amplifier units, although the detection unit and the limiter unit can limit the amplitude of the input signal power, after the limiter unit is turned on, a certain power signal will still enter the receiving channel. This part of the power may still damage the subsequent stage components after being amplified by the first stage amplifier unit. Multiple stages of limiters can be set in the amplifier circuit, and a limiter unit can be configured for each of the first stage amplifier unit and the second stage amplifier unit. In this way, even if the first stage limiter unit fails to completely limit the power, the subsequent stage limiter units can continue to play a role, further improving the reliability of protecting the subsequent stage components. It should be noted that it is necessary to reasonably control the gain effect of the first stage amplifier unit to avoid excessive gain resulting in excessive power output when a low power signal is input. Therefore, the embodiments of the present application do not limit the specific number and specific location of the limiter units, and any stage amplifier unit can be configured with a limiter unit. In addition, the embodiments of the present application do not limit the specific number of limiter transistors in each limiter unit.

[0098] In some embodiments, as Figure 12 As shown, the amplifying circuit further includes a second DC amplifier A2, one end of which is connected to the signal output end of the detection unit 203, and the other end is connected to the control end of the limiter unit 1501;

[0099] The second DC amplifier A2 is used to amplify the detection signal and control the opening and closing of the limiter unit 1001 according to the amplified detection signal.

[0100] For the detection unit 203, the detection voltage output by it is positively correlated with the input signal power. It is possible that due to the low detection voltage, the limiting transistor in the limiting unit 1001 cannot be fully turned on, but the power of the amplifying transistor has already exceeded the reliability range. A second DC amplifier A2 can be added to the output end of the detection unit 203 to amplify the lower detection voltage, thereby controlling the limiting unit 1001 to turn on in advance. Specifically, the signal output end of the detection unit 203 is connected to the control end of the switch SW1 and the signal input end of the second DC amplifier A2. The signal output end of the second DC amplifier A2 is respectively connected to the control end of the first-stage limiting unit and the second-stage limiting unit, and is used to amplify the detection signal and control the opening and closing of the two limiting units based on the amplified detection signal. In some other embodiments, a second DC amplifier can be used to connect the signal output end of the detection unit and the control end of some limiting units.

[0101] In some embodiments, as Figure 13As shown, the amplifier circuit includes both the first DC amplifier A1 and the second DC amplifier A2. The signal input of the first DC amplifier A1 is connected to the signal output of the detection unit, and the signal output is connected to the control end of the switch SW1, for controlling the on and off of the switch SW1 according to the amplified detection voltage. The signal input of the second DC amplifier A2 is connected to the signal output of the detection unit 203, and the signal output is connected to the control end of the limiter unit 1001, for controlling the on and off of the limiter transistor within the limiter unit 1001 according to the amplified detection voltage. It is understood that the first DC amplifier and the second DC amplifier in this embodiment can be implemented by the same DC amplifier, the signal output of which is connected to the control end of the switch SW1 and the control end of the limiter unit 1001, respectively, for controlling the on and off of the switch SW1 and the limiter unit according to the amplified detection voltage.

[0102] In some embodiments, as Figure 14 As shown, the amplifier circuit further includes an input matching unit 1401 connected between the signal input terminal of the limiter unit 1001 and the control terminal of the amplifier unit 201;

[0103] The input matching unit includes at least one of the following passive components: a capacitor, an inductor, a resistor,

[0104] The input matching unit 1401 and the limiter unit 1001 are used together to match the impedance between the input signal and the control terminal of the amplifying unit.

[0105] The input matching unit 1404 can adjust the impedance of the input signal to match the input impedance of the amplifying unit 201, thereby reducing reflection and loss of the input signal during transmission and improving the efficiency of signal transmission.

[0106] In a specific embodiment, if Figure 15A As shown, input matching unit 1401 includes an inductor L1, a first matching capacitor C1, and a second matching capacitor C2. Inductor L1 is connected in series between the first matching capacitor C1 and the second matching capacitor C2, forming a π-shaped input matching unit. By adjusting the capacitance and inductance values, the impedance seen from the signal input terminal can be made equal to the input impedance of the amplifier unit, thereby achieving impedance matching. This allows the signal from the signal input terminal RFIN to be transmitted to the amplifier unit without reflection, thereby improving overall system performance.

[0107] Although the limiting unit can limit the signal power entering the receiving channel to prevent it from exceeding the processing capacity of the amplifying unit in the receiving channel, thereby protecting devices such as the amplifying transistor. However, the limiting unit itself will generate a certain amount of insertion loss during operation, which will cause the overall gain of the amplifying circuit to decrease. In addition, the limiting unit itself will also introduce a certain amount of noise, which may also increase the noise level of the amplifying circuit. Considering that when a low-power signal is input, the first limiting transistor M7 and the second limiting transistor M8 are turned off, which can be equivalent to a capacitor to the ground, the limiting unit 1001 can also be used to match the impedance between the input signal and the control end of the amplifying unit 201. Exemplarily, the equivalent capacitance of the limiting unit 1001 when receiving a low-power signal is used as part of the input matching unit, which can reduce the need to set the first matching capacitor C1 and / or the second matching capacitor C2 ( Figure 15B Taking the reduction of the first matching capacitor C1 as an example, this embodiment of the present application integrates the limiter unit with the input matching unit, using the equivalent capacitance of the limiter unit when receiving low-power signals as part of the input matching unit, thereby reducing the number of matching electronic components and reducing additional losses. Of course, a passive matching circuit can also be provided within the limiter unit. When the limiter transistor is turned off, the limiter unit and the input matching unit are combined to reduce input losses.

[0108] Similarly, in some embodiments, the signal output terminal of the amplifying unit (eg Figure 16 An output matching unit 1601 is provided between the drain of the sixth amplifying transistor M6 in the input transistor M1 and the RFOUT terminal, and / or an inter-stage matching unit 1602 is provided between the multi-stage amplifying units. It should be noted that the embodiments of the present application do not limit the specific structure of the passive matching units such as the input matching unit and the output matching unit.

[0109] In some embodiments, as Figure 17 As shown, a third capacitor Cin is further provided between the signal input terminal RFIN and the input matching unit 1401, and a fourth capacitor Cinter is further provided between the inter-stage matching unit and the control terminal of the next-stage amplification unit. A fifth capacitor Cout is further provided between the output matching unit 1601 and the signal output terminal RFOUT. The third capacitor Cin, the fourth capacitor Cinter, and the fifth capacitor Cout can prevent DC signals in the previous and subsequent stages from adversely affecting the circuit, thereby improving the circuit's stability.

[0110] In some embodiments, the detection unit includes a half detection circuit. Figure 18A As shown, the half-detection circuit includes: a detection diode D1 and a detection resistor R6 connected in series, one end of the detection diode D1 is connected to the signal input terminal RFIN of the amplifier circuit, and the other end is connected to the control end of the limiter unit 1001, the control end of the switch SW1 and the detection resistor, and the other end of the detection resistor is grounded.

[0111] Specifically, the anode of the detector diode D1 is connected to the RFIN terminal, and the cathode is grounded through the detection resistor R6. The cathode of the detector diode D1 serves as the signal output terminal of the detection unit 203, outputting the detection voltage after half-wave detection of the high-power signal to the limiter unit 1001 and the switch SW1.

[0112] In some embodiments, the detection unit includes a full detection circuit; wherein the full detection circuit is composed of two half detection circuits connected in reverse parallel. Figure 18B As shown, the detection unit 203 includes a first detection diode D2 and a second detection diode D3 connected in antiparallel. The anode of the first detection diode D2 is connected to the cathode of the second detection diode D3 and is also connected to the RFIN terminal via a sixth capacitor C6. A seventh resistor R7 has one end connected to the cathode of the first detection diode D2 and the other end grounded. An eighth resistor R8 has one end connected to the anode of the second detection diode D3 and the other end grounded. The cathode of the first detection diode D2 serves as the signal output terminal of the detection unit 203, outputting a detection voltage after full-wave detection of the high-power signal to the limiter unit 1001 and switch SW1.

[0113] The amplifier circuit provided in an embodiment of the present application comprises a detector unit at the signal input terminal of the amplifier circuit, a bias unit at the control terminal of the amplifier unit (or the gate of the amplifier transistor), and a detection voltage output by the detector unit, which is used to control the on and off of the bias unit via a switch. When the power level of the signal input terminal of the amplifier circuit is high, a low-resistance path to ground is provided by the switch, limiting the amplification function of the amplifier transistor connected to the bias unit, effectively reducing the possibility of breakdown of the amplifier transistor in the amplifier unit, and providing higher protection capabilities for the amplifier circuit and subsequent circuits.

[0114] The present application also provides a radio frequency transceiver chip. Figure 19 As shown, the RF transceiver chip 300 includes a receiving channel 1901 and a transmitting channel 1902;

[0115] The receiving channel 1901 includes the aforementioned amplifying circuit 200 .

[0116] Since the radio frequency transceiver chip includes the above-mentioned amplifier circuit, it has similar beneficial effects as the amplifier circuit, which will not be described in detail here.

[0117] The various embodiments / implementations provided in this application can be combined with each other without causing any contradiction.

[0118] The foregoing description is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. An amplifier circuit, characterized in that: include: One stage or multiple stages of amplifier units connected in series, each stage of the amplifier unit comprising at least one amplifier transistor; a bias unit connected to the gate of the amplifying transistor and configured to provide a bias current or a bias voltage; a detection unit connected to the signal input terminal of the amplifying circuit, configured to detect the input signal received by the amplifying circuit and output a detection signal, wherein the amplitude of the detection signal is positively correlated with the power of the input signal; A switch, wherein a first end is connected to the bias unit, a second end is grounded, and a control end is connected to the signal output end of the detection unit. The switch is used to control the opening and closing of the bias unit according to the detection signal.

2. The amplifier circuit according to claim 1, wherein: The bias unit includes a first bias input terminal, a first capacitor and a first resistor; The first bias input terminal is used to provide the bias voltage and is connected to the first end of the switch; The first bias input terminal is connected to the gate of the amplifying transistor through the first resistor; One end of the first capacitor is connected to the gate of the amplifying transistor, and the other end is grounded.

3. The amplifier circuit according to claim 2, wherein: The bias unit further includes a resistor string and a signal selector; The resistor string includes a plurality of second resistors connected in series; one end of the resistor string is connected to the power supply terminal, and the other end is grounded; The first input terminal of the signal selector is connected to the first node in the resistor string; the second input terminal of the signal selector is connected to the second node in the resistor string, and the voltage of the first node is different from that of the second node; The control end of the signal selector is used to receive a selection signal, and the output end serves as the first bias input end, is connected to the gate of the amplifying transistor through the first resistor, and is used to output the voltage of the first node or the voltage of the second node as the bias voltage according to the selection signal.

4. The amplifier circuit according to claim 1, wherein: The bias unit includes a second bias input terminal, a bias transistor and a third resistor; The second bias input terminal is used to provide the bias current and is connected to the first terminal of the switch; The gate of the bias transistor is connected to the control terminal of the amplifying unit through the third resistor, the drain is connected to the second bias input terminal, and the source is grounded.

5. The amplifier circuit according to claim 4, characterized in that: The bias unit further includes a current source, one end of which is connected to the power supply end, and the other end of which serves as the second bias input end and is connected to the drain of the bias transistor.

6. The amplifier circuit according to claim 1, wherein: The amplifying circuit further comprises a first DC amplifier, one end of which is connected to the signal output end of the detection unit and the other end is connected to the control end of the switch; The first DC amplifier is used to amplify the detection signal and control the on and off of the bias unit according to the amplified detection signal.

7. The amplifier circuit according to claim 1, wherein: The amplifying circuit further includes: a limiting unit; The signal input end of the amplitude limiting unit is connected to the control end of the amplifying unit and the signal input end of the amplifying circuit, and the control end of the amplitude limiting unit is connected to the signal output end of the detection unit; The detection signal is also used to control the opening and closing of the limiting unit.

8. The amplifier circuit according to claim 7, wherein: The amplifying circuit further comprises a second DC amplifier, one end of which is connected to the signal output end of the detection unit and the other end is connected to the control end of the limiter unit; The second DC amplifier is used to amplify the detection signal and control the opening and closing of the limiter unit according to the amplified detection signal.

9. The amplifier circuit according to claim 7, wherein: The amplifying circuit further includes an input matching unit connected between the signal input terminal of the limiting unit and the control terminal of the amplifying unit; The input matching unit includes at least one of the following passive elements: a capacitor, an inductor, and a resistor. The input matching unit and the limiter unit are used together to match the impedance between the input signal and the control end of the amplifying unit.

10. A radio frequency transceiver chip, characterized in that: The radio frequency transceiver chip includes a receiving channel and a transmitting channel; The receiving channel includes the amplifier circuit according to any one of claims 1 to 9.

Images