Trench-type SiC field effect transistor

Abstract

The utility model relates to a trench-type SiC field effect transistor. Relates to the technical field of semiconductors. Comprising a SiC Sub layer, a SiC Drift layer, a P region, an NP region, an ohmic contact alloy layer and a front electrode metal layer which are sequentially arranged from bottom to top. The SiC Drift layer is provided with: an N region, which is located in the middle of the SiC Drift layer and extends downwards from the top surface of the SiC Drift layer; the Pwell region extends downwards from the top surface of the SiC Drift layer and is connected with the N region; the bottom surface of the Pwell region is not higher than the bottom surface of the N region; the PP region extends downwards into the N region from the top surface of the NP region; the section of the gate oxide layer is of a U-shaped structure, and the gate oxide layer extends downwards into the SiC Drift layer from the top surface of the NP region; the Poly layer is filled in the gate oxide layer; and the top surface of the NP region is provided with an isolation dielectric layer covering the top surfaces of the gate oxide layer and the Poly layer. According to the utility model, the channel width of the through-flow path is increased, the through-flow capability of the SiC MOSFET device is improved, and the saturation current is also improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a trench SiC field effect transistor. Background Art

[0002] In power electronics, voltage-controlled switching devices are highly sought after due to their lower losses. From low- and medium-voltage Si MOSFETs to medium- and high-voltage Si IGBTs, their use covers a wide range of switching frequencies, system voltages, and power levels, and they are found in all walks of life. However, with the continuous development of society, the field of power electronics is also moving towards higher power and higher efficiency technologies. These increasingly demanding operating conditions place even more stringent requirements on power switching devices. Si MOSFETs and Si IGBTs have a long history of development. As traditional power switching devices, they are nearing their theoretical performance limits due to the inherent physical properties of Si materials. Therefore, researchers are beginning to investigate newer materials to create more advantageous devices.

[0003] As a typical representative of the third-generation wide bandgap semiconductor materials, SiC has a large bandgap width, high critical breakdown electric field, low intrinsic carrier concentration, fast saturation drift velocity, high melting point, and high thermal conductivity. These many physical performance advantages make SiC-based power devices have great application prospects in high-voltage, high-temperature, and high-frequency electronic applications, among which SiC MOSFET is the main product.

[0004] While SiC MOSFET devices offer numerous advantages over Si MOSFETs and Si IGBTs, they also present challenges. In SiC MOSFET fabrication, the gate oxide layer is typically grown directly via thermal oxidation. Consequently, the presence of carbon in the SiC element can lead to increased interface defects during gate oxide growth, resulting in poor quality. This impacts not only product reliability but also reduces the device's channel electron mobility, inhibiting its current flow capability. Therefore, a gate voltage of 18V or higher is generally recommended for SiC MOSFETs. Furthermore, the channel region of MOSFET devices has a saturation current limit. Once a MOSFET enters the saturation region, the current struggles to increase with voltage, which also inhibits the device's current flow capability. Therefore, improving the current flow capability of SiC MOSFET devices, such as the saturation current capability, is crucial for enhancing device performance. Utility Model Content

[0005] The utility model designs an N region next to a vertical channel region in a trench gate SiC MOSFET device. When the device gate is turned on to form a channel, the adjacent N region is affected by the external gate voltage, and the hole carriers inside enter the Pwell region to accelerate the formation of the channel. The width of the channel as a current path is also increased, thereby improving the current flow capability of the SiCMOSFET device, such as the saturation current.

[0006] The technical solution of the utility model is:

[0007] A trench SiC field-effect transistor includes a SiC sublayer, a SiC drift layer, a P region, an NP region, an ohmic contact alloy layer, and a front electrode metal layer arranged in sequence from bottom to top;

[0008] The SiC Drift layer is provided with:

[0009] An N region is located in the middle of the SiC Drift layer and extends downward from the top surface of the SiC Drift layer;

[0010] A Pwell region extends downward from the top surface of the SiC Drift layer and is connected to the N region; a bottom surface of the Pwell region is not higher than a bottom surface of the N region;

[0011] A PP region extending downward from the top surface of the NP region into the N region;

[0012] A gate oxide layer having a U-shaped cross section extending downward from the top surface of the NP region into the SiC Drift layer;

[0013] A Poly layer filled in the gate oxide layer;

[0014] The top surface of the NP region is provided with an isolation dielectric layer covering the top surfaces of the gate oxide layer and the Poly layer.

[0015] The bottom of the front electrode metal layer is connected to the ohmic contact alloy layer and the isolation dielectric layer respectively.

[0016] Specifically, the PP region is located in the N region and is spaced apart from a side of the N region.

[0017] Specifically, the thickness of the SiC Sub layer is 100um-450um.

[0018] Specifically, the SiC Drift layer has a thickness of 5 μm to 20 μm.

[0019] Specifically, the thickness of the P region is 0.5um-2um.

[0020] Beneficial effects of the utility model:

[0021] In SiC MOSFETs, the presence of carbon during thermal oxidation growth of the gate oxide layer creates numerous interface state defects in the gate oxide layer, resulting in poor material quality, reliability risks, and low device channel electron mobility. Therefore, the external gate voltage must be above 18V to achieve optimal device performance. In this trench-gate SiC MOSFET device, the present invention designs an N region within the Pwell region that forms the channel. When the external gate is opened and voltage is applied, the N region is affected by the external gate voltage, attracting hole carriers to accelerate channel formation. The width of the channel, which serves as the current path, is also increased, thereby improving the SiC MOSFET device's current capacity and saturation current. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic structural diagram of the trench gate SiC MOSFET of the utility model;

[0023] Figure 2 It is a structural diagram of step S100 of the present utility model;

[0024] Figure 3 It is a structural diagram of step S200 of the present utility model;

[0025] Figure 4 It is a structural diagram of step S300 of the present utility model;

[0026] Figure 5 It is a structural diagram of step S400 of the present utility model;

[0027] Figure 6 It is a structural diagram of step S500 of the present utility model;

[0028] Figure 7 It is a structural diagram of step S600 of the present utility model;

[0029] Figure 8 It is a structural diagram of step S800 of the present utility model;

[0030] Figure 9 It is a structural diagram of step S900 of the present utility model;

[0031] Figure 10 It is a structural diagram of step S1000 of the present utility model;

[0032] Figure 11 It is a structural diagram of step S1100 of the present utility model;

[0033] Figure 12 It is a structural diagram of step S1200 of the present utility model;

[0034] Figure 13 It is a structural diagram of step S1300 of the present utility model;

[0035] In the figure, 1 is the SiC Sub layer, 2 is the SiCDrift layer, 3 is the N region, 4 is the Pwell region, 5 is the P region, 6 is the NP region, 7 is the PP region, 8 is the gate oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the ohmic contact alloy layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0036] The present invention will be described in detail below with reference to specific practical cases. Examples of the embodiments are shown in the accompanying drawings. The schematic implementations of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0037] In the description of this utility model, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this utility model. They do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting this utility model. In the description of this utility model, unless otherwise specified, "plurality" means two or more.

[0038] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on the specific circumstances.

[0039] A trench SiC field effect transistor comprises the following steps:

[0040] S100, forming a SiC Drift layer 2 on the top surface of the SiC Sub layer 1 by epitaxial deposition;

[0041] The thickness of the SiC Sub layer 1 in step S100 is 100um-450um, and the doping concentration is 1E19cm -2 , SiC Drift layer 2 thickness is 5um-20um, and doping concentration is 1E15-3E16cm -2 .

[0042] S200 , forming N regions 3 arranged at intervals on the top surface of the SiC Drift layer 2 by N ion implantation;

[0043] The bottom depth of the N region 3 in step S200 is 0.2um-1.6um, and the doping concentration is 1E17-5E18cm -2 .

[0044] S300 , forming a Pwell region 4 on the top surface of the SiC Drift layer 2 by Al ion implantation;

[0045] The bottom depth of the Pwell region 4 in step S300 is 0.5um-2um, and the doping concentration is 1E17-3E18cm -2 .

[0046] S400 , forming a P region 5 on the top surface of the SiC Drift layer 2 by epitaxial deposition;

[0047] The thickness of the P region 5 in step S400 is 0.5um-2um, and the doping concentration is 1E17-3E18cm -2 .

[0048] S500 , forming an NP region 6 on the top surface of the P region 5 by N ion implantation;

[0049] The bottom depth of the NP region 6 in step S500 is 0.2um-1.4um, and the doping concentration is 5E17-1E19cm -2 .

[0050] S600, forming a PP region 7 on the top surface of the NP region 6 by Al ion implantation;

[0051] In step S600, the bottom surface depth of the PP region 7 is 0.8um-4um, that is, it coincides with the bottom surface of the N region 3, and the doping concentration is 1E18-1E19cm -2 .

[0052] S700, activating the implanted region by high temperature ion annealing;

[0053] The high temperature ion annealing conditions in step S700 are a temperature of 1600° C. to 1900° C. and a time of 3 to 5 minutes.

[0054] S800, forming a plurality of spaced trenches on the top surface of the NP region 6 by etching downward;

[0055] In step S800 , the depth between the bottom of the trench and the bottom surface of the Pwell region 4 is 0.2 μm-1 μm, that is, the bottom surface of the trench is lower than the bottom surface of the Pwell region 4 .

[0056] S900, forming a gate oxide layer 8 in the trench by dry oxygen oxidation;

[0057] The thickness of the gate oxide layer 8 in step S900 is 40 nm to 100 nm.

[0058] S1000, forming a Poly layer 9 inside the trench by polysilicon deposition;

[0059] S1100 , forming an isolation dielectric layer 10 on top of the NP region 6 and the Poly layer 9 by oxide deposition;

[0060] S1200, forming an ohmic contact alloy layer 11 on the top surfaces of the NP region 6 and the PP region 7 by Ni metal sputtering or deposition followed by rapid thermal annealing;

[0061] The thickness of the Ni metal in step S1200 is 0.3um-1um.

[0062] S1300, forming a front electrode metal layer 12 on the top of the device by sputtering Ti and AlCu metals;

[0063] In step S1300 , the thickness of the Ti metal is 0.1 um to 0.6 um, and the thickness of the AlCu metal is 2 um to 5 um.

[0064] A trench SiC field-effect transistor comprises a SiC sub-layer 1, a SiCDrift layer 2, a P region 5, an NP region 6, an ohmic contact alloy layer 11, and a front electrode metal layer 12, which are arranged in sequence from bottom to top;

[0065] The SiC Drift layer 2 is provided with:

[0066] An N region 3 is located in the middle of the SiC Drift layer 2 and extends downward from the top surface of the SiC Drift layer 2;

[0067] A Pwell region 4 extends downward from the top surface of the SiC Drift layer 2 and is connected to the N region 3 ; a bottom surface of the Pwell region 4 is not higher than a bottom surface of the N region 3 ;

[0068] The PP region 7 extends downward from the top surface of the NP region 6 into the N region 3; the bottom surface of the PP region 7 and the bottom surface of the N region 3 are in the same plane;

[0069] The gate oxide layer 8 has a U-shaped cross section and extends downward from the top surface of the NP region 6 into the SiC Drift layer 2;

[0070] A Poly layer 9 is filled in the gate oxide layer 8, and its top surface is flush with the top surface of the gate oxide layer 8;

[0071] An isolation dielectric layer 10 covering the top surfaces of the gate oxide layer 8 and the Poly layer 9 is provided on the top surface of the NP region 6 , and a side portion of the isolation dielectric layer 10 is connected to the ohmic contact alloy layer 11 .

[0072] The bottom of the front electrode metal layer 12 is connected to the ohmic contact alloy layer 11 and the isolation dielectric layer 10 respectively.

[0073] The PP region 7 is located in the N region 3 and is spaced apart from the side of the N region 3 .

[0074] There is a gap between the side of the N region 3 and the gate oxide layer 8 .

[0075] The utility model is as follows Figure 1 The channel region position of the trench gate SiC MOSFET device shown is designed by designing an N region 3 next to the channel region Pwell. When the device gate is turned on to form a channel, the adjacent N region 3 is affected by the external gate voltage, and the internal hole carriers will enter the Pwell region 4 of the channel region, thereby accelerating the formation of the channel. The channel width serving as the current path is also increased, thereby improving the current flow capability of the SiC MOSFET device, such as the saturation current.

Claims

1. A trench SiC field-effect transistor, characterized in that: It includes a SiC sub layer (1), a SiCDrift layer (2), a P region (5), an NP region (6), an ohmic contact alloy layer (11), and a front electrode metal layer (12) arranged in sequence from bottom to top; The SiC Drift layer (2) is provided with: An N region (3) is located in the middle of the SiC Drift layer (2) and extends downward from the top surface of the SiC Drift layer (2); A Pwell region (4) extends downward from the top surface of the SiC Drift layer (2) and is connected to the N region (3); a bottom surface of the Pwell region (4) is not higher than a bottom surface of the N region (3); A PP region (7) extending downward from the top surface of the NP region (6) into the N region (3); A gate oxide layer (8) having a U-shaped cross-section, extending downward from the top surface of the NP region (6) into the SiC Drift layer (2); A Poly layer (9) filled in the gate oxide layer (8); The top surface of the NP region (6) is provided with an isolation dielectric layer (10) covering the top surfaces of the gate oxide layer (8) and the Poly layer (9); The bottom of the front electrode metal layer (12) is respectively connected to the ohmic contact alloy layer (11) and the isolation dielectric layer (10).

2. The trench SiC field effect transistor according to claim 1, wherein: The PP region (7) is located in the N region (3) and is spaced apart from the side of the N region (3).

3. The trench SiC field effect transistor according to claim 1, wherein: The SiC Sub layer (1) has a thickness of 100 μm to 450 μm.

4. The trench SiC field effect transistor according to claim 1, wherein: The SiC Drift layer (2) has a thickness of 5um-20um.

5. The trench SiC field effect transistor according to claim 1, wherein: The thickness of the P region (5) is 0.5um-2um.

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