Multi-path staggered heat dissipation structure for chip packaging

Abstract

The utility model belongs to the technical field of chip packaging heat dissipation, and discloses a multi-path staggered heat dissipation structure for chip packaging, which comprises a chip packaging body with a multi-layer structure, a plurality of layers of bare chips are arranged in the chip packaging body, the plurality of layers of bare chips are staggered and overlapped, active heat dissipation assemblies are arranged in non-overlapping areas of two adjacent layers of bare chips, and the active heat dissipation assemblies are arranged in the non-overlapping areas of the two adjacent layers of bare chips. The heat absorption end of the active heat dissipation assembly is in contact with the bare chip, and the active heat dissipation assembly is used for generating a cold source at the heat absorption end and generating a heat source at the heat release end through energy supply of an external power supply. The packaging structure has the advantages of small packaging area, high bare chip heat dissipation efficiency and the like.

Description

Technical Field

[0001] The utility model belongs to the technical field of chip packaging heat dissipation, and in particular relates to a multi-path staggered heat dissipation structure for chip packaging. Background Art

[0002] Chip packaging is a key step in the semiconductor manufacturing process that involves placing the bare die (i.e., the unpackaged integrated circuit chip) into a protective housing and providing electrical connections so that the chip can be connected to other electronic components or circuit boards.

[0003] During the die packaging process, multiple die are packaged in the same housing. Parallel packaging is commonly used, and the chip packaging area is relatively large. Furthermore, materials with high thermal conductivity, such as copper, aluminum, or thermally conductive plastics, are often used in the prior art to manufacture the package. Heat is conducted through the thermally conductive material to dissipate heat from the die, allowing the chip to operate within a safe and optimal operating temperature range.

[0004] However, heat dissipation by heat diffusion is easily affected by the external ambient temperature, resulting in low heat dissipation efficiency. Utility Model Content

[0005] The purpose of the utility model is to provide a multi-path staggered heat dissipation structure for chip packaging, so as to solve the problems of large packaging area and low heat dissipation efficiency in the existing packaging structure.

[0006] In order to achieve the above-mentioned objectives, the present invention adopts the following technical solutions: a multi-path staggered heat dissipation structure of a chip package, comprising a multi-layer chip package body, wherein multiple layers of bare chips are arranged in the chip package body, and the multiple layers of bare chips are staggered and overlapped, and an active heat dissipation component is arranged in the non-overlapping area of two adjacent layers of bare chips, wherein the heat absorption end of the active heat dissipation component contacts the bare chips, and the active heat dissipation component is used to generate a cold source at the heat absorption end and a heat source at the heat release end by being energized by an external power supply.

[0007] Preferably, the chip package comprises two layers of substrates, and the multi-layer die is disposed between the two layers of the substrates.

[0008] Preferably, the multi-layer die has two layers, the die in the lower layer and the substrate in the upper layer form a first non-overlapping area, and the die in the upper layer and the substrate in the lower layer form a second non-overlapping area.

[0009] Preferably, a plurality of second solder pads are provided on the outer sides of the two layers of the substrate, and the outer sides of the substrate are used to be electrically connected to an external circuit board through the second solder pads.

[0010] Preferably, the external circuit board includes: a PCB board and electrical components soldered on the PCB board.

[0011] Preferably, the active heat dissipation components in the two non-overlapping areas include: an N-type couple and a P-type couple, one end of the N-type couple and one end of the P-type couple are electrically connected through a metal conductor, and the metal conductor serves as the heat absorption end of the active heat dissipation component, the other end of the N-type couple and the other end of the P-type couple are both connected to the substrate of the chip package, and the other end of the N-type couple and the other end of the P-type couple serve as the heat release end of the active heat dissipation component, and two first soldering pads are provided on the outside of the chip package, one of the first soldering pads is electrically connected to the other end of the N-type couple, and the other first soldering pad is electrically connected to the other end of the P-type couple, and the two first soldering pads are used to connect to an external power supply.

[0012] Preferably, a metal body is provided on the outside of the substrate of the chip package, the metal body is connected to the first pad connected to the other end of the N-type couple, and the metal body is electrically connected to the power output end of the external power supply.

[0013] Preferably, the metal conductor and the metal body are both made of copper.

[0014] Preferably, the N-type galvanic couple includes: an N-type TE layer, a first welding layer, a first copper pillar and a second welding layer, one side of the N-type TE layer is connected to the metal conductor, the other side of the N-type TE layer is connected to one side of the first welding layer, the other side of the first welding layer is connected to one end of the first copper pillar, the other end of the first copper pillar is connected to one side of the second welding layer, and the other side of the second welding layer is connected to the chip package.

[0015] Preferably, the P-type galvanic couple includes: a P-type TE layer, a third welding layer, a second copper pillar and a fourth welding layer, one side of the P-type TE layer is connected to the metal conductor, the other side of the P-type TE layer is connected to one side of the third welding layer, the other side of the third welding layer is connected to one end of the second copper pillar, the other end of the second copper pillar is connected to one side of the fourth welding layer, and the other side of the fourth welding layer is connected to the chip package.

[0016] Beneficial effects:

[0017] 1. The utility model packages multiple bare chips in an overlapping manner to reduce the chip packaging area;

[0018] 2. The present invention is provided with an active heat dissipation component in the non-overlapping area, forming a multi-path staggered heat dissipation structure for multiple dies to improve the heat dissipation efficiency of the dies;

[0019] 3. When powered by an external power source, the active heat dissipation component of this invention generates a cooling source at its heat-absorbing end. This cooling source exchanges heat with the heat generated by the die during operation, rapidly reducing the die's temperature. Simultaneously, a heat source is generated at the heat-releasing end of the active heat dissipation component, which releases heat to the external environment through thermal diffusion from the chip package. Therefore, the active heat dissipation component's cooling source output allows for rapid cooling of the die, further improving die heat dissipation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present invention, but do not constitute a limitation of the embodiments of the present invention. In the accompanying drawings:

[0021] Figure 1 A multi-path staggered heat dissipation structure for chip packaging provided by one embodiment of the present invention;

[0022] Figure 2 It is a schematic diagram of the overall structure of an active heat dissipation component provided by one embodiment of the present utility model.

[0023] Description of reference numerals:

[0024] 1. Bare die; 2. Substrate; 3. Second solder pad; 4. PCB board; 5. Electrical component; 6. N-type galvanic couple; 7. P-type galvanic couple; 8. Metal conductor; 9. First solder pad; 10. Metal body; 11. Package layer; 12. Non-overlapping area; 13. Bump; 14. Solder ball; 601. N-type TE layer; 602. First solder layer; 603. First copper pillar; 604. Second solder layer; 701. P-type TE layer; 702. Third solder layer; 703. Second copper pillar; 704. Fourth solder layer. DETAILED DESCRIPTION

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be briefly introduced below in conjunction with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structures of the drawings is only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0026] Figure 1 The utility model provides a multi-path staggered heat dissipation structure of a chip package, such as Figure 1As shown, a multi-path staggered heat dissipation structure of a chip package includes a multi-layer chip package body, wherein multiple layers of bare chips 1 are arranged in the chip package body, and the multiple layers of bare chips 1 are staggered and overlapped. An active heat dissipation component is provided in the non-overlapping area 12 of two adjacent layers of bare chips 1, and the heat absorption end of the active heat dissipation component is in contact with the bare chips 1. The active heat dissipation component is used to generate a cold source at the heat absorption end and a heat source at the heat release end through the power supply of an external power supply.

[0027] In this embodiment, multiple bare chips 1 are packaged in an overlapping manner to reduce the chip packaging area. Furthermore, an active heat dissipation component is provided within the non-overlapping region 12, forming a multi-path interleaved heat dissipation structure for the multiple bare chips 1, thereby improving the heat dissipation efficiency of the bare chips 1. Furthermore, after receiving electrical energy from an external power source, the active heat dissipation component generates a cold source at its heat-absorbing end. This cold source can exchange heat with the heat generated by the bare chips 1 during operation, rapidly reducing the temperature of the bare chips 1. Simultaneously, a heat source is generated at the heat-releasing end of the active heat dissipation component, which releases heat to the external environment through thermal diffusion from the chip package. Therefore, the use of an active heat dissipation component to output a cold source can achieve rapid cooling of the bare chips 1, further improving the heat dissipation efficiency of the bare chips 1.

[0028] In this embodiment, the chip package includes two layers of substrates 2, with the multi-layer die 1 disposed between the two layers of substrates 2. The number of layers of die 1 in this embodiment is preferably two, but may also be more than two; this can be flexibly configured based on actual needs. In this embodiment, two layers of die 1 are used as an example. A first non-overlapping region 12 is formed between the lower layer of die 1 and the upper layer of substrate 2, while a second non-overlapping region 12 is formed between the upper layer of die 1 and the lower layer of substrate.

[0029] In this embodiment, a plurality of second solder pads 3 are provided on the outer sides of the two layers of the substrate 2, and the outer sides of the substrate 2 are used to be electrically connected to the external circuit board through the second solder pads 3; wherein, the external circuit board includes: a PCB board 4 and electrical components 5 soldered on the PCB board 4, and the electrical components 5 can be devices such as resistors, capacitors, diodes, or other chips.

[0030] In this embodiment, the space between the substrate 2 and the bare chip 1 is filled with epoxy resin or other materials to form a packaging layer 11 . The two layers of substrate 2 , the bare chip 1 and the packaging layer 11 constitute a multi-layer structure.

[0031] As a further optimization of this embodiment, the active heat dissipation component includes: an N-type couple 6 and a P-type couple 7, one end of the N-type couple 6 and one end of the P-type couple 7 are electrically connected through a metal conductor 8, and the metal conductor 8 serves as the heat absorption end of the active heat dissipation component. The other end of the N-type couple 6 and the other end of the P-type couple 7 are both connected to the chip package, and the other end of the N-type couple 6 and the other end of the P-type couple 7 serve as the heat release end of the active heat dissipation component. Two first soldering pads 9 are provided on the outside of the chip package, one of the first soldering pads 9 is electrically connected to the other end of the N-type couple 6, and the other first soldering pad 9 is electrically connected to the other end of the P-type couple 7. The two first soldering pads 9 are used to connect to an external power supply.

[0032] In this embodiment, when the other end of the N-type couple 6 is connected to the positive electrode of the external power supply, the other end of the P-type couple 7 is connected to the ground. At this time, a loop is formed between the N-type couple 6, the P-type couple 7 and the external power supply. The external power supply is a DC power supply. When the DC power supply is connected to the N-type couple 6 and the P-type couple 7, current flows through the N-type couple 6 and the P-type couple 7, and energy transfer occurs. Heat is absorbed on the side of the metal conductor 8 (releasing the cold source), and heat is released (releasing the heat source) at the other end of the N-type couple 6 and the other end of the P-type couple 7, thereby achieving heat dissipation for the bare chip 1.

[0033] In this embodiment, the metal conductor 8 is made of copper. Copper material has good electrical conductivity and good thermal conductivity. The heat generated by the bare chip 1 can be quickly transferred to the metal conductor 8 to achieve heat exchange, thereby improving the efficiency of heat exchange.

[0034] Specifically, a metal body 10 is provided on the outside of the chip package, and the metal body 10 is connected to the first pad 9 connected to the other end of the N-type galvanic couple 6. The metal body 10 is electrically connected to the power output end of the external power supply. In this embodiment, the metal body 10 is made of copper.

[0035] In this embodiment, the external power supply can be directly connected to the metal body 10, which is made of copper. At this time, the metal body 10 can quickly take away the heat on the substrate 2 and also play a conductive role, providing working power for the N-type thermocouple 6 and the P-type thermocouple 7.

[0036] As a further optimization of this embodiment, Figure 2As shown, the N-type galvanic couple 6 includes: an N-type TE layer 601, a first welding layer 602, a first copper pillar 603 and a second welding layer 604. One side of the N-type TE layer 601 is connected to the metal conductor 8, and the other side of the N-type TE layer 601 is connected to one side of the first welding layer 602. The other side of the first welding layer 602 is connected to one end of the first copper pillar 603. The other end of the first copper pillar 603 is connected to one side of the second welding layer 604. The other side of the second welding layer 604 is connected to the chip package.

[0037] As a further optimization of this embodiment, Figure 2 As shown, the P-type galvanic couple 7 includes: a P-type TE layer 701, a third welding layer 702, a second copper pillar 703 and a fourth welding layer 704. One side of the P-type TE layer 701 is connected to the metal conductor 8, and the other side of the P-type TE layer 701 is connected to one side of the third welding layer 702. The other side of the third welding layer 702 is connected to one end of the second copper pillar 703. The other end of the second copper pillar 703 is connected to one side of the fourth welding layer 704. The other side of the fourth welding layer 704 is connected to the chip package.

[0038] The N-type TE layer 601 is an N-type doped tellurium (Te) layer, and the P-type TE layer 701 is a P-type doped tellurium (Te) layer. Doping refers to the process of intentionally introducing foreign atoms to change the charge carrier type (electrons or holes) and conductive properties of the material.

[0039] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A multi-path staggered heat dissipation structure for chip packaging, characterized in that: The invention relates to a chip package having a multi-layer structure, wherein a plurality of bare chips (1) are arranged in the chip package, the plurality of bare chips (1) are staggered and overlapped, an active heat dissipation component is arranged in a non-overlapping area (12) of two adjacent layers of bare chips (1), a heat absorbing end of the active heat dissipation component is in contact with the bare chips (1), and the active heat dissipation component is used to generate a cold source at the heat absorbing end and a heat source at the heat releasing end by supplying energy from an external power source.

2. The multi-path staggered heat dissipation structure of chip package according to claim 1, characterized in that: The chip package comprises two layers of substrates (2), and the multi-layer bare chip (1) is arranged between the two layers of substrates (2).

3. The multi-path staggered heat dissipation structure of chip package according to claim 2, characterized in that: The multi-layer bare chip (1) has two layers, a first non-overlapping area (12) is formed between the bare chip (1) of the lower layer and the substrate (2) of the upper layer, and a second non-overlapping area (12) is formed between the bare chip (1) of the upper layer and the substrate (2) of the lower layer.

4. The multi-path staggered heat dissipation structure of chip package according to claim 3, characterized in that: A plurality of second solder pads (3) are provided on the outer sides of the two layers of the substrate (2), and the outer sides of the substrate (2) are used to be electrically connected to an external circuit board via the second solder pads (3).

5. The multi-path staggered heat dissipation structure of chip package according to claim 4, characterized in that: The external circuit board comprises: a PCB board (4) and electrical components (5) welded on the PCB board (4).

6. The multi-path staggered heat dissipation structure of chip package according to claim 3, characterized in that: The active heat dissipation components in the two non-overlapping areas (12) each include: an N-type thermocouple (6) and a P-type thermocouple (7), one end of the N-type thermocouple (6) and one end of the P-type thermocouple (7) are electrically connected via a metal conductor (8), and the metal conductor (8) serves as a heat absorption end of the active heat dissipation component; the other end of the N-type thermocouple (6) and the other end of the P-type thermocouple (7) are both connected to the substrate (2) of the chip package, and the other end of the N-type thermocouple (6) and the other end of the P-type thermocouple (7) serve as a heat release end of the active heat dissipation component; two first soldering pads (9) are provided on the outside of the chip package, one of the first soldering pads (9) is electrically connected to the other end of the N-type thermocouple (6), and the other first soldering pad (9) is electrically connected to the other end of the P-type thermocouple (7), and the two first soldering pads (9) are used to connect to an external power supply.

7. The multi-path staggered heat dissipation structure of chip package according to claim 6, characterized in that: A metal body (10) is provided on the outside of the substrate (2) of the chip package, the metal body (10) is connected to the first pad (9) connected to the other end of the N-type thermocouple (6), and the metal body (10) is electrically connected to the power output end of the external power supply.

8. The multi-path staggered heat dissipation structure of chip package according to claim 7, characterized in that: The metal conductor and the metal body (10) are both made of copper.

9. The multi-path staggered heat dissipation structure of chip package according to claim 6, characterized in that: The N-type galvanic couple (6) comprises: an N-type TE layer (601), a first welding layer (602), a first copper pillar (603) and a second welding layer (604); one side of the N-type TE layer (601) is connected to the metal conductor (8); the other side of the N-type TE layer (601) is connected to one side of the first welding layer (602); the other side of the first welding layer (602) is connected to one end of the first copper pillar (603); the other end of the first copper pillar (603) is connected to one side of the second welding layer (604); and the other side of the second welding layer (604) is connected to the chip package.

10. The multi-path staggered heat dissipation structure of chip package according to claim 7, characterized in that: The P-type galvanic couple (7) comprises: a P-type TE layer (701), a third welding layer (702), a second copper pillar (703) and a fourth welding layer (704); one side of the P-type TE layer (701) is connected to the metal conductor (8); the other side of the P-type TE layer (701) is connected to one side of the third welding layer (702); the other side of the third welding layer (702) is connected to one end of the second copper pillar (703); the other end of the second copper pillar (703) is connected to one side of the fourth welding layer (704); and the other side of the fourth welding layer (704) is connected to the chip package.

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