Reference voltage generation circuit, chip and electronic equipment

Abstract

The embodiment of the utility model provides a reference voltage generation circuit, a chip and electronic equipment. The reference voltage generation circuit comprises a first current mirror module, a second current mirror module, a switch module and a resistor module, wherein the reference voltage generating circuit has a first working state and a second working state, and when the reference voltage generating circuit is in the first working state, the switch module controls at least one path of first mirror current to be input into the resistor module; and when the reference voltage generating circuit is in a second working state, the switch module controls at least one path of second mirror current to be input into the resistor module. According to the reference voltage generation circuit, the fixed reference voltage is output by utilizing the fixed first mirror current, and the periodically changed reference voltage is output by utilizing the periodically changed second mirror current, so that the phenomenon that the existing reference voltage generation circuit only can provide the constant fixed voltage is avoided.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a reference voltage generating circuit, chip, and electronic device. Background Art

[0002] Reference voltages play a crucial role in electronic systems, often serving as a reference voltage for various applications such as comparison, calibration, and measurement. Currently, reference voltages are typically fixed and maintained constant. However, in some scenarios, both a constant reference voltage and a periodically varying reference voltage are required. Therefore, current reference voltage generation circuits are not suitable for these specialized applications. Utility Model Content

[0003] In view of the above problems, embodiments of the present application provide a reference voltage generating circuit, a chip, and an electronic device to solve the above technical problems.

[0004] In a first aspect, an embodiment of the present application provides a reference voltage generating circuit, comprising:

[0005] A first current mirror module for outputting at least one first mirror current, wherein the magnitude of the first mirror current is fixed;

[0006] A second current mirror module for outputting at least one second mirror current, wherein the magnitude of the at least one second mirror current varies periodically;

[0007] a switch module, the switch module being connected to the first current mirror module, and the switch module being connected to the second current mirror module;

[0008] a resistance module, the resistance module being connected to the switch module to receive at least one first mirror current and / or at least one second mirror current;

[0009] The reference voltage generating circuit has a first working state and a second working state. When the reference voltage generating circuit is in the first working state, the switch module controls at least one first mirror current input resistor module to output a reference voltage of a fixed magnitude.

[0010] When the reference voltage generating circuit is in the second working state, the switch module controls at least one second mirror current input resistor module to output a periodically changing reference voltage.

[0011] In a second aspect, an embodiment of the present application further provides a chip comprising the above-mentioned reference voltage generating circuit.

[0012] In a third aspect, an embodiment of the present application further provides an electronic device comprising the above-mentioned chip or reference voltage generating circuit.

[0013] The present application provides at least one first mirror current of fixed magnitude through a first current mirror module, and provides at least one second mirror current of periodically varying magnitude through a second current mirror module. When the reference voltage generating circuit is in a first working state, the switch module controls at least one first mirror current input resistor module; and when the reference voltage generating circuit is in a second working state, the switch module controls at least one second mirror current input resistor module. Therefore, the reference voltage generating circuit can not only use the fixed first mirror current to output a reference voltage of fixed magnitude, but also use the periodically varying second mirror current to output a periodically varying reference voltage, thereby avoiding the phenomenon that the current reference voltage generating circuit can only provide a constant fixed voltage and cannot be adapted to some special application scenarios (such as clock spread spectrum).

[0014] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A circuit diagram of an RC oscillator in related art is shown.

[0017] Figure 2 A schematic diagram of a clock generation circuit involved in an embodiment of the present application is shown.

[0018] Figure 3 A schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown.

[0019] Figure 4 A schematic diagram showing a change of the reference voltage in an embodiment of the present application is shown.

[0020] Figure 5 Another schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown.

[0021] Figure 6 Another schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown.

[0022] Figure 7 Another schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown.

[0023] Figure 8 Another schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown.

[0024] Figure 9 Another schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown.

[0025] Figure 10 Another schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown.

[0026] Figure 11 Another schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown.

[0027] Figure 12 A schematic diagram of a circuit for outputting a preset voltage signal in an embodiment of the present application is shown.

[0028] Figure 13 Another schematic diagram of a circuit for outputting a preset voltage signal in an embodiment of the present application is shown.

[0029] Among them, 10 is a first current mirror module, 20 is a second current mirror module, 30 is a switch module, 40 is a resistor module, a reference voltage Vref, a first mirror current I1, and a second mirror current I2;

[0030] First operational amplifier OP1, first transistor M1, first resistor R1, first mirror transistor MP1, second mirror transistor MP2, third mirror transistor MP3, first switch S1, second operational amplifier OP2, second transistor M2, second resistor R2, fourth mirror transistor MP4, fifth mirror transistor MP5, second switch S2. DETAILED DESCRIPTION

[0031] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0032] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0033] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0034] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0035] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0036] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0037] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects are in an "or" relationship.

[0038] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0039] The first electrode / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second electrode / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first electrode / first end and the second electrode / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode / first end of the transistor is the source, and the second electrode / second end is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode / first end of the transistor is the drain, and the second electrode / second end is the source.

[0040] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0041] Currently, an RC oscillator is an oscillator circuit that generates a clock signal by cyclically charging and discharging a capacitor and comparing the voltages during the charging and discharging process. Figure 1 , Figure 1 A circuit diagram of an RC oscillator in the related art is shown. The RC oscillator includes a comparator COMP1, a comparator COMP2, an RS trigger composed of two NAND gates, a capacitor Cx, a capacitor Cy, a transistor MN1 for controlling the charging and discharging of the capacitor Cx, and a transistor MN2 for controlling the charging and discharging of the capacitor Cy.

[0042] During operation of the RC oscillator, the two NAND gates output control signals OUT1 and OUT2, respectively, thereby controlling transistors MN1 and MN2 to alternately charge capacitors Cx and Cy. When the output voltages IN1 and IN2 of capacitors Cx and Cy exceed the reference voltage Vref, one of capacitors Cx and Cy is switched to charge while the other is discharged, causing the output terminals of comparators COMP1 and COMP2 to output clock signals that alternate between high and low levels.

[0043] In an ideal situation where loop delay (such as comparator delay) is not considered, the time it takes for capacitor Cx\Cy to charge to the reference voltage Vref is half a cycle of the clock signal. The oscillation frequency f of the output clock signal is:

[0044] f=N / (2RC)

[0045] Wherein, N is the ratio of the charging current NIref of the capacitor Cx\Cy to the reference current Iref, R is the resistor corresponding to the reference voltage Vref, and C is the capacitance value of the capacitor Cx\Cy.

[0046] In the actual case of considering the comparator delay, the actual oscillation frequency f of the output clock signal is:

[0047] f=N / 2(RC+t)

[0048] Where t is the time corresponding to the comparator delay.

[0049] It can be seen that since the RC oscillator needs to use a comparator to compare the reference voltage with the voltage during the capacitor charging and discharging process during operation, the delay of the comparator will seriously worsen the frequency drift of the RC oscillator. If the clock signal is spread spectrum by adjusting the capacitor charging and discharging current or changing the capacitor value, the frequency accuracy of the clock signal will also be reduced.

[0050] In one embodiment, the clock signal drift problem of the RC oscillator can be solved by controlling the frequency of the clock signal in a negative feedback manner through a reference voltage. Figure 2 , Figure 2 A schematic diagram of a clock generation circuit involved in the present application is shown, wherein the clock generation circuit includes an operational amplifier OP, a voltage-controlled oscillator, a non-overlapping clock circuit, and a frequency-voltage conversion circuit. The non-overlapping clock circuit can output two non-overlapping clock signals CLKA and CLKB based on the clock signal CLK output by the voltage-controlled oscillator. The frequency-voltage conversion circuit generates a corresponding feedback voltage VFB based on the frequencies of the two non-overlapping clock signals CLKA and CLKB. The operational amplifier OP outputs a control voltage Vctrl under the control of the feedback voltage VFB and the reference voltage Vref to facilitate controlling the oscillation frequency of the voltage-controlled oscillator.

[0051] Since the operational amplifier OP has the virtual short and virtual off characteristics, after the loop stabilizes, VFB = Vref. It can be seen that the frequency f of the clock signal CLK satisfies the following relationship:

[0052] f=VFB*k=Vref*k

[0053] Wherein, k is the frequency-to-voltage conversion coefficient of the frequency-to-voltage conversion circuit.

[0054] As can be seen, the frequency f of the clock signal CLK is controlled by the reference voltage Vref. When the reference voltage Vref varies periodically, the frequency f of the clock signal CLK also varies periodically, thereby achieving the purpose of spectrum spreading of the clock signal CLK. Furthermore, because this clock generation circuit does not require a comparator, the problem of clock signal frequency degradation due to comparator delay is eliminated.

[0055] However, current reference voltages are typically constant fixed voltages, and therefore current reference voltage generation circuits are not suitable for use in the aforementioned clock generation circuit scenario. It is understood that the aforementioned clock generation circuit is only one application scenario for the reference voltage generation circuit of the present application, and the application scenarios of the reference voltage generation circuit of the present application are not limited thereto. For example, the reference voltage generation circuit can also be used in application scenarios such as voltage comparison circuits.

[0056] To this end, the present application provides a reference voltage generating circuit, a chip, and an electronic device, which are described in detail below.

[0057] First, see Figure 3 , Figure 3 A schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown, wherein the reference voltage generating circuit includes a first current mirror module 10 , a second current mirror module 20 , a switch module 30 and a resistor module 40 .

[0058] Specifically, the first current mirror module 10 is connected to a power supply terminal VDD and is configured to output at least one first mirror current I1. The magnitude of each first mirror current I1 is fixed, so that the resistor module 40 generates a fixed reference voltage Vref using the at least one first mirror current I1 of fixed magnitude. Exemplarily, the first current mirror module 10 may include, but is not limited to, a current source such as a voltage-controlled current source (VCCS) or a current-controlled current source (CCCS).

[0059] The second current mirror module 20 is connected to a power supply terminal VDD and is configured to output at least one second mirror current I2. The magnitude of the at least one second mirror current I2 varies periodically, so that the resistor module 40 generates a reference voltage Vref that varies periodically using the second mirror current I2 that varies periodically. For example, the second mirror current I2 may be, but is not limited to, a triangular wave current, a pulse current, a sine wave / cosine wave, or a sawtooth wave current. The second current mirror module 20 may include, but is not limited to, a triangular wave current source, a pulse current source, a sine wave current source, a sawtooth wave current source, and the like.

[0060] The switch module 30 is connected to the first current mirror module 10 to control whether the first mirror current I1 is output, and the switch module 30 is connected to the second current mirror module 20 to control whether the first mirror current I1 is output. In some embodiments of the present application, the switch module 30 can set a corresponding switch for each first mirror current I1 and each second mirror current I2 to facilitate controlling whether each first mirror current I1 and each second mirror current I2 is output. In some embodiments of the present application, the switch module 30 can set a corresponding switch only for a portion of the first mirror current I1 and each second mirror current I2, while the first mirror current I1 without a switch is input to the resistor module 40 in both the first and second operating states of the reference voltage generation circuit.

[0061] For example, the switch module 30 may include but is not limited to transistors with switching functions, such as triodes, MOS transistors, and IGBT transistors.

[0062] The resistor module 40 is configured to generate a corresponding reference voltage Vref after the first mirror current I1 and / or the second mirror current I2 flow through the resistor module 40. For example, when the switch module 30 controls only the first mirror current I1 to flow through the resistor module 40, the resistor module 40 may generate a fixed reference voltage Vref at one end or at a node within the resistor module 40. For another example, when the switch module 30 controls only the second mirror current I2 to flow through the resistor module 40, the resistor module 40 may generate a periodically varying reference voltage Vref at one end or at a node within the resistor module 40. For another example, when the switch module 30 controls both the first mirror current I1 and the second mirror current I2 to flow through the resistor module 40, the resistor module 40 may generate a periodically varying reference voltage Vref at one end or at a node within the resistor module 40.

[0063] For example, the resistor module 40 may include one or more resistors, and the circuit connection mode of the multiple resistors may be series connection, parallel connection, or a combination of series connection and parallel connection.

[0064] In an embodiment of the present application, the reference voltage generating circuit has a first operating state and a second operating state. When the reference voltage generating circuit is in the first operating state, the switch module 30 controls at least one first mirror current I1 input resistor module 40; when the reference voltage generating circuit is in the second operating state, the switch module 30 controls at least one second mirror current I2 input resistor module 40. Therefore, the reference voltage generating circuit can not only use the fixed first mirror current I1 to output a fixed reference voltage Vref, but also use the periodically changing second mirror current I2 to output a periodically changing reference voltage Vref, thereby avoiding the phenomenon that the current reference voltage generating circuit can only provide a constant fixed voltage and cannot be adapted to some special application scenarios (such as clock spread spectrum).

[0065] In some embodiments of the present application, the reference voltage Vref generated by the reference voltage generating circuit in the first working state has a first preset value; the average value of the reference voltage Vref generated by the reference voltage generating circuit in the second working state is equal to the first preset value.

[0066] For example, see Figure 4 , Figure 4 A schematic diagram of the change of the reference voltage Vref in an embodiment of the present application is shown. Before time t1, the reference voltage generating circuit is in a first working state, and the reference voltage Vref remains unchanged at a first preset value. After time t1, the reference voltage generating circuit is in a second working state, and the reference voltage Vref changes periodically and the average magnitude is equal to the first preset value. For an embodiment in which the reference voltage Vref output by the reference voltage generating circuit of the present application is applied to a clock spread spectrum scenario, it can not only ensure that the reference voltage Vref is fixed before the spread spectrum and the frequency of the clock signal is f0, but also ensure that the reference voltage Vref changes periodically after the spread spectrum and the frequency of the clock signal changes periodically with the center frequency f0.

[0067] It should be noted that the first preset value is a setting parameter value of the reference voltage Vref, and those skilled in the art can adjust the value according to actual needs (for example, Figure 2 The frequency of the clock signal CLK in the middle) sets the reference voltage Vref to a size corresponding to a first preset value, such as 1V, 2V, 2.2V, etc., which is not specifically limited in this application.

[0068] In some embodiments of the present application, the first current mirror module 10 outputs a first mirror current I1, and the second current mirror module 20 outputs a second mirror current I2; wherein the average magnitude of the second mirror current I2 is equal to the magnitude of the first mirror current I1.

[0069] For example, see Figure 5 , Figure 5 Another schematic diagram of the reference voltage generating circuit in an embodiment of the present application is shown, wherein the switch module 30 includes a first switch S1 and a second switch S2, the first current mirror module 10 outputs a first mirror current I1, the first switch S1 controls whether the first mirror current I1 flows into the resistor module 40, the second current mirror module 20 outputs a second mirror current I2, and the second switch S2 controls whether the second mirror current I2 flows into the resistor module 40. Since the second mirror current I2 changes periodically and its average magnitude is equal to the magnitude of the first mirror current I1, the average magnitude of the reference voltage Vref generated based on the second mirror current I2 will be equal to the magnitude of the reference voltage Vref generated based on the first mirror current I1, thereby enabling the reference voltage generating circuit of the present application to be applied to clock spread spectrum scenarios.

[0070] In some embodiments of the present application, the first current mirror module 10 outputs multiple first mirror currents I1, and the second current mirror module 20 outputs one second mirror current I2; wherein, at least one first mirror current I1 serves as a target replacement current, and the average magnitude of the second mirror current I2 is equal to the magnitude of the target replacement current.

[0071] For example, see Figure 6 , Figure 6 Another schematic diagram of the reference voltage generating circuit in an embodiment of the present application is shown. The first current mirror module 10 outputs the first mirror currents I1′ and I1″, and the second current mirror module 20 outputs a second mirror current I2. Taking the first mirror current I1″ as the target replacement current as an example, the average magnitude of the second mirror current I2 is equal to the magnitude of the first mirror current I1″.

[0072] It should be noted that, in the first working state and the second working state of the reference voltage generating circuit, all first mirror currents I1 except the target replacement current flow into the resistor module 40. Figure 6 In the embodiment, the first mirror current I1' flows into the resistance module 40, so the reference voltage Vref in the first working state is: Vref = (I1' + I1") * R, and the reference voltage Vref in the second working state is: Vref = (I1' + I2) * R. Since the average size of the second mirror current I2 is equal to the size of the first mirror current I1", the average size of the reference voltage Vref output by the reference voltage generating circuit in the first working state and the second working state is equal, thereby enabling the reference voltage generating circuit of the present application to be applied to clock spread spectrum scenarios.

[0073] It is understandable that the first current mirror module 10 can also output more fixed mirror currents; or, the second current mirror module 20 can also output multiple mirror currents with periodically varying magnitudes.

[0074] In some embodiments of the present application, see Figure 7 , Figure 7 Another schematic diagram of the reference voltage generating circuit in an embodiment of the present application is shown. The switch module 30 includes a first switch S1 and a second switch S2. The first switch S1 is connected to the first current mirror module 10, and the second switch S2 is connected to the second current mirror module 20. The first switch S1 can control whether the target replacement current is input into the resistance module 40, and the second switch S2 can control whether the second mirror current I2 is input into the resistance module 40. Therefore, when the first switch S1 is closed and the second switch S2 is open, the reference voltage generating circuit is in a first working state and outputs a fixed reference voltage Vref; and when the second switch S2 is closed and the first switch S1 is open, the reference voltage generating circuit is in a second working mode and outputs a periodically changing reference voltage Vref.

[0075] As an exemplary embodiment of the first current mirror module 10, see Figure 8 , Figure 8 Another schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown, wherein a first current mirror module 10 includes a first operational amplifier OP1, a first transistor M1, a first resistor R1, a first mirror transistor MP1, and a second mirror transistor MP2; a first end of the first mirror transistor MP1 is connected to a power supply terminal VDD, and a control end of the first mirror transistor MP1 is connected to a second end of the first mirror transistor MP1; a first end of the second mirror transistor MP2 is connected to the power supply terminal VDD, a control end of the second mirror transistor MP2 is connected to the control end of the first mirror transistor MP1, and a second end of the second mirror transistor MP2 is connected to a resistor module 40 to input a mirror current to the resistor module 40; a first end of the first transistor M1 is connected to the second end of the first mirror transistor MP1, a second end of the first transistor M1 is connected to the first end of the first resistor R1, and a second end of the first resistor R1 is connected to ground; a first input end of the first operational amplifier OP1 is connected to a reference voltage VBG, a second input end of the first operational amplifier OP1 is connected to the first end of the first resistor R1, and an output end of the first operational amplifier OP1 is connected to the control end of the first transistor M1.

[0076] It should be noted that the reference voltage VBG can be provided by a bandgap reference source. Since the operational amplifier has a virtual short and virtual off characteristic, the voltage at the first end of the first resistor R1 is equal to the reference voltage VBG connected to the first input end of the first operational amplifier OP1. Therefore, the current flowing through the first mirror transistor MP1, the first transistor M1, and the first resistor R1 is:

[0077] I=VBG / R1

[0078] At the same time, since the source voltage and gate voltage of the first mirror transistor MP1 and the second mirror transistor MP2 are equal, the first mirror transistor MP1 and the second mirror transistor MP2 form a current mirror. It can be seen that the current flowing through the second mirror transistor MP2 (i.e., the first mirror current I1) is:

[0079] I1=I / n1=VBG / (R1*n1)

[0080] Here, n1 is the mirror ratio between the first mirror transistor MP1 and the second mirror transistor MP2.

[0081] It can be seen that since the reference voltage VBG is fixed, the above circuit structure can output a first mirror current I1 of fixed magnitude, so that the reference voltage Vref outputs a reference voltage Vref of fixed magnitude according to the first mirror current I1.

[0082] In some embodiments of the present application, for example, for an embodiment in which the first current mirror module 10 can output multiple current signals, see Figure 9 , Figure 9 Another schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown, wherein the first current mirror module 10 further includes a third mirror transistor MP3, and the switch module 30 includes a first switch S1; a first end of the third mirror transistor MP3 is connected to the power supply terminal VDD, and a control end of the third mirror transistor MP3 is connected to the control end of the second mirror transistor MP2; a first end of the first switch S1 is connected to a second end of the third mirror transistor MP3, and a second end of the first switch S1 is connected to the resistor module 40.

[0083] Similarly, since the source voltage and gate voltage of the first mirror transistor MP1 and the third mirror transistor MP3 are equal, the first mirror transistor MP1 and the third mirror transistor MP3 form a current mirror. It can be seen that when the first switch S1 is closed, the current flowing through the third mirror transistor MP3 (i.e., the first mirror current I1") is:

[0084] I1"=I / n2=VBG / (R1*n2)

[0085] Here, n2 is the mirror ratio between the first mirror transistor MP1 and the third mirror transistor MP3.

[0086] In the first working state of the reference voltage generating circuit, the first switch S1 is in a closed state. At this time, the reference voltage Vref generated by the resistance module 40 is:

[0087] Vref=(I1'+I1”)*R0=(VBG / (R1*n1)+VBG / (R1*n2))*R0

[0088] It can be seen that since the reference voltage VBG is fixed, a reference voltage Vref of fixed magnitude can be output through the above current mirror structure.

[0089] In some embodiments of the present application, see Figure 10 , Figure 10Another schematic diagram of the reference voltage generating circuit in an embodiment of the present application is shown, wherein the second current mirror module 20 includes a second operational amplifier OP2, a second transistor M2, a second resistor R2, a fourth mirror transistor MP4, and a fifth mirror transistor MP5. The switch module 30 also includes a second switch S2. The first end of the fourth mirror transistor MP4 is connected to the power supply terminal VDD, and the control end of the fourth mirror transistor MP4 is connected to the second end of the fourth mirror transistor MP4. The first end of the fifth mirror transistor MP5 is connected to the power supply terminal VDD, and the control end of the fifth mirror transistor MP5 is connected to the control end of the fourth mirror transistor MP4. The fifth mirror transistor M The second end of P5 is connected to the switch module 30; the first end of the second transistor M2 is connected to the second end of the fourth mirror transistor MP4, the second end of the second transistor M2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the ground end; the first input end of the second operational amplifier OP2 is connected to a periodically changing preset voltage signal, the second input end of the second operational amplifier OP2 is connected to the first end of the second resistor R2, and the output end of the second operational amplifier OP2 is connected to the control end of the second transistor M2; the first end of the second switch S2 is connected to the second end of the fifth mirror transistor MP5, and the first end of the second switch S2 is connected to the resistor module 40.

[0090] It should be noted that the periodically changing preset voltage signal VTRI can be a triangular wave voltage signal, a sine / cosine AC voltage signal, a pulse voltage signal, etc., and this application does not impose any specific limitations. Since the operational amplifier has a virtual short and virtual off characteristic, the voltage at the first end of the second resistor R2 is equal to the preset voltage signal connected to the first input end of the second operational amplifier OP2. Therefore, the current flowing through the first mirror transistor MP1, the first transistor M1, and the first resistor R1 is:

[0091] I=VTRI / R2

[0092] At the same time, since the source voltage and gate voltage of the fourth mirror transistor MP4 and the fifth mirror transistor MP5 are equal, the fourth mirror transistor MP4 and the fifth mirror transistor MP5 form a current mirror. It can be seen that the current flowing through the fifth mirror transistor MP5 (i.e., the second mirror current I2) is:

[0093] I3=I / n3=VTRI / (R1*n3)

[0094] Here, n3 is the mirror ratio between the fourth mirror transistor MP4 and the fifth mirror transistor MP5.

[0095] Therefore, in the second working state of the reference voltage generating circuit, the first switch S1 is in the open state, and the second switch S2 is in the closed state. At this time, the reference voltage Vref generated by the resistance module 40 is:

[0096] Vref=(I1'+I2)*R0=(VBG / (R1*n1)+VTRI / (R1*n3))*R0

[0097] It can be seen that, because the preset voltage signal VTRI varies periodically, the above-described current mirror structure can output a second mirror current I2 with periodic variations. Furthermore, when the mirror ratio between the first mirror transistor MP1 and the third mirror transistor MP3 is equal to the mirror ratio between the fourth mirror transistor MP4 and the fifth mirror transistor MP5 (i.e., n2=n3), if the average voltage of the preset voltage signal VTRI is equal to the reference voltage VBG, then the average current magnitude of the second mirror current I2 is also equal to the first mirror current I1″. Therefore, the average magnitude of the reference voltage Vref generated by the resistor module 40 is the same in both the first and second operating states of the reference voltage generating circuit.

[0098] Understandably, in Figure 10 A single resistor R0 is used as the resistor module 40. In some possible embodiments, the resistor module 40 includes multiple resistors connected in series and / or in parallel. In some possible embodiments, the mirror ratio between the first mirror transistor MP1 and the second mirror transistor MP2 may also be equal to the mirror ratio between the fourth mirror transistor MP4 and the fifth mirror transistor MP5 (i.e., n1=n3). For example, see Figure 11 , Figure 11 Another schematic diagram of a reference voltage generating circuit in an embodiment of the present application is shown. The first current mirror module 10 controls whether to output the first mirror current I1 through the first switch S1, and the second current mirror module 20 controls whether to output the second mirror current I2 through the second switch S2. If the average voltage of the preset voltage signal VTRI is equal to the reference voltage VBG, the average current magnitude of the second mirror current I2 is also equal to the first mirror current I1. Therefore, the first current mirror module 10 does not need to output the first mirror current I1 again, and the reference voltage generating circuit can also output a reference voltage Vref with a fixed voltage and a periodically changing voltage and an average magnitude equal to the first preset value.

[0099] As an exemplary embodiment of generating a periodically changing preset voltage signal VTRI, refer to Figure 12 , Figure 12A schematic diagram of a circuit for outputting a preset voltage signal VTRI in an embodiment of the present application is shown, wherein the circuit for outputting a preset voltage signal VTRI includes a first current source IS1, a second current source IS2, a third switch S3, a fourth switch S4, and a capacitor C0; an input end of the first current source IS1 is connected to the power supply end VDD, an output end of the first current source IS1 is connected to a first end of the third switch S3, and a second end of the third switch S3 is connected to the capacitor C0; a first end of the fourth switch S4 is connected to the capacitor C0, a second end of the fourth switch S4 is connected to the input end of the second current source IS2, and an output end of the second current source IS2 is connected to the ground end.

[0100] It should be noted that in the second operating state of the reference voltage generating circuit, the third switch S3 and the fourth switch S4 alternately switch between an open state and a closed state. For example, when the third switch S3 is closed, the fourth switch S4 is open, and the first current source IS1 charges the capacitor C0, causing the preset voltage signal VTRI to increase. When the preset voltage signal VTRI increases to a certain level, the third switch S3 is opened, and the fourth switch S4 is closed. Therefore, the second current source IS2 discharges the capacitor C0, causing the preset voltage signal VTRI to decrease. When the preset voltage signal VTRI decreases to a certain level, the third switch S3 is closed again, and the fourth switch S4 is opened again. The above process is repeated, ultimately generating a periodically varying preset voltage signal VTRI.

[0101] In some embodiments of the present application, see Figure 13 , Figure 13 Another schematic diagram of a circuit for outputting a preset voltage signal VTRI in an embodiment of the present application is shown, wherein the circuit for outputting a preset voltage signal VTRI further includes a first comparator COMP1, a second comparator COMP2, and an RS trigger RSQ; a first input terminal of the first comparator COMP1 is connected to a capacitor C0, a second input terminal of the first comparator COMP1 is connected to a second preset voltage V2, and an output terminal of the first comparator COMP1 is connected to a first input terminal of the RS trigger RSQ; a second input terminal of the second comparator COMP2 is connected to a capacitor C0, a first input terminal of the second comparator COMP2 is connected to a third preset voltage V3, and an output terminal of the second comparator COMP2 is connected to a second input terminal of the RS trigger RSQ; an output terminal of the RS trigger RSQ is connected to a control terminal of a third switch S3, an output terminal of the RS trigger RSQ is connected to a control terminal of a fourth switch S4, and an average value of the second preset voltage V2 and the third preset voltage V3 is equal to the first preset voltage V1.

[0102] It should be noted that, since the first input terminal of the first comparator COMP1 is connected to the capacitor C0 and the second input terminal of the first comparator COMP1 is connected to the second preset voltage V2, when the preset voltage signal VTRI output by the capacitor C0 is greater than the second preset voltage V2, the first comparator COMP1 will output one of the high-level signal and the low-level signal, otherwise, the first comparator COMP1 outputs the other of the high-level signal and the low-level signal; at the same time, since the second input terminal of the first comparator COMP1 is connected to the capacitor C0 and the first input terminal of the first comparator COMP1 is connected to the third preset voltage V3, when the preset voltage signal VTRI output by the capacitor C0 is greater than the third preset voltage V3, the second comparator COMP2 will output one of the high-level signal and the low-level signal, otherwise, the first comparator COMP1 outputs the other of the high-level signal and the low-level signal.

[0103] Therefore, the RS flip-flop RSQ can control the third switch S3 and the fourth switch S4 based on the signal CLKc from the first comparator COMP1 and the second comparator COMP2, thereby alternately charging and discharging the capacitor C0 and generating a periodically varying predetermined voltage signal VTRI. For example, when the predetermined voltage signal VTRI is greater than the second predetermined voltage V2, the first comparator COMP1 will output a high signal and the second comparator COMP2 will output a low signal. Therefore, the RS flip-flop RSQ can control the third switch S3 to open and the fourth switch S4 to close, thereby stopping charging the capacitor C0 and discharging the capacitor C0 through the second current source IS2, causing the predetermined voltage signal VTRI to decrease until it is less than the third predetermined voltage V3. When the predetermined voltage signal VTRI is less than the third predetermined voltage V3, the first comparator COMP1 will output a low signal and the second comparator COMP2 will output a high signal. Therefore, the RS flip-flop RSQ can control the third switch S3 to close and the fourth switch S4 to open, thereby stopping discharging the capacitor C0 and charging the capacitor C0 through the first current source IS1, causing the predetermined voltage signal VTRI to increase until it is greater than the second predetermined voltage V2. Since the above process is repeatedly performed, the purpose of alternately charging and discharging the capacitor C0 and generating the periodically changing preset voltage signal VTRI can be finally achieved.

[0104] The present application also provides a chip including the aforementioned reference voltage generation circuit. An integrated circuit (IC) is also referred to as a chip, and the chip may be, but is not limited to, a system-on-chip (SOC) chip or a system-in-package (SIP) chip. Because the chip of the present application includes the reference voltage generation circuit described in the aforementioned embodiments, it possesses all the beneficial effects of the reference voltage generation circuit in the aforementioned embodiments, and therefore will not be further elaborated here.

[0105] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control panel, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablet computers, and POS (point of sales terminals). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0106] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A reference voltage generating circuit, characterized in that: include: a first current mirror module for outputting at least one first mirror current, wherein the magnitude of the first mirror current is fixed; a second current mirror module for outputting at least one second mirror current, wherein the magnitude of the at least one second mirror current varies periodically; a switch module, wherein the switch module is connected to the first current mirror module and the switch module is connected to the second current mirror module; a resistance module, the resistance module being connected to the switch module to receive at least one first mirror current and / or at least one second mirror current; The reference voltage generating circuit has a first working state and a second working state. When the reference voltage generating circuit is in the first working state, the switch module controls at least one path of the first mirror current to input into the resistance module to output a reference voltage of a fixed magnitude. When the reference voltage generating circuit is in the second working state, the switch module controls at least one second mirror current to be input into the resistance module to output a periodically changing reference voltage.

2. The reference voltage generating circuit according to claim 1, wherein: The reference voltage generated by the reference voltage generating circuit in the first working state has a first preset value; The average magnitude of the reference voltage generated by the reference voltage generating circuit in the second working state is equal to the first preset value.

3. The reference voltage generating circuit according to claim 2, wherein: The first current mirror module outputs one channel of the first mirror current, and the second current mirror module outputs one channel of the second mirror current; The average magnitude of the second mirror current is equal to the magnitude of the first mirror current.

4. The reference voltage generating circuit according to claim 2, wherein: The first current mirror module outputs multiple first mirror currents, and the second current mirror module outputs one second mirror current; At least one of the first mirror currents is used as a target replacement current, and an average magnitude of the second mirror current is equal to a magnitude of the target replacement current.

5. The reference voltage generating circuit according to claim 4, wherein: The switch module includes a first switch and a second switch; The first switch is connected to the first current mirror module to control whether the target replacement current is input into the resistance module; The second switch is connected to the second current mirror module to control whether the second mirror current is input into the resistance module.

6. The reference voltage generating circuit according to claim 1, wherein: The first current mirror module includes a first operational amplifier, a first transistor, a first resistor, a first mirror transistor, and a second mirror transistor; A first end of the first mirror transistor is connected to a power supply end, and a control end of the first mirror transistor is connected to a second end of the first mirror transistor; A first end of the second mirror transistor is connected to the power supply end, a control end of the second mirror transistor is connected to the control end of the first mirror transistor, and a second end of the second mirror transistor is connected to the switch module; The first end of the first transistor is connected to the second end of the first mirror transistor, the second end of the first transistor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the ground; A first input terminal of the first operational amplifier is connected to a reference voltage, a second input terminal of the first operational amplifier is connected to a first terminal of the first resistor, and an output terminal of the first operational amplifier is connected to a control terminal of the first transistor.

7. The reference voltage generating circuit according to claim 6, wherein: The first current mirror module further includes a third mirror transistor; A first end of the third mirror transistor is connected to the power supply end, a control end of the third mirror transistor is connected to the control end of the first mirror transistor, and a second end of the third mirror transistor is connected to the switch module.

8. The reference voltage generating circuit according to claim 1, wherein: The second current mirror module includes a second operational amplifier, a second transistor, a second resistor, a fourth mirror transistor, and a fifth mirror transistor; The first end of the fourth mirror transistor is connected to the power supply end, and the control end of the fourth mirror transistor is connected to the second end of the fourth mirror transistor; A first end of the fifth mirror transistor is connected to the power supply end, a control end of the fifth mirror transistor is connected to the control end of the fourth mirror transistor, and a second end of the fifth mirror transistor is connected to the switch module; The first end of the second transistor is connected to the second end of the fourth mirror transistor, the second end of the second transistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the ground end; The first input terminal of the second operational amplifier is connected to a periodically changing preset voltage signal, the second input terminal of the second operational amplifier is connected to the first terminal of the second resistor, and the output terminal of the second operational amplifier is connected to the control terminal of the second transistor.

9. A chip, characterized in that: The device comprises the reference voltage generating circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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