Electronic package
By adopting the method of covering structure design and laser forming conductive columns in semiconductor packages, warping and thermal damage caused by mismatch in thermal expansion coefficients is solved, the process is simplified, cost is reduced, and product reliability is improved.
Patent Information
- Application Number
- CN202422284979.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-22
- Filing Date
- 2024-09-19
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2034-09-19
AI Technical Summary
The thermal stresses caused by mismatch in the thermal expansion coefficient of existing semiconductor packages are prone to warping, packaging colloid delamination and bubble problems. At the same time, high-temperature thermal processes cause damage to the semiconductor chip, and complex processes lead to high costs.
The electronic components are placed in the grooves and the electronic components are coated with a plate made of semiconductor material to reduce the thermal stress of mismatched thermal expansion coefficients, and the process is simplified by forming a conductive column through laser.
It effectively avoids the problem of packaging warping, packaging colloid delamination and bubbles, reduces damage to electronic components by the thermal process, simplifies the process and reduces costs, and improves product reliability.
Smart Images
Figure CN223245601U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a semiconductor device, and more particularly to an electronic package capable of improving product yield. Background Art
[0002] With the rapid development of portable electronic products in recent years, various related products have gradually moved towards high density, high performance, and light, thin, short, and small sizes. As a result, various package-on-package (PoP) processes have also been continuously innovated to meet the requirements of lightness, thinness, shortness, and high density.
[0003] Figures 1A to 1D It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package 1 .
[0004] like Figure 1A As shown, a circuit structure 10 is provided on a carrier 9, and a plurality of conductive pillars 13 are formed on the circuit structure 10, and at least one semiconductor chip 11 is provided on the circuit structure 10 with its non-active surface 11b through a die-bonding layer 18, and the active surface 11a of the semiconductor chip 11 has a plurality of conductive bumps 12.
[0005] like Figure 1B As shown, a packaging resin 15 is formed on the circuit structure 10 so that the packaging resin 15 covers the semiconductor chip 11 and the conductive pillars 13. Then, through a flattening process, the surface of the packaging resin 15 is flush with the end surface of the conductive pillars 13, so that the conductive pillars 13 are exposed on the surface of the packaging resin 15.
[0006] like Figure 1C As shown, a wiring structure 16 is formed on the packaging resin 15 to electrically connect the conductive pillars 13 and the plurality of conductive bumps 12 , so that a plurality of conductive elements 17 with C4 bump specifications and other passive elements 14 can be formed on the wiring structure 16 .
[0007] like Figure 1D As shown, the carrier 9 is removed to expose the circuit structure 10 , and then a plurality of solder balls 19 are formed on the circuit structure 10 so that the solder balls 19 are electrically connected to the circuit structure 10 .
[0008] However, in conventional methods of manufacturing semiconductor packages 1, the coefficient of thermal expansion (CTE) between the encapsulant 15 and the semiconductor chip 11 is mismatched, which can easily lead to uneven thermal stress. This can cause the encapsulant 15 to warp, resulting in cracks in the semiconductor package 1 (especially the semiconductor chip 11). Furthermore, the die-attachment layer 18 is prone to peeling, and can even cause bubbles to form in the encapsulant 15 during the manufacturing process.
[0009] Furthermore, in the conventional method of manufacturing the semiconductor package 1, the semiconductor chip 11 is disposed in an earlier process. Therefore, the semiconductor chip 11 must undergo high-temperature thermal processes such as the production of the encapsulation gel 15, the wiring structure 16 (such as RDL specifications), and the conductive elements 17 of the C4 bump specifications. This causes the semiconductor chip 1 to suffer thermal damage, such as thermal energy accumulation. The damage accumulates and increases, and thus easily exceeds the load of the semiconductor chip 11, causing the semiconductor chip 11 to malfunction or even be damaged, thereby causing product reliability issues.
[0010] Furthermore, directly manufacturing the conductive pillar 13 on the circuit structure 10 requires complicated processes such as exposure, development, and electroplating, which is not conducive to reducing the manufacturing cost of the semiconductor package 1 .
[0011] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Utility Model Content
[0012] In view of the various deficiencies of the above-mentioned prior art, the present application provides an electronic package, comprising: a coating structure having a first surface and a second surface relative to each other, wherein the coating structure has at least one groove and a plurality of through-holes connecting the first surface and the second surface, and a plurality of recesses connecting the first surface are formed on the bottom surface of the groove, so that the groove connects the first surface and the second surface through the plurality of recesses; a circuit structure, disposed on the first surface of the coating structure and exposed to the plurality of recesses and the plurality of through-holes; a plurality of conductive posts, disposed in the plurality of through-holes and electrically connected to the circuit structure; an electronic component, disposed in the groove and electrically connected to the circuit structure; and a wiring structure, disposed on the second surface of the coating structure and electrically connected to the plurality of conductive posts and / or the electronic component.
[0013] The present application also provides a method for manufacturing an electronic package, comprising: providing a coating structure having a first surface and a second surface relative to each other, wherein the second surface of the coating structure has at least one groove; forming a circuit structure on the first surface of the coating structure; forming a plurality of through-holes connecting the first surface and the second surface on the second surface of the coating structure, and forming a plurality of recesses on the bottom surface of the groove; forming a plurality of conductive posts electrically connected to the circuit structure in the plurality of through-holes, and arranging at least one electronic component in the groove, and the electronic component is electrically connected to the circuit structure; and forming a wiring structure on the second surface of the coating structure, and electrically connecting the wiring structure to the plurality of conductive posts.
[0014] In the aforementioned electronic package and its manufacturing method, the encapsulating structure is a plate made of semiconductor material.
[0015] In the aforementioned electronic package and method for manufacturing the same, an insulating material is filled between the electronic component and the recess. For example, the electronic component has an active surface and an inactive surface facing each other, and the active surface is electrically connected to the wiring structure via a plurality of conductive bumps. The plurality of conductive bumps are disposed within the plurality of recesses, and no adhesive is interposed between the inactive surface and the wiring structure. Furthermore, the inactive surface contacts the wiring structure.
[0016] In the aforementioned electronic package and its manufacturing method, a conductive element is formed on the surface of the circuit structure that does not contact the covering structure.
[0017] As can be seen from the above, in the electronic package and its manufacturing method of the present application, the electronic component is mainly arranged in the groove through the design of the encapsulation structure, so that the encapsulation structure encapsulates the electronic component, which is beneficial to reduce thermal stress. Therefore, compared with the existing technology, the present application can avoid the problems of peeling of the existing die-stack adhesive layer and void generation in the packaging colloid during the thermal process, and the encapsulation structure is not prone to warping, thereby avoiding the problem of the electronic package or electronic component being broken.
[0018] Furthermore, the manufacturing method of the present application first manufactures the circuit structure and the conductive elements, and then sets the electronic elements. Therefore, compared with the existing technology, the present application can prevent the electronic elements from being damaged by the heat accumulation generated by the RDL process and the conductive elements during the manufacturing process, thereby improving the process and product reliability.
[0019] Furthermore, the manufacturing method of the present application utilizes a laser to form through-holes on the encapsulation structure to produce the conductive pillars. Therefore, compared to the prior art, the manufacturing method of the present application effectively simplifies the manufacturing process, thereby helping to reduce the manufacturing cost of the electronic package. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figures 1A to 1D It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package.
[0021] Figures 2A to 2E It is a cross-sectional schematic diagram of the manufacturing method of the electronic package of the present application.
[0022] Description of Reference Numerals
[0023] 1 Semiconductor Package
[0024] 10,20 Line Structure
[0025] 11. Semiconductor Chips
[0026] 11a, 21a active surface
[0027] 11b, 21b non-active surface
[0028] 12,22 conductive bumps
[0029] 13,23 Conductive Column
[0030] 14 Passive Components
[0031] 15 Encapsulation colloid
[0032] 16,26 wiring structure
[0033] 17,27 Conductive elements
[0034] 18. Place the die-cast layer
[0035] 19 solder balls
[0036] 2 Electronic packaging
[0037] 200 dielectric layer
[0038] 201 circuit layer
[0039] 203 insulation protective layer
[0040] 21 Electronic components
[0041] 210 electrode pads
[0042] 220 recess
[0043] 230 Perforation
[0044] 24 Auxiliary functional components
[0045] 25 cladding structure
[0046] 25a first surface
[0047] 25b Second surface
[0048] 250 grooves
[0049] 260 insulation layer
[0050] 261 wiring layer
[0051] 262 electrical contact pads
[0052] 28 Insulation Materials
[0053] 29 Conductive parts
[0054] 9 bearing members. DETAILED DESCRIPTION
[0055] The following describes the implementation of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.
[0056] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed in this application without affecting the efficacy and purpose that can be achieved by this application. At the same time, terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of this application. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of this application without substantially changing the technical content.
[0057] Figures 2A to 2E It is a cross-sectional schematic diagram of a method for manufacturing the electronic package 2 of the present application.
[0058] like Figure 2A As shown, a covering structure 25 having a groove 250 is provided.
[0059] In this embodiment, the encapsulation structure 25 is, for example, a plate made of a semiconductor material (such as silicon or glass), having a first surface 25a and a second surface 25b opposite to each other, such that the groove 250 is formed on the second surface 25b. For example, the groove 250 can be formed by laser, etching, or other methods, so that the groove 250 does not penetrate the encapsulation structure 25.
[0060] like Figure 2B As shown, a circuit structure 20 is formed on the first surface 25 a of the encapsulation structure 25 .
[0061] In this embodiment, the circuit structure 20 is coreless and includes multiple dielectric layers 200 and a circuit layer 201 disposed on the dielectric layers 200, such as a redistribution layer (RDL). For example, the circuit layer 201 is formed of copper, and the dielectric layer 200 is formed of a material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials.
[0062] Furthermore, a plurality of conductive elements 27, such as solder material, are formed on the outermost circuit layer 201 of the circuit structure 20, such as C4 bump specifications. For example, an insulating protective layer 203, such as a solder mask, can be formed on the dielectric layer 200, and a plurality of openings can be formed in the insulating protective layer 203 to expose the circuit layer 201 to provide for the connection of the conductive elements 27.
[0063] Furthermore, at least one auxiliary functional element 24 , such as a passive element, may be placed on the outermost circuit layer 201 of the circuit structure 20 .
[0064] like Figure 2C As shown, a plurality of through holes 230 are formed on the second surface 25 b of the covering structure 25 to connect the first surface 25 a and the second surface 25 b , and a plurality of recesses 220 are formed on the bottom surface of the groove 250 .
[0065] In this embodiment, the recess 220 penetrates the cladding structure 25, so that the circuit layer 201 of the circuit structure 20 is exposed in the recess 220 and the through-hole 230. For example, the recess 220 and the through-hole 230 can be formed by laser, etching or other methods.
[0066] like Figure 2D As shown, a plurality of conductive pillars 23 electrically connected to the circuit layer 201 are formed on the circuit structure 20 with the through-hole 230 exposed, and at least one electronic component 21 is placed in the recess 220 through a plurality of conductive bumps 22 and disposed in the groove 250 and electrically connected to the circuit structure 20.
[0067] The conductive pillars 23 are formed on the circuit layer 201 by electroplating to electrically connect the circuit layer 201. For example, the conductive pillars 23 are made of a metal material such as copper or a solder material.
[0068] The electronic component 21 is an active component, a passive component, or a combination thereof, wherein the active component is a semiconductor chip, and the passive component is a resistor, a capacitor, or an inductor.
[0069] In this embodiment, the electronic component 21 is a semiconductor chip having an active surface 21 a and an inactive surface 21 b relative to each other. The electrode pad 210 on the active surface 21 a is flip-chip-mounted with the active surface 21 a face-down through a plurality of conductive bumps 22 such as copper pillars or solder balls, and is disposed on the circuit layer 201 with the recess 220 exposed, and is electrically connected to the circuit layer 201.
[0070] Furthermore, an insulating material 28 such as a primer is disposed between the electronic component 21 and the groove 250 (including between the side surface of the electronic component 21 and the wall surface of the groove 250 and between the active surface 21 a of the electronic component 21 and the bottom surface of the groove 250 ), and the insulating material 28 covers the conductive bumps 22 .
[0071] Furthermore, a flattening process may be performed, for example, by polishing to remove part of the material of the conductive pillar 23, part of the material of the electronic component 21, and part of the material of the encapsulation structure 25, so that the end surface of the conductive pillar 23, the inactive surface 21b of the electronic component 21, and the second surface 25b of the encapsulation structure 25 are coplanar (or flush with each other).
[0072] like Figure 2E As shown, a wiring structure 26 is formed on the second surface 25 b of the encapsulation structure 25 , and the wiring structure 26 is electrically connected to the conductive pillars 23 .
[0073] In this embodiment, the wiring structure 26 includes a plurality of insulating layers 260 and a plurality of wiring layers 261 disposed on the insulating layers 260. The outermost insulating layer 260 can serve as a solder mask, so that a portion of the outermost wiring layer 261 is exposed from the solder mask to serve as an electrical contact pad 262. A plurality of conductive members 29 (e.g., solder material) can be disposed on the electrical contact pad 262 to facilitate subsequent placement and electrical connection to an electronic component (not shown) via the plurality of conductive members 29. For example, the wiring layer 261 can be formed of copper, and the insulating layer 260 can be formed of a dielectric material such as poly(p-oxadiazole) (PBO), polyimide (PI), prepreg (PP), or other dielectric materials.
[0074] In subsequent manufacturing processes, the electronic package 2 can be mounted on an electronic device such as a circuit board (not shown) through the conductive elements 27 .
[0075] Therefore, the manufacturing method of the present application mainly uses a semiconductor material plate as the design of the encapsulation structure 25 to dispose the electronic component 21 in the groove 250, so that the encapsulation structure 25 encapsulates the electronic component 21. Because the thermal expansion coefficient (CTE) between the encapsulation structure 25 and the electronic component 21 matches, it is beneficial to reduce thermal stress. Therefore, compared with the existing technology, the manufacturing method of the present application can not only avoid the existing problems such as peeling of the die-cast adhesive layer 18 and the generation of bubbles in the packaging adhesive 15 during the thermal process, but also the encapsulation structure 25 is not prone to warping, and can avoid the reliability problems of the electronic package 2 or the electronic component 21 such as fragmentation, poor ball condition (i.e., the conductive element 27 falls and the circuit is electrically disconnected), non-wetting of the conductive element 27, or delamination of the circuit structure 20 (or wiring structure 26), thereby improving the reliability of the terminal electronic products (such as computers, mobile phones, etc.) using the electronic package.
[0076] Furthermore, the manufacturing method of the present application first manufactures the circuit structure 20 and the conductive element 27 of the C4 bump specification, and then sets the electronic element 21. Therefore, compared with the existing technology (first setting the semiconductor chip 11, and then manufacturing the wiring structure 16 and the conductive element 17 of the C4 bump specification), the present application can prevent the electronic element 21 (or semiconductor chip) from being damaged by the heat accumulation generated by the RDL process and the conductive element 27 during the manufacturing process, thereby improving the process and product reliability.
[0077] Furthermore, the manufacturing method of the present application utilizes a laser method to form the through-holes 230 on the encapsulation structure 25 to produce the conductive pillars 23 . Therefore, compared to the existing complicated processes such as exposure, development and electroplating, the manufacturing method of the present application effectively simplifies the process, thereby helping to reduce the manufacturing cost of the electronic package 2 .
[0078] The present application provides an electronic package 2 , including: a coating structure 25 , an electronic component 21 , a plurality of conductive pillars 23 , a circuit structure 20 , and a wiring structure 26 .
[0079] The encapsulating structure 25 has a first surface 25a and a second surface 25b opposite to each other, wherein the encapsulating structure 25 is provided with a groove 250 and a plurality of through holes 230 connecting the first surface 25a and the second surface 25b on the second surface 25b, and a plurality of recesses 220 connected to the first surface 25a are formed on the bottom surface of the groove 250, so that the groove 250 is combined with the plurality of recesses 220 to connect the first surface 25a and the second surface 25b.
[0080] The circuit structure 20 is disposed on the first surface 25 a of the covering structure 25 and is exposed at the plurality of recesses 220 and the plurality of through holes 230 .
[0081] The plurality of conductive pillars 23 are disposed in the plurality of through-holes 230 and electrically connected to the circuit structure 20 .
[0082] The electronic component 21 is disposed in the groove 250 and electrically connected to the circuit structure 20 .
[0083] The wiring structure 26 is disposed on the second surface 25 b of the encapsulation structure 25 and is electrically connected to the plurality of conductive pillars 23 and / or the electronic component 21 .
[0084] In one embodiment, the encapsulation structure 25 is a plate made of semiconductor material.
[0085] In one embodiment, the electronic component 21 is a semiconductor chip. For example, the electronic component 21 has an active surface 21a and an inactive surface 21b opposite each other. The active surface 21a is electrically connected to the circuit structure 20, while no adhesive is present between the inactive surface 21b and the wiring structure 26. Furthermore, the inactive surface 21b contacts the wiring structure 26.
[0086] In one embodiment, a conductive element 27 is formed on the surface of the circuit structure 20 that is not in contact with the cladding structure 25 .
[0087] In summary, the electronic package and its manufacturing method of the present application, through the design of the encapsulation structure, are arranged in the groove of the encapsulation structure, so that the encapsulation structure encapsulates the electronic component, which is beneficial to reducing thermal stress. Therefore, when performing the thermal process, the present application can not only avoid the problems of peeling of the existing die-stack adhesive layer and the generation of voids in the packaging colloid, but also the encapsulation structure is not prone to warping, thereby avoiding the problem of the electronic package or electronic component being broken.
[0088] Furthermore, the manufacturing method of the present application first manufactures the circuit structure and the conductive elements, and then sets the electronic elements. Therefore, the present application can prevent the electronic elements (or semiconductor chips) from being damaged by the heat accumulation generated by the RDL process and the conductive elements during the manufacturing process, thereby improving the process and product reliability.
[0089] Furthermore, the manufacturing method of the present application utilizes a laser to form through-holes on the encapsulation structure to produce the conductive pillars. Therefore, the manufacturing method of the present application effectively simplifies the manufacturing process, thereby facilitating a reduction in the manufacturing cost of the electronic package.
[0090] The above embodiments are intended only to illustrate the principles and effects of this application and are not intended to limit this application. Those skilled in the art may modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application shall be as set forth in the claims.
Claims
1. An electronic package, characterized in that: include: A covering structure having a first surface and a second surface opposite to each other, wherein the covering structure is provided with a groove on the second surface and a plurality of through-holes connecting the first surface and the second surface, and a plurality of recesses connected to the first surface are formed on the bottom surface of the groove, so that the groove is combined with the plurality of recesses to connect the first surface and the second surface; a circuit structure disposed on the first surface of the covering structure and exposed in the plurality of recesses and the plurality of through holes; a plurality of conductive posts disposed in the plurality of through-holes and electrically connected to the circuit structure; an electronic component disposed in the groove and electrically connected to the circuit structure; and The wiring structure is disposed on the second surface of the encapsulating structure and is electrically connected to the plurality of conductive pillars and / or the electronic element.
2. The electronic package according to claim 1, wherein The covering structure is a plate body made of semiconductor material.
3. The electronic package according to claim 1, wherein: Insulation material is filled between the electronic component and the groove.
4. The electronic package according to claim 1, wherein: The electronic component has an opposite active surface and an inactive surface, and the active surface is electrically connected to the circuit structure through a plurality of conductive bumps. The conductive bumps are arranged in the plurality of recesses, and there is no glue between the inactive surface and the wiring structure.
5. The electronic package according to claim 4, wherein: The inactive surface contacts the wiring structure.
6. The electronic package according to claim 1, wherein: A plurality of conductive elements are formed on the surface of the circuit structure that does not contact the cladding structure.