Packaging body and packaging device thereof

Abstract

The utility model relates to the field of semiconductor devices, and discloses a packaging body and a packaging device thereof, the packaging body comprises a packaging shell, a wafer, a base island, a plurality of pins and a heat dissipation piece, the wafer and the base island are sequentially arranged in the packaging shell from top to bottom, the heat dissipation piece is arranged on one side, away from the wafer, of the base island, and the plurality of pins are arranged in the packaging shell. The heat dissipation piece is used for being attached to a circuit board, and the multiple pins are oppositely arranged on the two sides of the packaging shell and connected with the wafer. According to the utility model, the heat dissipation piece is arranged below the base island, the wafer directly conducts heat to the heat dissipation piece through the base island, and then is attached to the circuit board through the heat dissipation piece, so that the wafer can be effectively cooled through the heat dissipation piece, the structure is simple, and the production and manufacturing are convenient.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a packaging body and a packaging device thereof. Background Art

[0002] With the increasing demand for portable small electronic products such as drones, handheld power tools, and outdoor power supplies, power device packaging is developing towards small size, low package resistance, low thermal resistance, and low cost.

[0003] Existing chip packaging uses a flip-chip package method. There is no pad on the bottom of the package, and there is no direct contact between the chip and the printed circuit board. Effective heat dissipation cannot be achieved through the printed circuit board (PCB), which is also called a PCB board. The package thermal resistance is extremely large.

[0004] Therefore, the existing technology still needs to be improved and developed. Utility Model Content

[0005] The technical problem to be solved by the present invention is to provide a package body and a packaging device thereof in view of the above-mentioned defects of the prior art, aiming to solve the problem in the prior art that the chip has no direct contact with the PCB board and cannot effectively dissipate heat through the PCB board.

[0006] The technical solutions adopted by the present invention to solve the technical problems are as follows:

[0007] A package body includes a package shell, a wafer, a base island, multiple pins and a heat sink. The wafer and the base island are arranged in sequence from top to bottom in the package shell. The heat sink is provided on the side of the base island facing away from the wafer. The heat sink is used to be attached to a circuit board. The multiple pins are arranged relatively on both sides of the package shell and are connected to the wafer.

[0008] Optionally, the heat sink is a solder pad.

[0009] Optionally, the shape of the pad is circular or rectangular.

[0010] Optionally, a thermally conductive adhesive layer is provided between the wafer and the base island.

[0011] Optionally, the package body also includes a lead frame arranged in the package shell, a carrying portion for carrying the base island is provided in the middle position of the lead frame, a plurality of connecting portions are arranged around the carrying portion, and the plurality of connecting portions are arranged in two groups relative to each other along the width direction of the lead frame, the connecting portions protrude from the lead frame arrangement and are used to connect pins, wherein the lead frame includes two parallel opposite long sides and two parallel opposite wide sides, the connecting portion close to one of the wide sides protrudes from the lead frame arrangement, and the protruding portion is a first area, and the connecting portion close to the other wide side protrudes from the lead frame arrangement, and the protruding portion is a second area.

[0012] Optionally, the first area and the second area are equal.

[0013] Optionally, the first area is 0.5-0.8 mm 2 , the second area is 0.5-0.8mm 2 .

[0014] Optionally, at least one of the connecting parts is connected to the bearing part.

[0015] Optionally, there are six connecting portions, and the six connecting portions are arranged in two groups opposite to each other along the width direction of the lead frame.

[0016] A packaging device comprises a packaging body as described in any one of the above technical solutions, and a packaging chip arranged on the packaging body.

[0017] Beneficial effects:

[0018] The utility model provides a package body and a packaging device thereof, wherein a heat sink is arranged below the base island, and the wafer is directly heat-conducted to the heat sink through the base island, and then attached to the circuit board through the heat sink, so that the wafer can be effectively cooled by the heat sink, and then the chip can be cooled, thereby extending the service life of the chip. The utility model has a simple structure and is easy to produce and manufacture. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural diagram of the package body of the utility model;

[0020] Figure 2 It is a structural diagram of an existing package lead frame;

[0021] Figure 3 It is a structural diagram of the lead frame of the utility model;

[0022] Figure 4 This is a wiring structure diagram of the lead frame of the utility model.

[0023] In the picture:

[0024] 100. Package shell; 200. Lead; 300. Pin; 400. Wafer; 500. Thermal conductive adhesive layer; 600. Base island; 700. Pad; 800. Lead frame; 810. Carrying part; 820. Wide side; 830. Long side; 910. First connection part; 920. Second connection part; 930. Third connection part; 940. Fourth connection part; 950. Fifth connection part; 960. Sixth connection part; 1000. Chip. DETAILED DESCRIPTION

[0025] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0026] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "multiple" means two or more.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0028] Existing chip packaging uses a flip-chip package method. There is no pad on the bottom of the package, and there is no direct contact between the chip and the PCB board. Effective heat dissipation through the PCB board cannot be achieved. The package thermal resistance is extremely large. In addition, the lead frame design limits the number of lead soldering, resulting in an inability to bond more wires, resulting in extremely large package resistance.

[0029] The existing chip packaging has the following problems:

[0030] 1. It adopts upright inverted sealing, with no pad at the bottom, and the heat of the chip cannot be conducted out.

[0031] 2. The shape of the original lead frame is unreasonable (such as Figure 2 As shown), the parasitic resistance of the bonding wire is large.

[0032] Based on the above issues, see Figure 1 As shown, the present application provides a package body, including a package shell 100, a wafer 400, a base island 600, a plurality of pins 300 and a heat sink, wherein the wafer 400 and the base island 600 are sequentially arranged from top to bottom in the package shell 100, and the heat sink is provided on the side of the base island 600 away from the wafer 400, and the heat sink is used to be attached to a circuit board, and the plurality of pins 300 are relatively arranged on both sides of the package shell 100 and connected to the wafer 400.

[0033] Specifically, this embodiment discloses a heat sink disposed beneath the base island 600. Heat from the wafer 400 is transferred to the heat sink through the base island 600, and then directly transferred to the circuit board (PCB), also known as a printed circuit board. This effectively dissipates heat from the wafer 400 through the heat sink, improving the operational reliability of the wafer 400. Furthermore, installing the heat sink beneath the base island 600 is a mature process with low cost. More specifically, the pins 300 are connected to the wafer 400 via the leads 200, allowing input or output signals from the wafer 400 to be transmitted to the pins 300.

[0034] It should be noted that wafer 400 is the material for manufacturing chips. It is produced through photolithography, ion implantation, deposition, etching and planarization processes, and then cut out a suitable area and packaged to form a chip. In this solution, wafer 400 in this solution refers to wafer 400 after production, that is, the chip, so that the heat sink can dissipate heat from the chip, extend the service life of the chip, and has a simple structure, which is convenient for production and manufacturing.

[0035] See also Figure 1 As shown, in another embodiment of the present application, the heat dissipation element is a solder pad 700 .

[0036] Specifically, the present embodiment discloses that the heat sink is a solder pad 700 . The solder pad 700 is made of copper material and has good thermal conductivity, so that the heat of the wafer 400 can be effectively transferred.

[0037] Furthermore, the shape of the pad 700 can be circular, square or other shapes, and its size and shape can be made according to the usage scenario. Preferably, the pad 700 is square to match the structural shape of the package, covering more circuit board area for better heat dissipation.

[0038] See also Figure 1 As shown, in another embodiment of the present application, a thermal conductive adhesive layer 500 is provided between the wafer 400 and the base island 600 .

[0039] Specifically, the present embodiment discloses a thermally conductive adhesive layer 500, which is a special adhesive with efficient heat transfer performance. The wafer 400 and the base island 600 are bonded together by the thermally conductive adhesive layer 500, which helps to reduce the thermal resistance between the wafer 400 and the base island 600, facilitates the rapid transfer of heat from the wafer 400 to the base island 600, and extends the service life of the wafer 400. More specifically, the thermally conductive adhesive layer 500 is mainly composed of a resin matrix (such as epoxy resin, silicone or polyurethane) and a thermally conductive filler. The thermally conductive filler can be a metal oxide (such as aluminum oxide, copper powder), a metal powder (such as silver, copper), a carbon-based material (such as graphene) or other highly thermally conductive inorganic materials. These fillers form a thermally conductive network in the colloid, so that heat can be rapidly transferred along this network.

[0040] See also Figure 3 As shown, in another embodiment of the present application, the package body also includes a lead frame 800 arranged in the package shell 100, and a supporting portion 810 for supporting the base island 600 is provided in the middle position of the lead frame 800, and a plurality of connecting portions are arranged around the supporting portion 810, and the plurality of connecting portions are arranged in two groups relative to each other along the width direction of the lead frame 800, and the connecting portion protrudes from the lead frame 800 and is used to connect the pin 200, wherein the lead frame 800 includes two parallel opposite long sides 830 and two parallel opposite wide sides 820, the connecting portion near one of the wide sides 820 protrudes from the lead frame 800, and the protruding portion is a first area, and the connecting portion near the other wide side 820 protrudes from the lead frame 800, and the protruding portion is a second area.

[0041] Specifically, this embodiment discloses a lead frame 800, which includes two parallel, opposing long sides 830 and two parallel, opposing wide sides 820. Thus, the lead frame 800 is rectangular in shape. A carrier portion 810 is disposed in the middle of the lead frame 800. The carrier portion 810 is used to support the base island 600, thereby supporting the wafer 400 on the base island 600 and, in turn, loading the chip. More specifically, a plurality of connecting portions are disposed around the carrier portion 810. The plurality of connecting portions are arranged in two groups opposite each other along the width direction of the lead frame 800. The connecting portions protrude from the lead frame 800 and are used to connect to the pins 200, allowing the chip located on the carrier portion 810 to be connected to the connecting portion circuit, thereby allowing the chip to input or output signals on the connecting portion.

[0042] Further, Figure 3 The following are examples: Figure 3 The left and right sides are two wide sides 820 of the lead frame 800. Figure 3 The upper and lower sides of the lead frame 800 are the two long sides 830, as shown in FIG. Figure 3 and Figure 4 As shown, the connection part includes a first connection part 910, a second connection part 920, a third connection part 930, a fourth connection part 940, a fifth connection part 950 and a sixth connection part 960, the first area refers to the area of the sixth connection part 960, and the second area refers to the area of the fourth connection part 940.

[0043] See also Figure 3 As shown, when the sixth connection portion 960 close to the left wide side 820 is arranged along the first area protruding from the lead frame 800, the first area is larger than the existing Figure 2 The area of the sixth connection portion 960 is increased, thereby increasing the area of the sixth connection portion 960 in the lead frame 800, so that the sixth connection portion 960 can be connected in parallel with more circuits and the resistance is smaller. When the fourth connection portion 940 close to the right wide side 820 is arranged along the second area protruding from the lead frame 800, the second area is larger than the existing Figure 2 The area of the fourth connection portion 940 is increased, so that the fourth connection portion 940 can be connected in parallel with more circuits, and the resistance is smaller. In this solution, by changing the structural shape of the connection portion within the lead frame 800, more circuits can be connected in parallel, and the resistance is smaller.

[0044] It should be noted that the internal resistance of the package of the power MOS tube is determined by the lead 200. Most common packages use 42um copper wire as the lead 200. Figure 2 As shown, a maximum of 6 wires (in parallel) can be connected to a single end in the package, each with a resistance of about 18mΩ, and the actual single-ended resistance is 3mΩ. Figure 4As shown, the chip 1000 is located in the center of the lead frame 800. Chip 1000 can have 12 wires (connected in parallel) on a single end, with an actual single-ended resistance of 1.5mΩ. This reduces the combined internal resistance of the input and output wires by 3mΩ. When the load current is 10A, this 3mΩ reduction reduces power consumption by 0.3W, thereby reducing parasitic resistance in the wires, improving efficiency, and reducing heat generation and power consumption.

[0045] Furthermore, in another specific embodiment of the present invention, see Figure 2 and Figure 4 As shown, the first area and the second area are equal.

[0046] Specifically, when the first area and the second area are equal, the sixth connection part 960 and the fourth connection part 940 form a symmetrical relationship in the center of the lead frame 800. Both connection parts can connect more lines, making the chip's wiring parasitic resistance smaller, and the symmetrical setting is conducive to aesthetics.

[0047] Furthermore, the first area and the second area are not equal.

[0048] Specifically, there are two situations in which the first area and the second area are not equal: the first area is larger than the second area, and the second area is smaller than the second area; however, regardless of the first area or the second area, both are larger than the areas of the sixth connection portion 960 and the fourth connection portion 940 in the prior art. The sixth connection portion 960 and the fourth connection portion 940 can also play a role in reducing the parasitic resistance of the bonding wire.

[0049] It is understood that the connecting portion includes a head and a tail, the head and the tail are integrally formed, the head is in the shape of a rectangle, the length of the head is in the range of 0.40-0.50 mm, and the width is in the range of 0.6-0.8 mm; and the first area and the second area are equal, and the first area and the second area are both 0.5-0.8 mm 2 Preferably, the first area and the second area are both 0.75 mm 2 .

[0050] See also Figure 2 As shown, in another embodiment of the present application, at least one of the connecting portions is connected to the carrying portion 810 .

[0051] In this embodiment, the disclosure of at least one connection portion connected to the carrier portion 810 means that the connection portion can be connected to the wafer 400 on the carrier portion 810 in an appropriate number according to the usage scenario. For example, see Figure 2As shown, when the number of connecting parts is six, there are three connecting parts close to the long side 830, and the second connecting part 920 in the middle is directly connected to the carrier part 810, which is beneficial to reducing the volume of the package, reducing signal delay, and improving the reliability of the chip. Those skilled in the art can select the appropriate number of connecting parts to connect the wafer 400 according to actual needs. Figure 3 As shown, the second connecting portion 920 in the middle and the fifth connecting portion 950 opposite to the second connecting portion 920 are both directly connected to the bearing portion 810, which is conducive to forming a symmetrical relationship, facilitating wiring and achieving an aesthetic effect.

[0052] See also Figure 3 As shown, in another embodiment of the present application, six connecting portions are provided, and the six connecting portions are arranged in two groups opposite to each other along the width direction of the supporting portion 810 .

[0053] Specifically, the present embodiment discloses that the number of connecting parts is six, and the six connecting parts are divided into two groups, with three in each group, which are relatively arranged along the width direction of the supporting part 810, and the corresponding number of pins 300 is also six. By setting six connecting parts and six pins 300, the manufacturing difficulty of the package body is moderate, which is conducive to reducing costs.

[0054] The present application also provides a packaging device, comprising a packaging body as described in any one of the above technical solutions, and a packaging chip arranged on the packaging body.

[0055] The present invention provides a packaging device that has all the above beneficial effects because it is provided with the packaging body described in any of the above technical solutions. No further details will be given here. It can be understood that the packaged chip refers to the ESOT23-6 chip.

[0056] In summary, the present invention provides a package body and a packaging device thereof. By arranging a heat sink under the base island, the wafer directly conducts heat to the heat sink through the base island, and then is attached to the circuit board through the heat sink, so that the wafer can be effectively dissipated heat through the heat sink. The structure is simple and easy to produce. By changing the area of the connection part on the lead frame, the chip can have more circuits, the resistance generated is also smaller, the heat generation is reduced, and it is beneficial to improve the stability of the chip.

[0057] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, they can make improvements or changes based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A package, characterized in that: The package body includes a packaging shell, a wafer, a base island, a plurality of pins and a heat sink, wherein the wafer and the base island are sequentially arranged in the packaging shell from top to bottom, the heat sink is arranged on the side of the base island away from the wafer, and the heat sink is used to be attached to a circuit board, and the plurality of pins are relatively arranged on both sides of the packaging shell and connected to the wafer; the package body also includes a lead frame arranged in the packaging shell, a supporting portion for supporting the base island is provided in the middle position of the lead frame, and a plurality of connecting portions are arranged around the supporting portion, and the plurality of connecting portions are arranged in two groups relatively along the width direction of the lead frame, and the connecting portions protrude from the lead frame arrangement and are used to connect the pins, wherein the lead frame includes two parallel opposite long sides and two parallel opposite wide sides, the connecting portion close to one of the wide sides protrudes from the lead frame arrangement, and the protruding portion is a first area, and the connecting portion close to the other wide side protrudes from the lead frame arrangement, and the protruding portion is a second area.

2. The package according to claim 1, wherein: The heat dissipation element is a solder pad.

3. The package according to claim 2, wherein: The shape of the pad is circular or rectangular.

4. The package according to claim 1, wherein: A thermal conductive adhesive layer is provided between the wafer and the base island.

5. The package according to claim 1, wherein: The first area and the second area are equal.

6. The package according to claim 1, wherein: The first area is 0.5-0.8 mm 2 , the second area is 0.5-0.8mm 2 .

7. The package according to claim 1, wherein: At least one of the connecting portions is connected to the carrying portion.

8. The package according to claim 1, wherein: There are six connecting portions, and the six connecting portions are divided into two groups and arranged opposite to each other along the width direction of the lead frame.

9. A packaging device, characterized in that: The invention comprises a package body as claimed in any one of claims 1 to 8, and a packaged chip arranged on the package body.

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