Power supply self-protection circuit
Through the combination of PMOS switch tube and detection circuit, the protection problem of load overcurrent or short circuit in low-voltage DC circuit is solved, and the power protection of fast response and self-recovery is achieved, which improves the safety and reliability of the system.
Patent Information
- Application Number
- CN202422512708.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-17
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2034-10-17
AI Technical Summary
When the load current in low-voltage DC circuit is too large or short-circuited, there is a lack of an effective protection mechanism, which may lead to damage to the power module and safety risks.
The PMOS switch tube and detection circuit are adopted to achieve self-protection of the power supply through a self-locking circuit composed of a current sense resistor and transistor, and quickly respond and cut off the power supply in case of a fault.
It realizes fast-responsive power protection, reduces design costs, improves system reliability and availability, and avoids power module damage and safety risks.
Smart Images
Figure CN223246273U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power supply short circuit self-protection, in particular to a power supply self-protection circuit. Background Art
[0002] Frequent fault conditions encountered in low-voltage DC circuit applications include excessive load current (overcurrent) and abnormal circuit connection (short circuit). If the power module lacks effective protection mechanisms when these fault conditions occur, not only will the power module be damaged almost instantly, but they may also lead to serious safety risks, such as electrical fires, posing immeasurable threats to personal safety and property. Utility Model Content
[0003] The purpose of this utility model is to provide a power supply self-protection circuit to solve the above technical problems.
[0004] To achieve the above-mentioned purpose, the utility model provides a power supply self-protection circuit, including a PMOS switch tube connected in series to a power supply circuit and used to control the on and off of the power supply, a current-sensing resistor is connected in series between the source of the PMOS switch tube and the positive electrode of the power supply, the drain of the PMOS switch tube is connected to the positive electrode of the load, the gate of the PMOS switch tube is connected to a self-locking circuit, and the self-locking circuit is connected to a detection circuit connected in parallel to both ends of the current-sensing resistor.
[0005] Preferably, the detection circuit includes a first PNP transistor, the emitter and base of the first PNP transistor are respectively connected to the two ends of the current detection resistor, and the collector of the first PNP transistor is respectively electrically connected to the gate of the PMOS switch tube and the self-locking circuit.
[0006] Preferably, the self-locking circuit includes a second PNP transistor and an NPN transistor, the emitter of the second PNP transistor is connected between the emitter of the first PNP transistor and the current-sense resistor, the collector of the second PNP transistor is connected between the collector of the first PNP transistor and the gate of the PMOS switch tube, the base of the second PNP transistor is connected to the collector of the NPN transistor, the emitter of the NPN transistor and the base of the NPN transistor are connected to both ends of a first voltage-dividing resistor, the first voltage-dividing resistor is grounded, the first voltage-dividing resistor is connected in series with the second voltage-dividing resistor, then connected in parallel with the third voltage-dividing resistor, and then connected in series with the fourth voltage-dividing resistor, and the fourth voltage-dividing resistor is connected between the current-sense resistor and the source of the PMOS switch tube;
[0007] The collector of the first PNP transistor is also connected between the second voltage-dividing resistor and the fourth voltage-dividing resistor.
[0008] Preferably, under normal working conditions, the voltage across the fourth voltage-dividing resistor is greater than the turn-on voltage of the PMOS switch tube. At this time, the PMOS switch tube is turned on, and the voltage across the first voltage-dividing resistor is less than the turn-on voltage of the NPN transistor. The NPN transistor operates in the cut-off region.
[0009] Preferably, a bias resistor is further connected between the emitter and the base of the second PNP transistor.
[0010] Preferably, the first voltage-dividing resistor is further connected in parallel with the filter capacitor.
[0011] A current limiting resistor is further connected between the base of the second PNP transistor and the collector of the NPN transistor.
[0012] Therefore, the beneficial effects of the present invention are:
[0013] Simple hardware implementation: Only basic semiconductor components are used, and no software control is required, which simplifies the design and reduces costs.
[0014] Fast response: The full hardware design ensures immediate response when overcurrent or short circuit occurs, quickly cutting off the power supply to protect system safety.
[0015] Self-recovery function: Once the fault is eliminated, the circuit can resume normal operation after power is restored, improving the availability and stability of the system.
[0016] The power supply can achieve self-protection through hardware design without relying on a microcontroller (MCU) for control, which improves response speed and reliability.
[0017] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 The utility model is a circuit principle diagram of a power supply self-protection circuit. DETAILED DESCRIPTION
[0019] In the description of the present utility model, it should be noted that the terms "upper", "lower", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or the orientations or positional relationships in which the utility model product is usually placed when in use. They are only for the convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In the description of the present utility model, it should also be noted that, unless otherwise clearly specified and limited, the terms "setting", "installation" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be a communication between the internal parts of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0020] The following describes the embodiments of the present invention in detail with reference to the accompanying drawings.
[0021] like Figure 1 As shown, a power supply self-protection circuit includes a PMOS switch tube Q1 connected in series to a power supply circuit and used to control the power supply on and off. A current-sense resistor R1 is connected in series between the source S of the PMOS switch tube Q1 and the positive electrode of the power supply. The drain D of the PMOS switch tube Q1 is connected to the positive electrode of the load. The gate G of the PMOS switch tube Q1 is connected to a self-locking circuit, and the self-locking circuit is connected to a detection circuit connected in parallel to both ends of the current-sense resistor R1.
[0022] The detection circuit includes a first PNP transistor Q2, the emitter E and base B of the first PNP transistor Q2 are respectively connected to the two ends of the current detection resistor R1, and the collector C of the first PNP transistor Q2 is respectively electrically connected to the gate G of the PMOS switch tube Q1 and the self-locking circuit.
[0023] The self-locking circuit includes a second PNP transistor Q3 and an NPN transistor Q4. The emitter E of the second PNP transistor Q3 is connected between the emitter E of the first PNP transistor Q2 and the current-sense resistor R1. The collector C of the second PNP transistor Q3 is connected between the collector C of the first PNP transistor Q2 and the gate G of the PMOS switch tube Q1. The base B of the second PNP transistor Q3 is connected to the collector C of the NPN transistor Q4. The emitter E and the base B of the NPN transistor Q4 are connected to both ends of a first voltage-dividing resistor R7. The first voltage-dividing resistor R7 is grounded. The first voltage-dividing resistor R7 is connected in series with the second voltage-dividing resistor R3, then in parallel with the third voltage-dividing resistor R4, and then in series with the fourth voltage-dividing resistor R2. The fourth voltage-dividing resistor R2 is connected between the current-sense resistor R1 and the source S of the PMOS switch Q1. The collector C of the first PNP transistor Q2 is also connected between the second voltage-dividing resistor R3 and the fourth voltage-dividing resistor R2.
[0024] Under normal working conditions, the voltage across the fourth voltage-dividing resistor R2 is greater than the turn-on voltage of the PMOS Q1 switch tube. At this time, the PMOS switch tube Q1 is turned on, and the voltage across the first voltage-dividing resistor R7 is less than the turn-on voltage of the NPN transistor Q4. The NPN transistor Q4 operates in the cut-off region.
[0025] A bias resistor R5 is further connected between the emitter E and the base B of the second PNP transistor Q3 to prevent abnormal operation of the second PNP transistor Q3.
[0026] The first voltage-dividing resistor R7 is also connected in parallel with the filter capacitor C1 to suppress instantaneous surges.
[0027] A current limiting resistor R6 is further connected between the base of the second PNP transistor Q3 and the collector of the NPN transistor Q4.
[0028] Working principle:
[0029] During normal operation, the first and second voltage-dividing resistors R7 and R3 are connected in series, in parallel with the third and fourth voltage-dividing resistors R4, and then in series with the fourth voltage-dividing resistor R2. This ensures that the voltage difference between the gate G (voltage at point P2) and source S (voltage at point P1) of the PMOS switch Q1 exceeds the turn-on voltage of the PMOS switch Q1. This causes the PMOS switch Q1 to conduct and output voltage. At this point, the voltage at the base B of the NPN transistor Q4 (voltage at point P3) is lower than its turn-on voltage due to the voltage divided by the first and second voltage-dividing resistors R7 and R3, deactivating the self-locking circuit. During this period, the filter capacitor C1 smoothes input voltage fluctuations, preventing malfunctions caused by transient surges. The voltage difference across the current-sense resistor R1 is lower than the turn-on voltage of the first PNP transistor Q2, deactivating the first PNP transistor Q2.
[0030] When an overcurrent or short circuit occurs: the voltage difference across the current-sense resistor R1 is greater than the start-up voltage of the first PNP transistor Q2, causing the first PNP transistor Q2 to turn on and increase the voltage at point P2. When the voltage difference between the voltage at point P2 and point P1 is less than the turn-on voltage of the PMOS switch Q1, the PMOS switch Q1 is turned off and stops outputting voltage. At the same time, the voltage at point P3 increases with the voltage at point P2 until the voltage at point P3 is greater than the turn-on voltage of the NPN transistor Q4. The NPN transistor Q4 turns on and then drives the second PNP transistor Q3 to turn on, maintaining the voltage at point P2. This achieves self-locking and keeps the PMOS switch Q1 in the off state until the power is restarted.
[0031] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.
Claims
1. A power supply self-protection circuit, characterized in that: It includes a PMOS switch tube connected in series to a power supply circuit and used to control the on and off of the power supply. A current-sense resistor is connected in series between the source of the PMOS switch tube and the positive electrode of the power supply. The drain of the PMOS switch tube is connected to the positive electrode of the load. The gate of the PMOS switch tube is connected to a self-locking circuit. The self-locking circuit is connected to a detection circuit connected in parallel to both ends of the current-sense resistor.
2. A power supply self-protection circuit according to claim 1, characterized in that: The detection circuit includes a first PNP transistor, the emitter and base of the first PNP transistor are respectively connected to the two ends of the current detection resistor, and the collector of the first PNP transistor is respectively electrically connected to the gate of the PMOS switch tube and the self-locking circuit.
3. A power supply self-protection circuit according to claim 2, characterized in that: The self-locking circuit includes a second PNP transistor and an NPN transistor, the emitter of the second PNP transistor is connected between the emitter of the first PNP transistor and a current-sense resistor, the collector of the second PNP transistor is connected between the collector of the first PNP transistor and a gate of the PMOS switch tube, the base of the second PNP transistor is connected to the collector of the NPN transistor, the emitter of the NPN transistor and the base of the NPN transistor are connected to both ends of a first voltage-dividing resistor, the first voltage-dividing resistor is grounded, the first voltage-dividing resistor is connected in series with the second voltage-dividing resistor, then connected in parallel with a third voltage-dividing resistor, and then connected in series with a fourth voltage-dividing resistor, and the fourth voltage-dividing resistor is connected between the current-sense resistor and the source of the PMOS switch tube; The collector of the first PNP transistor is also connected between the second voltage-dividing resistor and the fourth voltage-dividing resistor.
4. A power supply self-protection circuit according to claim 3, characterized in that: Under normal working conditions, the voltage across the fourth voltage-dividing resistor is greater than the turn-on voltage of the PMOS switch tube. At this time, the PMOS switch tube is turned on, and the voltage across the first voltage-dividing resistor is less than the turn-on voltage of the NPN transistor. The NPN transistor operates in the cut-off region.
5. The power supply self-protection circuit according to claim 3, characterized in that: A bias resistor is further connected between the emitter and the base of the second PNP transistor.
6. A power supply self-protection circuit according to claim 3, characterized in that: The first voltage-dividing resistor is also connected in parallel with the filter capacitor.
7. The power supply self-protection circuit according to claim 3, characterized in that: A current limiting resistor is further connected between the base of the second PNP transistor and the collector of the NPN transistor.