Package structure

Abstract

The utility model discloses a packaging structure, and belongs to the technical field of semiconductors, the packaging structure comprises an electronic component and a first shielding layer covering the electronic component, the first shielding layer comprises an upper cover part located above the electronic component, and a first side wall is continuous with the upper cover part; the second side wall is adjacent to the first side wall, and a first gap exists between the second side wall and the first side wall. According to the utility model, the electronic component is covered by the first shielding layer which is provided with the upper cover part located above the electronic component, the first side wall and the second side wall, so that the electronic component is at least shielded; a buffer space is provided at least for expansion and contraction of the first shielding layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a packaging structure. Background Art

[0002] Regarding the development of System in a Package (SiP) for magnetoresistive random access memory (MRAM), it is known that magnetoresistive random access memory is highly sensitive to magnetic fields and is easily affected by magnetic fields, which in turn affects the reading and writing speeds. Currently, there is no better magnetic shielding design for SiP products. Figure 1 As shown in the figure, for the magnetic field lines between two adjacent magnetic poles of two magnets, the magnetic field lines are from the north pole (N pole) of one magnet to the south pole (S pole) of the other magnet. Figure 2 A cross-sectional view of a conventional packaging structure 100 is shown. In conventional magnetic shielding solutions, a packaging layer 101 and a lower shielding layer 102 are typically used to completely encapsulate a magnetoresistive random access memory chip 103 located therebetween. An upper shielding layer 104 is located above the magnetoresistive random access memory 103, specifically, above the packaging layer 101. Such upper shielding layer 104 and lower shielding layer 102 constitute a two-sided magnetic shielding solution that shields the magnetoresistive random access memory chip 103 located therebetween.

[0003] When this package structure is placed in a similar Figure 1 When the magnetic lines of force between the two magnets shown are Figure 2 When the packaging structure 100 of the current two-sided magnetic shielding solution shown in the figure faces a horizontal magnetic source, the packaging structure 100 is set between the south pole 111 of the first magnet and the north pole 112 of the second magnet, and the three are horizontal to each other. The magnetic field lines are from the north pole 112 of the second magnet to the south pole 111 of the first magnet, wherein the magnetic field lines pass through the first shielding layer 104 and the second shielding layer 102. Since the first shielding layer 104 and the second shielding layer 102 are composed of ferromagnetic materials, the magnetic field is conducted along with the materials to achieve the effect of magnetic shielding. However, as Figure 3 When the packaging structure 100 of the current two-sided magnetic shielding scheme faces a vertical magnetic source, the packaging structure 100 is arranged between the south pole 111 of the first magnet and the north pole 112 of the second magnet, and the three are located on a vertical straight line. The magnetic field lines run from the north pole 112 of the second magnet to the south pole 111 of the first magnet. In this case, due to the lack of a vertical channel, the magnetic force is not conducted, and most of the magnetic force will directly pass through the magnetoresistive random access memory 103, so that the magnetoresistive random access memory 103 will be affected to a greater extent than when it is under a horizontal magnetic source. Figure 4This is a three-dimensional view of a packaging structure 100 of the current two-sided magnetic shielding solution. The packaging layer 101 encapsulates the magnetoresistive random access memory 103, and the first shielding layer 104 is located on the packaging layer 101. Figure 5 It shows how Figure 2 and Figure 3 The figure shows the interior and exterior appearance of the package structure 100 of the current two-sided magnetic shielding solution (a top view of the interior and bottom of the package layer, i.e., a top view directly above the MRAM 103, ignoring the structure above the MRAM 103). The second shielding layer 102 is located on the substrate 105, the MRAM 103 is located on the second shielding layer 102, and the multiple rows of pads 106 provided on the MRAM 103 and the multiple rows of pads 107 provided on the substrate 105 are connected by leads 108. For the vertical magnetic sources provided on the upper and lower sides of the MRAM chip, the current two-sided magnetic shielding solution lacks a magnetic conduction channel. At the same time, the shielding layer also has the problem of insufficient expansion and contraction buffer space. Utility Model Content

[0004] In response to the above problems, the present application proposes a packaging structure that provides a buffer space for the expansion and contraction of the first shielding layer, at least when the electronic components are shielded.

[0005] The technical solution of this application is achieved as follows:

[0006] According to one aspect of the present application, a packaging structure is provided, which includes: an electronic component; a first shielding layer covering the electronic component, the first shielding layer including: an upper cover portion located above the electronic component; a first side wall, which is continuous with the upper cover portion; and a second side wall, which is adjacent to the first side wall, wherein a first gap exists between the second side wall and the first side wall.

[0007] In some embodiments, at least one of the first side wall and the second side wall is an inverted trapezoidal piece that gradually narrows away from the upper cover portion.

[0008] In some embodiments, the packaging structure also includes a second shielding layer located below the electronic component opposite to the upper cover portion, and the first shielding layer and the second shielding layer are together constructed to have a cavity for accommodating the electronic component, wherein the first shielding layer has two opposite first side walls and two opposite second side walls to constitute the peripheral side wall of the cavity, wherein the second shielding layer constitutes the bottom wall of the cavity and the upper cover portion constitutes the top wall of the cavity.

[0009] In some embodiments, in a cross section perpendicular to the top surface of the electronic component and two opposite first side walls, the cavity is an inverted trapezoid that is wide at the top and narrow at the bottom, the upper cover is the wide part of the inverted trapezoid, and the second shielding layer is the narrow part of the inverted trapezoid.

[0010] In some embodiments, a packaging layer for packaging the electronic component is further provided between the electronic component and the first shielding layer. In a cross section, a width of the upper cover portion is greater than a width of the packaging layer.

[0011] In some embodiments, the first slit has a uniform width along a direction away from the upper cover portion.

[0012] In some embodiments, there are two first gaps between the first sidewall and the two second sidewalls. The two first gaps are respectively located on two opposite sides of the first sidewall, and the widths of the two first gaps are the same.

[0013] In some embodiments, the first sidewall is spaced apart from a sidewall of the encapsulation layer to form a second gap, and the second gap gradually narrows in a direction away from the upper cover portion.

[0014] In some embodiments, the first gap gradually widens in a direction away from the upper cover portion.

[0015] In some embodiments, an encapsulation layer for encapsulating the electronic component is provided between the electronic component and the first shielding layer, and a portion of the first side wall or a portion of the second side wall does not contact a side wall of the encapsulation layer.

[0016] In some embodiments, the packaging structure also includes: a substrate having pads for electrical connection to electronic components; and a second shielding layer covering an area of ​​the substrate outside the pads, wherein the electronic components are located on the area of ​​the second shielding layer covering the substrate and are located below the upper cover portion.

[0017] In some embodiments, the packaging structure also includes: a substrate having a first row of solder pads and a second row of solder pads for electrically connecting to electronic components; and a second shielding layer having a first shielding area covering the substrate and located between the first row of solder pads and the second row of solder pads, and a plurality of strip-shaped shielding areas extending from the first shielding area and spaced apart from each other, the plurality of strip-shaped shielding areas separating adjacent two solder pads in the first row of solder pads and the second row of solder pads from each other.

[0018] The beneficial effects of the above technical solution include at least:

[0019] The packaging structure of the present invention adopts a first shielding layer that covers the electronic components and has an upper cover portion located above the electronic components and a first side wall and a second side wall, so that at least the electronic components are shielded. By arranging a first gap between the first side wall and the second side wall of the first shielding layer, a buffer space is provided for at least the expansion and contraction of the first shielding layer.

[0020] The packaging structure includes a second shielding layer located below the electronic component opposite to the upper cover. The first shielding layer and the second shielding layer are together constructed to have a cavity for accommodating the electronic component, so that the packaging structure can conduct magnetic force along the first shielding layer and the second shielding layer for example, a horizontal or vertical magnetic source, thereby reducing the influence of the magnetic field on the electronic component, thereby improving the speed and accuracy of reading and writing the electronic component. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a schematic diagram of the magnetic lines of force between two magnets.

[0023] Figure 2 This is a cross-sectional schematic diagram of a packaging structure of an existing two-sided magnetic shielding solution facing a horizontal magnetic source.

[0024] Figure 3 This is a cross-sectional schematic diagram of a packaging structure of an existing two-sided magnetic shielding solution when facing a vertical magnetic source.

[0025] Figure 4 It is a three-dimensional view of the packaging structure of the current two-sided magnetic shielding solution.

[0026] Figure 5 This is an internal appearance photo of the packaging structure of the current two-sided magnetic shielding solution.

[0027] Figure 6 is a three-dimensional view of a package structure according to some embodiments.

[0028] Figure 7A is a schematic cross-sectional view of a package structure according to some embodiments.

[0029] Figure 7B FIG. 1 is another cross-sectional schematic diagram of a package structure according to some embodiments.

[0030] Figure 8 A cross-sectional view of a hypothetical packaging structure.

[0031] Figure 9A and 9B is a schematic cross-sectional view of a package structure under the influence of a horizontal magnetic source according to some embodiments.

[0032] Figure 10A and 10Bis a schematic cross-sectional view of a package structure under the influence of a vertical magnetic source according to some embodiments.

[0033] Figure 11 is another three-dimensional view of a package structure according to some embodiments.

[0034] Figure 12 FIG. 1 is another schematic cross-sectional view of a package structure according to some embodiments.

[0035] Figure 13 is another schematic cross-sectional view of a package structure according to some embodiments.

[0036] Figure 14A FIG. 1 is an internal exterior view of a package structure according to some embodiments.

[0037] Figure 14B FIG. 1 is another internal exterior view of a package structure according to some embodiments.

[0038] Figure 14C FIG. 2 is another internal exterior view of a package structure according to some embodiments.

[0039] Figures 15 to 20 It is a schematic cross-sectional view at multiple stages of forming a packaging structure.

[0040] Figure 20' is formed Figure 20 Schematic diagram of the process of upper shielding layer.

[0041] Figure 21 Schematic diagram of another preformed cross-shaped ferromagnetic alloy foil.

[0042] Figures 22 to 27 Schematic cross-sectional views of various stages of forming another packaging structure.

[0043] Figure 27' is formed Figure 27 The process of upper and middle shielding layers.

[0044] Figure 28 It is another cross-sectional schematic diagram of a packaging structure.

[0045] Figure 29 It is another cross-sectional schematic diagram of another packaging structure. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0047] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is merely for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0048] In addition, the embodiments and features of the embodiments in this application can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0049] In some embodiments, Figure 6 is a three-dimensional view of the package structure 10. Figure 6As shown, the package structure 10 includes a first shielding layer 61. An electronic component (not shown) is covered by the first shielding layer 61. The first shielding layer 61 has an upper cover portion 601 located above the electronic component. The first shielding layer 61 also has a first side wall 602 and a second side wall 603. The first side wall 602 and the second side wall 603 can have the same size and shape, such as a rectangle or an inverted trapezoid. When the first side wall 602 and the second side wall 603 have an inverted trapezoidal shape, the width of the first side wall 602 and the second side wall 603 gradually narrows in a direction away from the upper cover portion 601. The upper cover portion 601 is continuous with the first side wall 602 without being disconnected. The second side wall 603 can also be continuous with the upper cover portion 601 without being disconnected. The first side wall 602 is adjacent to the second side wall 603 and a first gap 620 is formed between them. The first gap 620 can have a uniform width along the direction away from the upper cover portion 601. Specifically, on a plane parallel to the upper cover portion 601, along the extension direction of the first gap 620, the distance between the first side wall 602 and the second side wall 603 is uniform. Due to the existence of the first gap 620, a buffer space is provided for the expansion of the first shielding layer 61. For example, during a thermal process, the first gap 620 provides a buffer space for the expansion of the first shielding layer 61. The first shielding layer 61 shields the electronic component. Preferably, the first shielding layer 61 can be a magnetic layer, and the electronic component can be a magnetoresistive random access memory chip. The first shielding layer 61 configured in this way can play a role in conducting the magnetic field around the electronic component, especially the magnetic field generated by the vertical magnetic sources arranged at the upper and lower ends of the electronic component. Furthermore, the first shielding layer 61 can be a ferromagnetic alloy foil, and the first shielding layer 61 can also be an integrally molded part. Before the packaging structure 10 is formed, the first shielding layer 61 is formed by attaching and pressing the integrally formed preformed cross alloy foil to the surface of the unformed packaging structure 10. The formation process of the first shielding layer 61 will be described in detail during the formation process of the packaging structure.

[0050] In some embodiments, Figure 7A 1 is a schematic cross-sectional view of the package structure 10. Figure 7A As shown, the electronic component 71 is disposed on a substrate 72 , the packaging layer 73 packages the electronic component 71 , the upper cover 601 is located above the electronic component 71 , and the two side walls of the first shielding layer 61 are located on both sides of the electronic component 71 .

[0051] In some embodiments, the package structure 10 may further include a second shielding layer 62 positioned between the electronic component 71 and the substrate 72, so as to be constructed together with the first shielding layer 61 to form a cavity for accommodating the electronic component 71. The second shielding layer 62 may be a magnetic layer, or a ferromagnetic alloy foil. Furthermore, unlike the first shielding layer 61, the second shielding layer 62 may be made of ferrosilicon. This is because ferrosilicon has a high rigidity and cannot be used in the process of attaching and pressing the first shielding layer 61 after preforming. Furthermore, the first sidewall 602 of the first shielding layer 61 may be a pair of opposing sidewalls, and the second sidewall 603 may be a pair of opposing sidewalls. In this case, further, the first shielding layer 61 has four surfaces surrounded by a pair of opposing first side walls 602 and a pair of opposing second side walls 603. A single first side wall 602 is adjacent to two second side walls 603, and each has two first slits 620. The two first slits 620 are located on opposite sides of the single first side wall 602, and the widths of the two first slits 620 are the same. It can be understood that each two adjacent surfaces of the four surfaces of the first shielding layer 61 are a first side wall 602 and a second side wall 603, respectively. The first shielding layer 61 can have four first slits 620, and the widths of the four first slits 620 can all be the same. Similar to the aforementioned description of the first slits 620 having consistent widths, the width of each of the four first slits 620 can be consistent. Figure 7A In the cross section shown, the two side walls of the first shielding layer 61 located on both sides of the electronic component 71 can be a pair of opposing first side walls 602 or a pair of opposing second side walls 603. Furthermore, the opposing pair of first side walls 602 and the opposing pair of second side walls 603 constitute the peripheral side walls of a cavity surrounding the electronic component 71, the second shielding layer 62 constitutes the bottom wall of the cavity, and the upper cover 601 constitutes the top wall of the cavity. In some embodiments, the second shielding layer 62 can also be disconnected from the first shielding layer 61 so as not to constitute a cavity, for example Figure 7B As shown in another cross-sectional schematic diagram of the package structure 10 in FIG, the second shielding layer 62 has no contact with the first shielding layer 61 .

[0052] Figure 8 A cross-sectional view of a hypothetical package structure 20 is shown. Figure 3 The problem that the packaging structure of the existing two-sided magnetic shielding scheme cannot be turned on when facing a vertical magnetic source can be solved by Figure 8 In the embodiment of the encapsulation structure 20 shown in FIG, the first shielding layer 81 and the second shielding layer 82 are arranged on the left and right sides of the magnetoresistive random access memory 83. Figure 3In the current packaging structure of the two-sided magnetic shielding scheme shown in FIG, the first shielding layer 81 and the second shielding layer 82 are not located on the upper and lower sides of the magnetoresistive random access memory 83. The magnetic field is conducted along the first shielding layer 81 and the second shielding layer 82 to achieve the effect of magnetic shielding. In actual applications, similar to Figure 1 The magnetic field shown can be set at any distance and angle relative to the electronic component. Figure 7A The first shielding layer 61 and the second shielding layer 62 of the packaging structure 10 shown in the embodiment of the present application are constructed to have a cavity for accommodating the electronic component 71, so that the packaging structure 10 can conduct the magnetic force along the shielding layer for, for example, a horizontal or vertical magnetic source, thereby meeting the high magnetic shielding requirements of the electronic component 71, thereby reducing the influence of the magnetic field on the electronic component 71, thereby improving the speed and accuracy of reading and writing of the electronic component 71.

[0053] Specifically, if Figure 9A 、 9B and Figure 10A 、 10B The figure shows a cross-sectional view of the package structure 10 under the influence of a vertical magnetic source and a horizontal magnetic source in some embodiments. Figure 9A and 9B As shown, the package structure 10 is under the influence of a horizontal magnetic source, and the magnetic field lines extend from the north pole of one magnet to the south pole of another magnet. In this case, the magnetic field is conducted along the horizontal magnetic conduction channel formed by the upper cover 601 and the second shielding layer 62, and the electronic component 71 is less affected by the horizontal magnetic force. Figure 10A and 10B As shown, the packaging structure 10 is under the influence of a vertical magnetic source, and the magnetic lines of force extend from the north pole of one magnet to the south pole of another magnet. In this case, the magnetic field is conducted along the vertical magnetic conduction channel formed by the first side wall 602 or the second side wall 603 of the first shielding layer 61, and the electronic component 71 is less affected by the vertical magnetic force.

[0054] In some embodiments, Figure 11 FIG. 1 is another three-dimensional view of the package structure 10. Figure 11 As shown, the first gap 620 gradually widens in a direction away from the upper cover portion 601 .

[0055] In some embodiments, Figure 12 FIG1 is another cross-sectional view of the package structure 10. Figure 12 As shown, there is an encapsulation layer 73 between the electronic component 71 and the first shielding layer 61, and a portion of the first side wall 602 or a portion of the second side wall 603 does not contact the side wall of the encapsulation layer 73. Preferably, the portion of the first side wall 602 or the second side wall 603 away from the substrate 72 does not contact the side wall of the encapsulation layer 73.

[0056] In some embodiments, Figure 13 FIG. 1 is another cross-sectional view of the package structure 10. Figure 13 As shown, the direction of the cross section can be perpendicular to the top surface of the electronic component 71 and the two opposite first side walls 602, and the direction of the cross section can also be perpendicular to the top surface of the electronic component 71 and the two opposite second side walls 603. Figure 13 In the embodiment, the width of the upper cover 601 is greater than the width of the encapsulation layer 73. It can be understood that the projection of the encapsulation layer 73 onto the first shielding layer 61 falls within the boundary of the first shielding layer 61. A gap may exist between the first sidewall 602 and the sidewall of the encapsulation layer 73 to form a second gap 666. The second gap 666 gradually narrows as it moves away from the upper cover 601. Alternatively, it can be understood that the distance between the first sidewall 602 and the sidewall of the encapsulation layer 73 gradually decreases as it moves away from the upper cover 601. The first sidewall 602 may not contact the sidewall of the encapsulation layer 73. A gap may also exist between the second sidewall 603 and the sidewall of the encapsulation layer 73 to form a second gap 666. The second gap 666 gradually narrows as it moves away from the upper cover 601. Alternatively, it can be understood that the distance between the second sidewall 603 and the sidewall of the encapsulation layer 73 gradually decreases as it moves away from the upper cover 601. The second sidewall 603 may not contact the sidewall of the encapsulation layer 73. Additionally, in a plane parallel to the substrate 72, the distances between a single first side wall 602 in the pair of first side walls 602 and the side wall of the encapsulation layer 73 may be the same, and the distances between a single second side wall 603 in the pair of second side walls 603 and the side wall of the encapsulation layer 73 may also be the same. Furthermore, in a cross section, the pair of opposing first side walls 602 or the pair of opposing second side walls 603, the upper cover 601, and the second shielding layer 62 may together form an inverted trapezoid. It is understood that in Figure 13 The cavity formed by the first shielding layer 61 and the second shielding layer 62 may be an inverted trapezoid that is wide at the top and narrow at the bottom, wherein the upper cover 601 is the wide portion of the inverted trapezoid and the second shielding layer 62 is the narrow portion of the inverted trapezoid.

[0057] In some embodiments, Figure 14A 1 is an internal appearance photo of the package structure 10. The internal appearance photo is a top view obtained inside the package layer 73 of the package structure 10, that is, a top view obtained by ignoring the package layer 73 on the electronic component 71 and the first shielding layer 61. Figure 14AAs shown, the substrate 72 has pads 721 for electrical connection to the electronic component 71, and the second shielding layer 62 covers the area of ​​the substrate 72 outside the pads 721. The second shielding layer 62 covers the area on the substrate 72 via through-holes provided in the second shielding layer 62. Preferably, the through-holes can be larger than the pads 721 to provide more space for the electrical connection between the pads 721 and the electronic component 71. Furthermore, the pads 721 on the substrate 72 are electrically connected to the pads 711 on the electronic component 71 via leads 722. The substrate 72 can have multiple pads 721 in multiple rows, and the electronic component 71 can also have multiple pads 711 in multiple rows. The second shielding layer 62 completely confines the electronic component 71 within the encapsulation layer 73 while providing space for the pads provided on the substrate 72. It can be understood that the electronic component 71 is located in the area of ​​the second shielding layer 62 covering the substrate 72 and is located below the upper cover 601.

[0058] In some embodiments, Figure 14B FIG1 is another internal and external view of the package structure 10. Figure 14B As shown, the substrate 72 has a first row of pads 721 and a second row of pads 721' for electrical connection to the electronic component 71, a second shielding layer 62, and a first shielding area 62A covering the substrate 72 and located between the first row of pads 721 and the second row of pads 721'. To shield the electronic component 71 while minimizing material consumption, a plurality of spaced-apart strip-shaped shielding areas 62B extend from the first shielding area 62A. The plurality of strip-shaped shielding areas 62B separate adjacent pads in the first row of pads 721 and the second row of pads 721' from each other, thus freeing up space for electrical connection between the electronic component 71 and the substrate 72.

[0059] In some embodiments, Figure 14C This is another internal and external view of the package structure 10. Figure 14C As shown, the substrate 72 has a first row of pads 721 and a second row of pads 721 ′ for electrically connecting to the electronic component 71 , and the second shielding layer 62 covers the area of ​​the substrate 72 between the first row of pads 721 and the second row of pads 721 ′.

[0060] Figures 15 to 20 1 is a schematic cross-sectional view of various stages in forming a package structure 1500 similar to, for example, package structure 10. Figure 15 As shown, the ferrosilicon or ferromagnetic alloy foil is cut into appropriate sizes and then attached to the surface of the substrate 151 with conductive glue or magnetic epoxy resin to form a lower shielding layer 152. The substrate 151 is provided with solder pads 1511, which can be multiple or in multiple rows. Preferably, the lower shielding layer 152 can have a structure similar to Figure 14AThe shape of the second shielding layer 62 in 14B or 14C leaves space for the pad 1511. Figure 16 As shown, the electronic component 161 is attached to the lower shielding layer 152. Preferably, the electronic component 161 is a magnetoresistive random access memory chip. The electronic component 161 is provided with a soldering pad 1611. The soldering pad 1611 may have multiple or multiple rows. Figure 17 As shown, the pad 1511 on the substrate 151 and the pad 1611 on the electronic component 161 are connected by wires 1711 through a wire bonding (W / B) process. Figure 18 As shown, a packaging layer 181 that wraps the electronic component 161 is formed by a molding process. It can be understood that the lower shielding layer 152 and the packaging layer 181 together define the electronic component 161. Figure 19 As shown, the sawing process makes the sidewalls of the package structure 1500 flat. Figure 20 As shown, an upper shielding layer 201 is formed. Figure 20' It is formed by pre-forming a cross-shaped ferromagnetic alloy foil Figure 20 The process of forming the upper shielding layer 201. The upper shielding layer 201 can be formed by first cutting or punching out a preformed cross-shaped ferromagnetic alloy foil 202, then attaching the preformed cross-shaped ferromagnetic alloy foil 202 to the top surface of the packaging layer 181, and performing a pressing process on the side edges of the preformed cross-shaped ferromagnetic alloy foil 202, so that the preformed cross-shaped ferromagnetic alloy foil 202 is covered on the top surface and four side surfaces of the unformed packaging structure 1500 to form the upper shielding layer 201. It can be understood that the top surface and four side walls of the obtained upper shielding layer 201 are continuous. Similar to the first shielding layer 61 of the packaging structure 20, there is a first gap between two adjacent side walls of the upper shielding layer 201. The width of the first gap can gradually increase or remain unchanged in the direction approaching the substrate 151. It can be understood that there can also be multiple first gaps, and the width of each of the multiple first gaps can be the same as each other. The sidewalls of the upper shielding layer 201 may be in full contact, partial contact, or completely non-contact with the sidewalls of the packaging layer 181. Alternatively, the upper shielding layer 201 may be formed by finally sputtering the top surface and four side surfaces of the unformed packaging structure to coat the ferromagnetic material thereon.

[0061] Figure 21 is a schematic diagram of another preformed cross-shaped ferromagnetic alloy foil 211, see Figure 21 As shown, the four protruding portions of the preformed cross-shaped ferromagnetic alloy foil 211 are all trapezoidal with gradually decreasing widths in the extending direction of the protruding portions. It is understood that the four protruding portions of the preformed cross-shaped ferromagnetic alloy foil may have different shapes.

[0062] Figures 22 to 27 2 is a schematic cross-sectional view of multiple stages of forming another package structure 2200. Similar to the formation process of package structure 1500. First, refer to Figure 22 As shown, the ferrosilicon or ferromagnetic alloy foil is cut into appropriate sizes and then attached to the surface of the substrate 221 with conductive glue or magnetic epoxy resin to form a lower shielding layer 222. The substrate 221 is provided with solder pads 2211, which can be multiple or in multiple rows. Preferably, the lower shielding layer 222 can have a structure similar to Figure 14A Or the shape of the second shielding layer 62 in 14B, leaving space for the pad 2211. Figure 23 As shown, the electronic component 231 is attached to the lower shielding layer 222. Preferably, the electronic component 231 is a magnetoresistive random access memory chip. The electronic component 231 is provided with a soldering pad 2311. The soldering pad 2311 may have multiple or multiple rows. Figure 24 As shown, the pad 2211 on the substrate 221 and the pad 2311 on the electronic component 231 are connected by wires 2411 through a wire bonding process. Figure 25 As shown, a packaging layer 251 that wraps the electronic component 231 is formed through a molding process. It can be understood that the lower shielding layer 222 and the packaging layer 251 together define the electronic component 231. Figure 26 As shown, the cutting process makes the sidewalls of the package structure 2200 flat. Figure 27 As shown, an upper shielding layer 271 is formed. Figure 27' It is formed by preforming five pieces of ferromagnetic alloy foil Figure 27 The upper shielding layer 271 is formed by first cutting or punching out a preformed five-piece ferromagnetic alloy foil 272, and then covering the preformed five-piece ferromagnetic alloy foil 272 on the top surface and four side surfaces of the unformed package structure 2200 to form the upper shielding layer 271. It can be understood that the top surface and four side walls of the obtained upper shielding layer 271 are disconnected.

[0063] Figure 28 is another cross-sectional schematic diagram of the package structure 1500, see Figure 28 As shown, Figure 28 and Figure 20 The only difference is whether the lower shielding layer 152 is coplanar with the sidewalls of the encapsulation layer 181 and the substrate 151 .

[0064] Figure 29 is another cross-sectional schematic diagram of the package structure 2200, see Figure 29 As shown, Figure 29 and Figure 27 The only difference is whether the lower shielding layer 222 is coplanar with the sidewalls of the encapsulation layer 251 and the substrate 221 .

[0065] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A packaging structure, comprising: electronic components; a first shielding layer covering the electronic component, the first shielding layer comprising: An upper cover portion, located above the electronic components; a first side wall, the first side wall being continuous with the upper cover; A second side wall is adjacent to the first side wall, wherein a first gap exists between the second side wall and the first side wall.

2. The packaging structure according to claim 1 , further comprising a second shielding layer located below the electronic component and opposite to the upper cover, wherein the first shielding layer and the second shielding layer are together configured to have a cavity for accommodating the electronic component. in, The first shielding layer has two opposite first side walls and two opposite second side walls to form the peripheral side walls of the cavity. The second shielding layer constitutes the bottom wall of the cavity, and the upper cover constitutes the top wall of the cavity.

3. The packaging structure according to claim 2, wherein: In a cross section perpendicular to the top surface of the electronic component and the two opposite first side walls, the cavity is an inverted trapezoid that is wide at the top and narrow at the bottom, the upper cover is the wide part of the inverted trapezoid, and the second shielding layer is the narrow part of the inverted trapezoid.

4. The packaging structure according to claim 3, wherein: An encapsulation layer for encapsulating the electronic component is provided between the electronic component and the first shielding layer. In the cross section, the width of the upper cover portion is greater than the width of the encapsulation layer.

5. The package structure according to claim 1, wherein: The first slit has a uniform width along a direction away from the upper cover portion. The package structure according to claim 3 , wherein: There are two first gaps between the first side wall and the two second side walls. The two first gaps are respectively located on two opposite sides of the first side wall, and the widths of the two first gaps are the same.

7. The package structure according to claim 1, wherein: The first gap gradually widens in a direction away from the upper cover portion.

8. The package structure according to claim 7, wherein: An encapsulation layer for encapsulating the electronic component is provided between the electronic component and the first shielding layer, and a portion of the first side wall or a portion of the second side wall does not contact a side wall of the encapsulation layer.

9. The package structure according to claim 1, further comprising: a substrate having pads thereon for electrically connecting to the electronic components; as well as a second shielding layer covering the area of ​​the substrate outside the pad; The electronic component is located on a region of the second shielding layer covering the substrate and is located below the upper cover.

10. The package structure according to claim 4, wherein: The first sidewall is spaced apart from the sidewall of the encapsulation layer to form a second gap, and the second gap gradually narrows in a direction away from the upper cover portion.

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