Signal acquisition circuit and vehicle

Abstract

The utility model provides a signal acquisition circuit and a vehicle, and belongs to the technical field of electronic water pumps, the circuit comprises: a first conversion unit comprising a first triode and a first power supply, the base electrode of the first triode is connected with a pulse signal output end, the emitter electrode is connected with the first power supply, and the collector electrode is grounded; the second conversion unit comprises a second triode and a second power supply, the base of the second triode is connected with the collector of the first triode, the emitter is grounded, the collector is connected with the second power supply, and the second power supply is further connected with the pulse signal acquisition port. According to the acquisition circuit provided by the utility model, through the mutual cooperation of the first triode, the first power supply, the second triode and the second power supply, the state of the pulse signal acquired by the pulse signal acquisition port can be consistent with the state of the pulse signal output by the pulse signal output end; and mistaken starting of the electronic water pump caused by interference of the low-level signal can be reduced.

Description

Technical Field

[0001] The utility model belongs to the technical field of vehicles, and in particular relates to a signal acquisition circuit and a vehicle. Background Art

[0002] The operation of an electronic water pump is usually regulated by PWM (Pulse Width Modulation) control technology. The acquisition circuit of the PNP (Positive-Negative-Positive) transistor will cause the signal state received by the MCU (Microcontroller Unit) of the electronic water pump controller to be opposite to the state of the external PWM signal. During use, this may cause logical confusion in the electronic water pump controller and affect the normal operation of the water pump.

[0003] Secondly, low-level signals are more susceptible to external harmonic interference, which may cause the MCU to misidentify the signal status, causing the electronic water pump to start incorrectly, affecting the stability and reliability of the system. Utility Model Content

[0004] In view of the above problems, embodiments of the present application provide a signal acquisition circuit and a vehicle to overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect of an embodiment of the present application, a signal acquisition circuit is provided, comprising:

[0006] The first conversion unit includes a first transistor and a first power supply, wherein the base of the first transistor is connected to the pulse signal output terminal, the emitter is connected to the first power supply, and the collector is grounded;

[0007] A second conversion unit includes a second triode and a second power supply, wherein the base of the second triode is connected to the collector of the first triode, the emitter is grounded, and the collector is connected to the second power supply, and the second power supply is also connected to the pulse signal acquisition port;

[0008] The first transistor is configured to be cut off when the pulse signal output terminal outputs a high-level signal, so as to reduce the base voltage of the second transistor and cut off the second transistor, and the second power supply is configured to output a voltage to the pulse signal acquisition port in the cut-off state, so as to increase the level signal collected by the pulse signal acquisition port;

[0009] In addition, the first transistor is configured to be turned on when the pulse signal output end outputs a low-level signal, so that the first power supply provides a voltage to the base of the second transistor to turn on the second transistor, and the second power supply is configured to be grounded when the second transistor is in the on state to pull down the level signal collected by the pulse signal acquisition port.

[0010] Furthermore, the first transistor is further configured to be turned off when there is no signal output from the pulse signal output terminal, so as to turn off the second transistor.

[0011] Furthermore, it further comprises: a first power supply unit, wherein the first power supply unit is connected in series between the pulse signal output terminal and the first conversion unit;

[0012] Wherein, the first power supply unit is configured to pull up the base voltage of the first transistor when the pulse signal output terminal outputs a high level signal, so that the first transistor is turned off;

[0013] And when the pulse signal output end outputs a low level signal, the base voltage of the first transistor is pulled down to turn on the first transistor.

[0014] Furthermore, the first power supply unit includes:

[0015] a first current limiting resistor, wherein a first end of the first current limiting resistor is connected to the pulse signal output end, and a second end of the first current limiting resistor is connected to the base of the first transistor;

[0016] a first pull-up resistor, a first end of the first pull-up resistor and a base of the first transistor;

[0017] a first diode, wherein an anode of the first diode is connected to the second end of the first pull-up resistor;

[0018] a third power supply connected to the anode of the first diode;

[0019] The third power supply is configured to output a voltage to the base of the first transistor through the first pull-up resistor when the pulse signal output terminal outputs a high-level signal, so as to pull up the base voltage of the first transistor;

[0020] Furthermore, when the pulse signal output terminal outputs a low-level signal, a voltage is output to the pulse signal output terminal through the first pull-up resistor and the first current-limiting resistor to pull down the base voltage of the first transistor.

[0021] Furthermore, it further includes a second diode and a second power supply unit; the second diode is connected in series between the pulse signal output end and the second power supply unit, and the second power supply unit is also connected to the first conversion unit;

[0022] The second diode is configured to be cut off when the pulse signal output terminal outputs a high level signal, and to be turned on when the pulse signal output terminal outputs a low level signal;

[0023] The second power supply unit is configured to, when the second diode is in a cut-off state, pull up the base voltage of the first transistor to cut off the first transistor;

[0024] Furthermore, when the second diode is in the on state, the base voltage of the first transistor is pulled down to turn on the first transistor.

[0025] Furthermore, the second power supply unit includes:

[0026] a second current limiting resistor, wherein a first end of the second current limiting resistor is connected to the anode of the second diode, and a second end of the second current limiting resistor is connected to the first conversion unit;

[0027] a second pull-up resistor, wherein a first end of the second pull-up resistor is connected to an anode of the second diode;

[0028] a fourth power supply; the fourth power supply being connected to the second end of the second pull-up resistor;

[0029] The fourth power supply is configured to output a voltage to the base of the first transistor through the second current limiting resistor and the second pull-up resistor when the second diode is in the cut-off state, so as to pull up the base voltage of the first transistor;

[0030] Furthermore, when the pulse signal output terminal outputs a low-level signal, a voltage is output to the pulse signal output terminal through the second pull-up resistor to pull down the base voltage of the first transistor.

[0031] Furthermore, the supply voltage ranges of the first power supply, the second power supply, and the fourth power supply are equal to the collection voltage range of the collection device connected to the pulse signal collection port.

[0032] Furthermore, it also includes:

[0033] a first filter capacitor, wherein a first end of the first filter capacitor is connected to the pulse signal acquisition port and a second end thereof is grounded;

[0034] and / or,

[0035] A second filter capacitor, wherein a first end of the second filter capacitor is connected to the pulse signal output end and a second end thereof is grounded.

[0036] Furthermore, it also includes: a third current limiting resistor, a third pull-up resistor, a fourth current limiting resistor and a fourth pull-up resistor; wherein,

[0037] A first end of the third current limiting resistor is grounded, a second end of the third current limiting resistor is connected to the first end of the third pull-up resistor and the collector of the first transistor, and a second end of the third pull-up resistor is connected to the base of the second transistor;

[0038] The first end of the fourth current limiting resistor is connected to the pulse signal acquisition port, the second end of the fourth current limiting resistor is connected to the first end of the fourth pull-up resistor and the collector of the second transistor, and the second end of the fourth pull-up resistor is connected to the second power supply.

[0039] According to a second aspect of the embodiments of the present application, a vehicle is provided, wherein the vehicle includes an electronic water pump, and the electronic water pump includes the signal acquisition circuit as described in the first aspect of the embodiments of the present application.

[0040] The signal acquisition circuit provided by this embodiment includes: a first conversion unit, including a first transistor and a first power supply, wherein the base of the first transistor is connected to the pulse signal output end, the emitter is connected to the first power supply, and the collector is grounded; a second conversion unit, including a second transistor and a second power supply, wherein the base of the second transistor is connected to the collector of the first transistor, the emitter is grounded, and the collector is connected to the second power supply, and the second power supply is also connected to the pulse signal acquisition port; wherein the first transistor is configured to be cut off when the pulse signal output end outputs a high-level signal, thereby reducing the base voltage of the second transistor and causing the second transistor to be cut off; and the second power supply is configured to output a voltage to the pulse signal acquisition port in the cut-off state, thereby raising the level of the signal collected by the signal acquisition port;

[0041] In addition, the first transistor is configured to be turned on when a low-level signal is output at the pulse signal output end, so that the first power supply provides a voltage to the base of the second transistor to turn on the second transistor, and the second power supply is configured to be grounded when the second transistor is turned on to pull down the level signal collected by the signal acquisition port.

[0042] The circuit formed by the first transistor and the first power supply in the first conversion unit allows the first transistor to be turned off when the external PWM signal outputs a high-level signal through the pulse signal output terminal, causing the base voltage of the second transistor to decrease, thereby also turning off the second transistor. In this way, the second power supply outputs a high-level signal to the pulse signal acquisition port, reflecting the high-level state of the external PWM signal.

[0043] Furthermore, when the external PWM signal is low, the first transistor conducts, increasing the base voltage of the second transistor, turning the second transistor on. At this point, the second power supply is grounded, causing the signal acquisition port to capture a low-level signal, reflecting the low-level state of the external PWM signal. This effectively resolves the signal state inversion issue caused by the PNP transistor acquisition circuit, ensuring that the state of the pulse signal captured by the pulse signal acquisition port is consistent with the state of the pulse signal output by the pulse signal output port.

[0044] Secondly, the voltage of the signal acquisition port is stabilized by turning on and off the second transistor and using the second power supply, rather than directly relying on the low-level signal that may be interfered with. This helps reduce external harmonic interference on the low-level signal and causes the electronic water pump to start incorrectly. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1 This is a module schematic diagram of a data acquisition circuit provided in an embodiment of the present application;

[0047] Figure 2 This is a module diagram of another acquisition circuit provided in an embodiment of the present application;

[0048] Figure 3 This is a schematic diagram of the circuit structure of an acquisition circuit provided in an embodiment of the present application;

[0049] Reference numerals:

[0050] 1-first conversion unit; 2-second conversion unit; 3-pulse signal acquisition port; 4-pulse signal output port; 5-first power supply unit; 6-second power supply unit; Q1-first transistor; Q2-second transistor; V1-first power supply; V2-second power supply; V3-third power supply; V4-fourth power supply; D1-first diode; D2-second diode; C1-first filter capacitor; C2-second filter capacitor; R1-first current limiting resistor; R2-first pull-up resistor; R3-second current limiting resistor; R4-second pull-up resistor; R5-third current limiting resistor; R6-third pull-up resistor; R7-fourth current limiting resistor; R8-fourth pull-up resistor. DETAILED DESCRIPTION

[0051] The exemplary embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings in the embodiments of the present application. Although the accompanying drawings show exemplary embodiments of the present application, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0052] Reference Figure 1 , Figure 1 This is a schematic diagram of a module of a collection circuit provided in an embodiment of the present application. Figure 1 It can be seen that the signal acquisition circuit includes:

[0053] A first conversion unit 1 includes a first transistor Q1 and a first power supply V1, wherein the base of the first transistor Q1 is connected to the pulse signal output terminal 4, the emitter is connected to the first power supply V1, and the collector is grounded; a second conversion unit 2 includes a second transistor Q2 and a second power supply V2, wherein the base of the second transistor Q2 is connected to the collector of the first transistor Q1, the emitter is grounded, and the collector is connected to the second power supply V2, and the second power supply V2 is also connected to the pulse signal acquisition port 3; wherein the first transistor Q1 is configured to be cut off when the pulse signal output terminal 4 outputs a high-level signal, so as to reduce the base voltage of the second transistor Q2 and cut off the second transistor Q2, and the second power supply V2 is configured to output a voltage to the pulse signal acquisition port 3 in the cut-off state, so as to increase the level signal collected by the pulse signal acquisition port 3;

[0054] In addition, the first transistor Q1 is configured to be turned on when the pulse signal output terminal 4 outputs a low-level signal, so that the first power supply V1 provides a voltage to the base of the second transistor Q2 to turn on the second transistor Q2, and the second power supply V2 is configured to be grounded when the second transistor Q2 is turned on to pull down the level signal collected by the pulse signal acquisition port 3.

[0055] In this embodiment, the first transistor Q1 can be a PNP transistor, the second transistor Q2 can be an NPN (Negative-Positive-Negative) transistor, and the pulse signal output terminal 4 can be a terminal for receiving an external PWM signal. The external PWM signal generator outputs a level signal to the first conversion unit 1 through the pulse signal output terminal 4. The pulse signal acquisition port 3 can be an acquisition port for an external PWM signal acquisition device (such as an electronic water pump microcontroller) to collect PWM signals. The first power supply V1 is connected to the emitter of the first transistor Q1, which can provide a stable voltage for the first transistor Q1 to ensure that the first transistor Q1 is in a cut-off state when there is no base current. The second power supply V2 is connected to the pulse signal acquisition port 3 and the second transistor Q2 respectively. When the first transistor Q1 is in the cut-off state, a stable voltage can be output to the pulse signal acquisition port 3 to maintain the pulse signal acquisition port 3 in a high level state. When the first transistor Q1 is in the on state, since the emitter of the second transistor Q2 is grounded, the voltage output by the second power supply V2 flows to the ground, so that the pulse signal acquisition port 3 maintains a low level state when the first transistor Q1 is in the on state.

[0056] Therefore, when the pulse signal output terminal 4 outputs a high-level signal, the first transistor Q1 is cut off under the combined action of the first power supply V1 and the high-level signal, so that the base of the second transistor Q2 is grounded, and the second transistor Q2 is controlled to be cut off, so that the second power supply V2 outputs a voltage to the pulse signal acquisition port 3, so that the pulse signal acquisition port 3 maintains a high level.

[0057] In addition, when the pulse signal output terminal 4 outputs a low-level signal, the first transistor Q1 is turned on under the combined action of the first power supply V1 and the low-level signal, so that the first power supply V1 provides a voltage to the base of the second transistor Q2, controlling the second transistor Q2 to be turned on, so that the voltage output by the second power supply V2 flows to the ground and cannot flow into the pulse signal acquisition port 3, so that the pulse signal acquisition port 3 maintains a low level.

[0058] In summary, through the working function of the first conversion unit 1 and the second conversion unit 2, the level signal collected by the external PWM signal acquisition device at the pulse signal acquisition port 3 can be kept consistent with the level state output by the pulse signal output terminal 4, thereby avoiding the problem of logical confusion of the electronic water pump controller.

[0059] In a specific embodiment, the first transistor Q1 is further configured to be turned off when there is no signal output from the pulse signal output terminal 4, so as to turn off the second transistor Q2.

[0060] In this embodiment, the first transistor Q1 is also configured to be cut off when there is no signal output from the pulse signal output terminal 4, so that the second transistor Q2 is cut off. Specifically, when there is no signal output from the pulse signal output terminal 4, it means that the base of the first transistor Q1 has not received sufficient voltage or current to make it turn on, but because the first power supply V1 can provide a stable voltage source for the emitter of the first transistor Q1, the base is not reversely forward biased relative to the emitter. At this time, the first transistor Q1 is cut off. Since the conduction or cutoff of the second transistor Q2 is controlled by the first transistor Q1 and is consistent with the state of the first transistor Q1, when the first transistor Q1 is cut off, the second transistor Q2 will also be cut off, thereby avoiding the situation where there is no signal output from the pulse signal output terminal 4. The pulse signal acquisition port 3 can be kept in a high level state, which helps to reduce external harmonic interference on the low-level signal and cause the electronic water pump to start incorrectly.

[0061] In a specific embodiment, referring to Figure 2 , Figure 2 This is a module diagram of another acquisition circuit provided in an embodiment of the present application; Figure 2 It can be seen that the acquisition circuit also includes: a first power supply unit 5, which is connected in series between the pulse signal output terminal 4 and the first conversion unit 1; wherein the first power supply unit 5 is configured to pull up the base voltage of the first transistor Q1 when the pulse signal output terminal 4 outputs a high-level signal, so that the first transistor Q1 is cut off; and when the pulse signal output terminal 4 outputs a low-level signal, pull down the base voltage of the first transistor Q1, so that the first transistor Q1 is turned on.

[0062] In this embodiment, a first power supply unit 5 is further included. The first power supply unit 5 is connected in series between the pulse signal output terminal 4 and the first conversion unit 1. The first power supply unit 5 can output a high-level signal at the pulse signal output terminal 4, output an appropriate voltage to the base of the first transistor Q1, pull up the base voltage of the first transistor Q1, so that the base of the first transistor Q1 is reverse biased and is in a cut-off state, and output a low-level signal at the pulse signal output terminal 4. The first power supply unit 5 outputs a voltage to the pulse signal output terminal 4, thereby pulling down the base voltage of the first transistor Q1, so that the base of the first transistor Q1 is forward biased and is in a conduction state.

[0063] In a specific embodiment, referring to Figure 3 , Figure 3 This is a schematic diagram of the circuit structure of a collection circuit provided by an embodiment of the present application. Figure 3 As can be seen from FIG, the first power supply unit 5 includes:

[0064] a first current limiting resistor R1, a first end of the first current limiting resistor R1 is connected to the pulse signal output terminal 4, and a second end is connected to the base of the first transistor Q1; a first pull-up resistor R2, a first end of the first pull-up resistor R2 is connected to the base of the first transistor Q1; a first diode D1, an anode of the first diode D1 is connected to the second end of the first pull-up resistor R2; a third power supply V3, the third power supply V3 is connected to the anode of the first diode D1; the third power supply V3 is configured to output a voltage to the base of the first transistor Q1 through the first pull-up resistor R2 when the pulse signal output terminal 4 outputs a high-level signal, so as to pull up the base voltage of the first transistor Q1; and, when the pulse signal output terminal 4 outputs a low-level signal, output a voltage to the pulse signal output terminal 4 through the first pull-up resistor R2 and the first current limiting resistor R1, so as to pull down the base voltage of the first transistor Q1.

[0065] In this embodiment, by Figure 3 The connection method of the first current limiting resistor R1, the first pull-up resistor R2, the third power supply V3 and the first diode D1 is such that when the pulse signal output terminal 4 outputs a low-level signal, the first current limiting resistor R1 can limit the current flowing through the pulse signal output terminal 4 to prevent excessive current from damaging the external PWM signal generator. The first pull-up resistor R2 can ensure that when no pulse signal is output from the pulse signal output terminal 4, the base voltage of the first transistor Q1 is pulled high. The first diode D1 can prevent the reverse current in the acquisition circuit from flowing to the third power supply V3 and damaging the third power supply V3.

[0066] Therefore, when the pulse signal output terminal 4 outputs a high-level signal, the third power supply V3 outputs a voltage to the base of the first transistor Q1 through the first pull-up resistor R2 to pull up the base voltage of the first transistor Q1; and, when the pulse signal output terminal 4 outputs a low-level signal, the third power supply V3 outputs a voltage to the pulse signal output terminal 4 through the first pull-up resistor R2 and the first current limiting resistor R1 to pull down the base voltage of the first transistor Q1.

[0067] In a specific embodiment, referring to Figure 2 The acquisition circuit also includes a second diode D2 and a second power supply unit 6; the second diode D2 is connected in series between the pulse signal output terminal 4 and the second power supply unit 6, and the second power supply unit 6 is also connected to the first conversion unit 1; the second diode D2 is configured to be cut off when the pulse signal output terminal 4 outputs a high-level signal, and to be turned on when the pulse signal output terminal 4 outputs a low-level signal; the second power supply unit 6 is configured to pull up the base voltage of the first transistor Q1 when the second diode D2 is in the cut-off state, so that the first transistor Q1 is cut off; and, when the second diode D2 is in the on state, pull down the base voltage of the first transistor Q1, so that the first transistor Q1 is turned on.

[0068] In this embodiment, the pulse signal output by the pulse signal output terminal 4 is between 0 and 13.5V, and the pulse signal collected by the external PWM signal acquisition device is between 0 and 5V. It should be noted here that the voltage range provided by the first power supply unit 5 is consistent with the voltage range of the pulse signal output by the pulse signal output terminal 4, that is, between 0 and 13.5V.

[0069] Therefore, in order to keep the voltage range of the pulse signal output by the pulse signal output terminal 4 consistent with the voltage range of the pulse signal collected by the external PWM signal acquisition device, the acquisition circuit may further include a second diode D2 and a second power supply unit 6. Through the second diode D2, when the pulse signal output terminal 4 outputs a high-level signal, it is cut off, and then the second power supply unit 6 replaces the first power supply unit 5 to output an appropriate voltage, output an appropriate voltage to the base of the first transistor Q1, and pull up the base voltage of the first transistor Q1, so that the base of the first transistor Q1 is reverse biased and is in a cut-off state.

[0070] And through the second diode D2, it is turned on when the pulse signal output terminal 4 outputs a low level signal, and the second power supply unit 6 outputs a voltage to the pulse signal output terminal 4, thereby pulling down the base voltage of the first transistor Q1, so that the base of the first transistor Q1 is forward biased and is in a conductive state.

[0071] In a specific embodiment, referring to Figure 3 , the second power supply unit 6 includes:

[0072] a second current limiting resistor R3, a first end of the second current limiting resistor R3 is connected to the anode of the second diode D2, and a second end is connected to the first conversion unit 1; a second pull-up resistor R4, a first end of the second pull-up resistor R4 is connected to the anode of the second diode D2; a fourth power supply V4; the fourth power supply V4 is connected to the second end of the second pull-up resistor R4; the fourth power supply V4 is configured to output a voltage to the base of the first transistor Q1 through the second current limiting resistor R3 and the second pull-up resistor R4 when the second diode D2 is in the cut-off state, so as to pull up the base voltage of the first transistor Q1; and, when the pulse signal output terminal 4 outputs a low-level signal, output a voltage to the pulse signal output terminal 4 through the second pull-up resistor R4 to pull down the base voltage of the first transistor Q1.

[0073] In this embodiment, by Figure 3The connection mode of the second current-limiting resistor R3, the second pull-up resistor R4, the fourth power supply V4, and the second diode D2 is such that a high-level signal is output at the pulse signal output terminal 4. The second diode D2 can limit the passage of the high-level signal and also limit the passage of the voltage output by the third power supply V3. Only the fourth power supply V4 outputs a voltage to the base of the first transistor Q1 through the second pull-up resistor R4 and the second current-limiting resistor R3, thereby raising the base voltage of the first transistor Q1. At the same time, the current flowing through the base of the first transistor Q1 is also limited by the second resistor to prevent excessive current from damaging the first transistor Q1.

[0074] When the pulse signal output terminal 4 outputs a low level signal, the second diode D2 is turned on, and the fourth power supply V4 can output a voltage to the pulse signal output terminal 4 through the second pull-up resistor R4 to pull down the base voltage of the first transistor Q1.

[0075] In a specific embodiment, the supply voltage ranges of the first power supply V1 , the second power supply V2 and the fourth power supply V4 are equal to the collection voltage range of the collection device connected to the pulse signal collection port.

[0076] In this embodiment, the acquisition device connected to the pulse signal acquisition port can be an external PWM signal acquisition device. To ensure signal consistency or matching, the supply voltage range of the first power supply V1, the second power supply V2, and the fourth power supply V4 is equal to the acquisition voltage range. The acquisition voltage range refers to the operating voltage range of the acquisition circuit in the acquisition device used to receive and process pulse signals. For example, assuming that the acquisition circuit in the acquisition device that performs pulse signal acquisition is an MCU, but the MCU's operating voltage range is between 0 and 5V, in order to cooperate with the MCU and ensure that the final acquired pulse signal is adapted to the MCU's operating voltage range, the supply voltage range of the first power supply V1, the second power supply V2, and the fourth power supply V4 is 0 to 5V.

[0077] In a specific embodiment, the acquisition circuit further includes:

[0078] A first filter capacitor C1, a first end of the first filter capacitor C1 is connected to the pulse signal acquisition port 3 and a second end is grounded; and / or a second filter capacitor C2, a first end of the second filter capacitor C2 is connected to the pulse signal output terminal 4 and a second end is grounded.

[0079] In this embodiment, referring to Figure 3The acquisition circuit may further include a first filter capacitor C1 or a second filter capacitor C2, or both the first filter capacitor C1 and the second filter capacitor C2. By connecting the first end of the first filter capacitor C1 to the pulse signal acquisition port 3 and the second end to ground, noise in the level signal output by the pulse signal acquisition port 3 to the external PWM signal acquisition device can be filtered out. By connecting the first end of the second filter capacitor C2 to the pulse signal output terminal 4 and the second end to ground, noise in the level signal output by the external PWM signal generator to the pulse signal generator can be filtered out by the second filter capacitor C2.

[0080] In a specific embodiment, referring to Figure 3 , the acquisition circuit further includes: a third current limiting resistor R5, a third pull-up resistor R6, a fourth current limiting resistor R7 and a fourth pull-up resistor R8; wherein,

[0081] A first end of the third current limiting resistor R5 is grounded, a second end of the third current limiting resistor R5 is connected to a first end of the third pull-up resistor R6 and the collector of the first transistor Q1, and a second end of the third pull-up resistor R6 is connected to the base of the second transistor Q2; a first end of the fourth current limiting resistor R7 is connected to the pulse signal acquisition port 3, a second end of the fourth current limiting resistor R7 is connected to a first end of the fourth pull-up resistor R8 and the collector of the second transistor Q2, and a second end of the fourth pull-up resistor R8 is connected to the second power supply V2.

[0082] In this embodiment, by Figure 3 When the third current-limiting resistor R5, the third pull-up resistor R6, the fourth current-limiting resistor R7, and the fourth pull-up resistor R8 are connected, the third current-limiting resistor R5 can provide a voltage divider between the collector of the first transistor Q1 and ground to protect the collector of the first transistor Q1. The third pull-up resistor R6 can pull the base of the second transistor Q2 to a high level, ensuring that the transistor is in a predetermined off or on state. The fourth current-limiting resistor R7 prevents the large current input through the pulse signal acquisition port 3 from damaging the second transistor Q2. A stable voltage is provided between the pulse signal acquisition port 3 and the transistor collector. The fourth pull-up resistor R8 can pull the collector of the second transistor Q2 to a high level, ensuring that the transistor is in a cut-off state when there is no input signal, thereby allowing the second power supply V2 to maintain the high level state of the pulse signal acquisition port 3.

[0083] An embodiment of the present application further provides a vehicle, the vehicle including an electronic water pump, and the electronic water pump including the signal acquisition circuit of the embodiment of the present application.

[0084] For example, the following will be combined with Figure 3 , the acquisition circuit provided by this application is applied to the electronic water pump on the vehicle, and the signal status of the electronic water pump is collected during the operation of the electronic water pump.

[0085] When the external PWM signal generator outputs a high-level signal through pulse signal output terminal 4, the voltage output by the third power supply V3 is blocked by the second diode D2. Therefore, the voltage is output to the base of the first transistor Q1 through the fourth power supply V4. At this time, the first transistor Q1 is in the off state, pulling down the base voltage of the second diode D2, thereby turning off the second diode D2. The second power supply V2 then outputs a voltage to the pulse signal acquisition port 3 through the fourth pull-up resistor R8 and the fourth current-limiting resistor R7, maintaining the pulse signal acquisition port 3 at a high level, consistent with the level signal state output by the pulse signal output terminal 4. The voltage range of the third power supply V3 is 0 to 13.5V, which is different from the voltage range of the fourth power supply V4.

[0086] When the external PWM signal generator outputs a low-level signal through the pulse signal output terminal 4, the voltage output by the fourth power supply V4 is turned on by the second diode D2, thereby pulling down the base voltage of the first transistor Q1. At this time, the first transistor Q1 is in the on state, pulling up the base voltage of the second diode D2 to turn on the second diode D2, and then the voltage output by the second power supply V2 flows to the ground through the fourth pull-up resistor R8 and the second transistor Q2 in sequence, so that the pulse signal acquisition port 3 maintains a low-level state, which is consistent with the level signal state output by the pulse signal output terminal 4.

[0087] When the external PWM signal generator does not output a level signal through the pulse signal output terminal 4, the first power supply V1 can provide a stable voltage source for the emitter of the first transistor Q1, so that the first transistor Q1 is in a cut-off state, and the base voltage of the second diode D2 is pulled down to cut off the second diode D2, so that the pulse signal acquisition port 3 is normally in a high-level state, which can effectively solve the problem of external PWM input harmonic interference and avoid false starting of the electronic water pump.

[0088] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0089] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0090] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of additional identical elements in the process, article, or terminal device that includes the element.

[0091] The signal acquisition circuit and vehicle provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A signal acquisition circuit, characterized in that: include: The first conversion unit includes a first transistor and a first power supply, wherein the base of the first transistor is connected to the pulse signal output terminal, the emitter is connected to the first power supply, and the collector is grounded; A second conversion unit includes a second triode and a second power supply, wherein the base of the second triode is connected to the collector of the first triode, the emitter is grounded, and the collector is connected to the second power supply, and the second power supply is also connected to the pulse signal acquisition port; The first transistor is configured to be cut off when the pulse signal output terminal outputs a high-level signal, so as to reduce the base voltage of the second transistor and cut off the second transistor, and the second power supply is configured to output a voltage to the pulse signal acquisition port in the cut-off state, so as to increase the level signal collected by the pulse signal acquisition port; In addition, the first transistor is configured to be turned on when the pulse signal output end outputs a low-level signal, so that the first power supply provides a voltage to the base of the second transistor to turn on the second transistor, and the second power supply is configured to be grounded when the second transistor is in the on state to pull down the level signal collected by the pulse signal acquisition port.

2. The acquisition circuit according to claim 1, characterized in that: The first transistor is further configured to be turned off when no signal is output from the pulse signal output terminal, so as to turn off the second transistor.

3. The acquisition circuit according to claim 1, characterized in that: Also includes: a first power supply unit, the first power supply unit being connected in series between the pulse signal output terminal and the first conversion unit; Wherein, the first power supply unit is configured to pull up the base voltage of the first transistor when the pulse signal output terminal outputs a high level signal, so that the first transistor is turned off; And when the pulse signal output end outputs a low level signal, the base voltage of the first transistor is pulled down to turn on the first transistor.

4. The acquisition circuit according to claim 3, characterized in that: The first power supply unit includes: a first current limiting resistor, wherein a first end of the first current limiting resistor is connected to the pulse signal output end, and a second end of the first current limiting resistor is connected to the base of the first transistor; a first pull-up resistor, a first end of the first pull-up resistor and a base of the first transistor; a first diode, wherein an anode of the first diode is connected to the second end of the first pull-up resistor; a third power supply connected to the anode of the first diode; The third power supply is configured to output a voltage to the base of the first transistor through the first pull-up resistor when the pulse signal output terminal outputs a high-level signal, so as to pull up the base voltage of the first transistor; Furthermore, when the pulse signal output terminal outputs a low-level signal, a voltage is output to the pulse signal output terminal through the first pull-up resistor and the first current-limiting resistor to pull down the base voltage of the first transistor.

5. The acquisition circuit according to any one of claims 1 to 4, characterized in that: It also includes a second diode and a second power supply unit; the second diode is connected in series between the pulse signal output end and the second power supply unit, and the second power supply unit is also connected to the first conversion unit; The second diode is configured to be cut off when the pulse signal output terminal outputs a high level signal, and to be turned on when the pulse signal output terminal outputs a low level signal; The second power supply unit is configured to, when the second diode is in a cut-off state, pull up the base voltage of the first transistor to cut off the first transistor; Furthermore, when the second diode is in the on state, the base voltage of the first transistor is pulled down to turn on the first transistor.

6. The acquisition circuit according to claim 5, characterized in that: The second power supply unit includes: a second current limiting resistor, wherein a first end of the second current limiting resistor is connected to the anode of the second diode, and a second end of the second current limiting resistor is connected to the first conversion unit; a second pull-up resistor, wherein a first end of the second pull-up resistor is connected to an anode of the second diode; a fourth power supply; the fourth power supply being connected to the second end of the second pull-up resistor; The fourth power supply is configured to output a voltage to the base of the first transistor through the second current limiting resistor and the second pull-up resistor when the second diode is in the cut-off state, so as to pull up the base voltage of the first transistor; Furthermore, when the pulse signal output terminal outputs a low-level signal, a voltage is output to the pulse signal output terminal through the second pull-up resistor to pull down the base voltage of the first transistor.

7. The acquisition circuit according to claim 6, characterized in that: The supply voltage ranges of the first power supply, the second power supply, and the fourth power supply are equal to the collection voltage range of the collection device connected to the pulse signal collection port.

8. The signal acquisition circuit according to claim 1, characterized in that: Also includes: a first filter capacitor, wherein a first end of the first filter capacitor is connected to the pulse signal acquisition port and a second end thereof is grounded; and / or, A second filter capacitor, wherein a first end of the second filter capacitor is connected to the pulse signal output end and a second end thereof is grounded.

9. The signal acquisition circuit according to claim 1, characterized in that: Also includes: A third current limiting resistor, a third pull-up resistor, a fourth current limiting resistor and a fourth pull-up resistor; wherein, A first end of the third current limiting resistor is grounded, a second end of the third current limiting resistor is connected to the first end of the third pull-up resistor and the collector of the first transistor, and a second end of the third pull-up resistor is connected to the base of the second transistor; The first end of the fourth current limiting resistor is connected to the pulse signal acquisition port, the second end of the fourth current limiting resistor is connected to the first end of the fourth pull-up resistor and the collector of the second transistor, and the second end of the fourth pull-up resistor is connected to the second power supply.

10. A vehicle, characterized in that: The vehicle includes an electronic water pump, and the electronic water pump includes the signal acquisition circuit according to any one of claims 1 to 9.

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