Square wave generating circuit and electronic equipment

Abstract

A square wave generating circuit and an electronic device belong to the technical field of electronic circuits, and are characterized in that an input end of a first inverter is connected with a first end of a first current limiting assembly and a positive electrode of a first energy storage assembly; the output end of the first phase inverter is connected with the first end of the first current limiting assembly and the positive electrode of the second energy storage assembly. The negative electrode of the second energy storage assembly is connected with the input end of the second phase inverter and the first end of the second current limiting assembly. The negative electrode of the first energy storage assembly, the second end of the second current limiting assembly and the output end of the second phase inverter are jointly used as the output end of the square wave generation circuit so as to output a square wave signal; therefore, when stable square waves are output, the circuit is simplified and the cost is reduced.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular relates to a square wave generating circuit and an electronic device. Background Art

[0002] The relevant square wave generating circuit includes a positive phase output circuit and a negative phase output circuit, a control module and a switching circuit; wherein, the control module is connected to the signal end of the switching circuit, is used to receive a control signal, and send a first signal or a second signal to the switching circuit according to the control signal; the switching circuit, the output end of the switching circuit is connected to the input end of the positive phase output circuit and the negative phase output circuit, is used to control the output end of the positive phase output circuit to output a positive phase voltage when receiving a first signal; and control the output end of the negative phase output circuit to output a negative phase voltage when receiving a second signal; thereby generating a simple and convenient square wave voltage.

[0003] However, the above square wave generating circuit requires a logic circuit to generate high and low level control signals of a preset frequency, which results in a complex circuit and high cost.

[0004] Therefore, the related square wave generating circuit is complex and has high cost. Utility Model Content

[0005] The purpose of this application is to provide a square wave generating circuit and electronic equipment, aiming to solve the problem that the related square wave generating circuit is complex and has high cost.

[0006] An embodiment of the present application provides a square wave generating circuit, comprising a first inverter, a second inverter, a first current limiting component, a second current limiting component, a first energy storage component, and a second energy storage component;

[0007] The input end of the first inverter is connected to the first end of the first current limiting component and the positive electrode of the first energy storage component;

[0008] The output end of the first inverter is connected to the first end of the first current limiting component and the positive electrode of the second energy storage component;

[0009] The negative electrode of the second energy storage component is connected to the input end of the second inverter and the first end of the second current limiting component;

[0010] The negative electrode of the first energy storage component, the second end of the second current limiting component and the output end of the second inverter serve together as the output end of the square wave generating circuit to output a square wave signal.

[0011] In one embodiment, the first current limiting component and the second current limiting component have the same resistance value.

[0012] In one embodiment, the first energy storage component and the second energy storage component have the same capacitance.

[0013] In one embodiment, the first inverter is a first Schmitt trigger;

[0014] The input end of the first Schmitt trigger is the input end of the first inverter;

[0015] The output end of the second Schmitt trigger is the output end of the second inverter.

[0016] In one embodiment, the second inverter is a second Schmitt trigger;

[0017] The input terminal of the second Schmitt trigger is the input terminal of the second inverter;

[0018] The output end of the second Schmitt trigger is the output end of the second inverter.

[0019] In one embodiment, the first current limiting component includes a first resistor;

[0020] The first end of the first resistor is the first end of the first current limiting component;

[0021] The second end of the first resistor is the second end of the first current limiting component.

[0022] In one embodiment, the second current limiting component includes a second resistor;

[0023] The first end of the second resistor is the first end of the second current limiting component;

[0024] The second end of the second resistor is the second end of the second current limiting component.

[0025] In one embodiment, the first energy storage component includes a first capacitor;

[0026] The first end of the first capacitor is the positive electrode of the first energy storage component;

[0027] The second end of the first capacitor is the negative electrode of the first energy storage component.

[0028] In one embodiment, the second energy storage component is a second capacitor;

[0029] The first end of the second capacitor is the positive electrode of the second energy storage component;

[0030] The second end of the second capacitor is the negative electrode of the second energy storage component.

[0031] An embodiment of the present utility model further provides an electronic device, which includes the above-mentioned square wave generating circuit.

[0032] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: since the input end of the first inverter is connected to the first end of the first current limiting component and the positive electrode of the first energy storage component; the output end of the first inverter is connected to the first end of the first current limiting component and the positive electrode of the second energy storage component; the negative electrode of the second energy storage component is connected to the input end of the second inverter and the first end of the second current limiting component; the negative electrode of the first energy storage component, the second end of the second current limiting component and the output end of the second inverter jointly serve as the output end of the square wave generating circuit to output a square wave signal; therefore, while outputting a stable square wave, the circuit is simplified and the cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical utility model in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 A schematic structural diagram of a square wave generating circuit provided in one embodiment of the present application;

[0035] Figure 2 A waveform diagram of a square wave generating circuit provided in one embodiment of the present application;

[0036] Figure 3 This is an example circuit schematic diagram of a square wave generating circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0038] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0039] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0041] Figure 1 The following is a schematic diagram showing the structure of a square wave generating circuit provided in a preferred embodiment of the present application. For ease of explanation, only the parts related to this embodiment are shown, which are described in detail as follows:

[0042] The square wave generating circuit includes a first inverter 11 , a second inverter 12 , a first current limiting component 13 , a second current limiting component 14 , a first energy storage component 15 and a second energy storage component 16 .

[0043] The input end of the first inverter 11 is connected to the first end of the first current limiting component 13 and the positive electrode of the first energy storage component 15; the output end of the first inverter 11 is connected to the first end of the first current limiting component 13 and the positive electrode of the second energy storage component 16; the negative electrode of the second energy storage component 16 is connected to the input end of the second inverter 12 and the first end of the second current limiting component 14; the negative electrode of the first energy storage component 15, the second end of the second current limiting component 14 and the output end of the second inverter 12 together serve as the output end of the square wave generating circuit to output the square wave signal Vout.

[0044] Among them, the input end of the first inverter 11, the first end of the first current limiting component 13, and the positive electrode of the first energy storage component 15 are commonly connected to the first node A; the output end of the first inverter 11, the first end of the first current limiting component 13, and the positive electrode of the second energy storage component 16 are commonly connected to the second node B; the negative electrode of the second energy storage component 16 is connected to the input end of the second inverter 12 and the first end of the second current limiting component 14 and are commonly connected to the third node C; the negative electrode of the first energy storage component 15, the second end of the second current limiting component 14, and the output end of the second inverter 12 are commonly connected to the fourth node D.

[0045] It should be noted that the resistance of the current limiting component and the capacitance of the energy storage component can be set to configure the frequency of the square wave signal Vout.

[0046] In a specific implementation, the frequency of the square wave signal Vout may be 5 Hz.

[0047] The waveforms of the above nodes are as follows: Figure 2 shown.

[0048] It can be understood that when power is turned on at time T0, the first node A jumps to a low level, the output signal of the first inverter 11 jumps to a high level, the second node B jumps to a high level, the third node C jumps to a high level, the output signal of the second inverter 12 jumps to a low level, the fourth node D jumps to a low level, and the square wave generating circuit starts to output a low-level square wave signal Vout.

[0049] During the time period from T0 to T1, the voltage of the second node B charges the first energy storage component 15 through the first current limiting component 13, and the voltage of the first node A slowly rises. When the voltage of the first node A reaches the first preset voltage (such as 1.8V) at time T1, the output signal of the first inverter 11 jumps to a low level and remains at a low level. At this time, the second node B is close to 0V; at the same time, the third node C is a high level voltage and the fourth node D is discharged through the second current limiting component 14. When the voltage of the third node C drops to the second preset voltage (such as 1.8V) at time T1, the output signal of the second inverter 12 jumps to a high level and remains at a high level. At this time, the fourth node D is a high level; since the fourth node D jumps to a high level at time T1, the voltage of the first node A rises to the sum of the voltage of the fourth node D and the first preset voltage (such as 3.6V) at time T1; and since the second node B jumps to a low level at time T1, the third node C jumps from the second preset voltage (such as 1.8V) to 0V.

[0050] At time T1, the voltage of the first node A rises to the sum of the voltage of the fourth node D and the first preset voltage (such as 3.6V), the second node B jumps to a low level, the third node C jumps from the second preset voltage (such as 1.8V) to 0V, the output signal of the second inverter 12 jumps to a high level, the fourth node D jumps to a high level, and the square wave generating circuit starts to output a high-level square wave signal Vout.

[0051] During the time period from T1 to T2, the voltage of the first node A discharges the output end of the first inverter 11 (close to 0V at this time) through the first current limiting component 13. When the voltage of the first node A drops to the third preset voltage (such as 1.8V) at time T2, the output signal of the first inverter 11 jumps to a high level and maintains it. At this time, the second node B is close to 1.8V; at the same time, the high-level voltage of the fourth node D charges the second energy storage component 16 through the second current limiting component 14, so that the voltage of the third node C starts to rise from 0V and rises to the fourth preset voltage (such as 1.8V) at time T2. Therefore, at time T2, the output signal of the second inverter 12 jumps to a low level, the fourth node D jumps to a low level, and the square wave generating circuit starts to output a low-level square wave signal Vout.

[0052] It can be understood that the square wave generating circuit cyclically repeats the function of the time period from T0 to T2, thereby simplifying the circuit and reducing the cost while outputting a stable square wave.

[0053] As an example, the first current limiting component 13 and the second current limiting component 14 have the same resistance value.

[0054] By setting the first current limiting component 13 and the second current limiting component 14 with the same resistance value, the electrical parameters of the square wave signal are configured, thereby improving the stability of the square wave signal.

[0055] As an example and not a limitation, the first energy storage assembly 15 and the second energy storage assembly 16 have the same capacitance.

[0056] By setting the first energy storage component 15 and the second energy storage component 16 with the same capacitance, the electrical parameters of the square wave signal are configured, thereby improving the stability of the square wave signal.

[0057] Figure 3 A partial exemplary circuit structure of a square wave generating circuit provided by an embodiment of the present invention is shown. For ease of description, only the portion related to the embodiment of the present invention is shown, which is described in detail as follows:

[0058] The first inverter 11 is a first Schmitt trigger U1 .

[0059] An input end of the first Schmitt trigger U1 is an input end of the first inverter 11 ; an output end of the second Schmitt trigger U1 is an output end of the second inverter 12 .

[0060] The second inverter 12 is a second Schmitt trigger U2 .

[0061] An input end of the second Schmitt trigger U2 is an input end of the second inverter 12 ; an output end of the second Schmitt trigger U2 is an output end of the second inverter 12 .

[0062] It is understandable that the first Schmitt trigger U1 and the second Schmitt trigger U2 can be integrated into the same chip.

[0063] The first current limiting component 13 includes a first resistor R1 .

[0064] The first end of the first resistor R1 is the first end of the first current limiting component 13 ; the second end of the first resistor R1 is the second end of the first current limiting component 13 .

[0065] The second current limiting component 14 includes a second resistor R2 .

[0066] The first end of the second resistor R2 is the first end of the second current limiting component 14 ; the second end of the second resistor R2 is the second end of the second current limiting component 14 .

[0067] The first energy storage component 15 includes a first capacitor C1.

[0068] The first end of the first capacitor C1 is the positive electrode of the first energy storage component 15 ; the second end of the first capacitor C1 is the negative electrode of the first energy storage component 15 .

[0069] The second energy storage component 16 comprises a second capacitor C2.

[0070] The first end of the second capacitor C2 is the positive electrode of the second energy storage component 16 ; the second end of the second capacitor C2 is the negative electrode of the second energy storage component 16 .

[0071] The following is combined with the working principle Figure 3 As shown for further explanation:

[0072] Figure 3 The waveform diagrams of each node in the square wave generating circuit are shown as follows Figure 2 As shown, in Figure 2 In, V A is the voltage of the first node A, V B is the voltage of the first node B, V C is the voltage of the first node C, V D is the voltage of the first node D.

[0073] It can be understood that when power is turned on at time T0, the first node A jumps to a low level, the output signal of the first Schmitt trigger U1 jumps to a high level, the second node B jumps to a high level, the third node C jumps to a high level, the output signal of the second Schmitt trigger U2 jumps to a low level, the fourth node D jumps to a low level, and the square wave generating circuit starts to output a low-level square wave signal Vout.

[0074] During the time period from T0 to T1, the voltage of the second node B charges the first capacitor C1 through the first resistor R1, and the voltage of the first node A slowly rises. When the voltage of the first node A reaches the first preset voltage (e.g., 1.8V) at time T1, the output signal of the first Schmitt trigger U1 jumps to a low level and remains at a low level. At this time, the second node B is close to 0V. At the same time, the voltage of the third node C is a high level and discharges the fourth node D through the second resistor R2. When the voltage of the third node C drops to the second preset voltage (e.g., 1.8V) at time T1, the output signal of the second Schmitt trigger U2 jumps to a high level and remains at a high level. At this time, the fourth node D is a high level. Since the fourth node D jumps to a high level at time T1, the voltage of the first node A rises to the sum of the voltage of the fourth node D and the first preset voltage (e.g., 3.6V) at time T1. And since the second node B jumps to a low level at time T1, the third node C jumps from the second preset voltage (e.g., 1.8V) to 0V.

[0075] At time T1, the voltage of the first node A rises to the sum of the voltage of the fourth node D and the first preset voltage (such as 3.6V), the second node B jumps to a low level, the third node C jumps from the second preset voltage (such as 1.8V) to 0V, the output signal of the second Schmitt trigger U2 jumps to a high level, the fourth node D jumps to a high level, and the square wave generating circuit starts to output a high-level square wave signal Vout.

[0076] During the time period from T1 to T2, the voltage of the first node A discharges the output end of the first Schmitt trigger U1 (close to 0V at this time) through the first resistor R1. When the voltage of the first node A drops to the third preset voltage (such as 1.8V) at time T2, the output signal of the first Schmitt trigger U1 jumps to a high level and maintains it. At this time, the second node B is close to 1.8V; at the same time, the high-level voltage of the fourth node D charges the second capacitor C2 through the second resistor R2, so that the voltage of the third node C starts to rise from 0V and rises to the fourth preset voltage (such as 1.8V) at time T2. Therefore, at time T2, the output signal of the second Schmitt trigger U2 jumps to a low level, the fourth node D jumps to a low level, and the square wave generating circuit starts to output a low-level square wave signal Vout.

[0077] It can be understood that the square wave generating circuit cyclically repeats the function of the time period from T0 to T2, thereby simplifying the circuit and reducing the cost while outputting a stable square wave.

[0078] An embodiment of the present invention further provides an electronic device, which includes the above-mentioned square wave generating circuit.

[0079] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0080] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A square wave generating circuit, characterized in that: It includes a first inverter, a second inverter, a first current limiting component, a second current limiting component, a first energy storage component and a second energy storage component; The input end of the first inverter is connected to the first end of the first current limiting component and the positive electrode of the first energy storage component; The output end of the first inverter is connected to the first end of the first current limiting component and the positive electrode of the second energy storage component; The negative electrode of the second energy storage component is connected to the input end of the second inverter and the first end of the second current limiting component; The negative electrode of the first energy storage component, the second end of the second current limiting component and the output end of the second inverter serve together as the output end of the square wave generating circuit to output a square wave signal.

2. The square wave generating circuit according to claim 1, wherein: The first current limiting component and the second current limiting component have the same resistance value.

3. The square wave generating circuit according to claim 1, wherein: The first energy storage component and the second energy storage component have the same capacitance.

4. The square wave generating circuit according to claim 1, wherein: The first inverter is a first Schmitt trigger; The input end of the first Schmitt trigger is the input end of the first inverter; The output end of the first Schmitt trigger is the output end of the second inverter.

5. The square wave generating circuit according to claim 1, wherein: The second inverter is a second Schmitt trigger; The input terminal of the second Schmitt trigger is the input terminal of the second inverter; The output end of the second Schmitt trigger is the output end of the second inverter.

6. The square wave generating circuit according to claim 1, wherein: The first current limiting component includes a first resistor; The first end of the first resistor is the first end of the first current limiting component; The second end of the first resistor is the second end of the first current limiting component.

7. The square wave generating circuit according to claim 1, wherein: The second current limiting component includes a second resistor; The first end of the second resistor is the first end of the second current limiting component; The second end of the second resistor is the second end of the second current limiting component.

8. The square wave generating circuit according to claim 1, wherein: The first energy storage component includes a first capacitor; The first end of the first capacitor is the positive electrode of the first energy storage component; The second end of the first capacitor is the negative electrode of the first energy storage component.

9. The square wave generating circuit according to claim 1, wherein: the second capacitor of the second energy storage component; The first end of the second capacitor is the positive electrode of the second energy storage component; The second end of the second capacitor is the negative electrode of the second energy storage component.

10. An electronic device, characterized in that: The electronic device comprises the square wave generating circuit according to any one of claims 1 to 9.

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