Circuit for improving SPI (Serial Peripheral Interface) multi-path parallel driving capability
By introducing push-pull circuit and open-drain circuit module between the SPI master controller and the slave device, the chip selection signal capability is expanded, and the problem of insufficient driving capability of the SPI master controller is solved, thereby improving the multi-channel parallel driving capability and system simplification is achieved.
Patent Information
- Application Number
- CN202422447935.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-10
- Publication Date
- 2025-08-22
- Estimated Expiration
- 2034-10-10
AI Technical Summary
The signal driving capability of the SPI master controller is limited and cannot meet the needs of a large number of parallel-driven SPI slave devices. In addition, multiple master controllers are required to be used during multiple control, increasing system complexity.
By adding a first push-pull circuit module, a second push-pull circuit module, a first open-drain circuit module, a second open-drain circuit module and a decoder between the SPI master controller and the SPI slave device, the chip selection capability is expanded, the push-pull circuit module is used to enhance signal transmission, and the open-drain circuit module is used to avoid signal interference, and multiple parallel driving is realized.
The same SPI master controller can drive more SPI slaves, improve communication driving capabilities, reduce capacitive load, reduce dependence on the main controller pins, and simplify the system structure.
Smart Images
Figure CN223261520U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of SPI communication circuits, in particular to a circuit for improving the SPI multi-channel parallel driving capability. Background Art
[0002] The SPI (Serial Peripheral Interface) bus system is a synchronous serial peripheral interface that enables the MCU to communicate with various peripheral devices in a serial manner to exchange information.
[0003] Four lines are generally used between the SPI master controller and the SPI slave device: serial clock line (CLK), master output / slave input data line (MOSI), master input / slave output data line (MISO) and low-level active slave select line (CS).
[0004] Combine Figure 1 , a one-to-one connection between the SPI master controller and the SPI slave device. The clock signal terminal of the SPI master controller is connected to the clock signal terminal of the SPI slave device, the data signal output terminal of the SPI master controller is connected to the data signal input terminal of the SPI slave device, the data signal input terminal of the SPI master controller is connected to the data signal output terminal of the SPI slave device, and the chip select signal terminal of the SPI master controller is connected to the chip select signal terminal of the SPI slave device.
[0005] Combine Figure 2 When an SPI master controller is connected to three SPI slave devices, the SPI master controller must have three chip select signal terminals. One of the chip select signal terminals outputs a low level, while the other two output a high level. The SPI slave device that receives the low level is in the enabled state, while the SPI slave device that receives the high level is in the disabled state. The clock signal and data signal from the SPI master controller are sent directly to the three SPI slave devices via parallel lines, but the signals are easily weakened during the transmission process.
[0006] Due to the limited signal drive capability of the SPI master controller and the limited number of chip select signal terminals, when connecting more SPI slave devices, a single SPI master controller cannot meet the drive requirements, and additional SPI master controllers are needed. In summary, 1. SPI communication drive capability is limited by the SPI master controller and generally cannot meet the driving requirements for a large number of parallel lines; 2. When a single SPI master controller drives multiple SPI slave devices, the capacitive load is large, affecting the SPI communication drive capability; 3. When controlling multiple SPI slave devices, multiple SPI master controllers are required, which places high demands on the system's master controller.
[0007] Therefore, how to increase the number of SPI slave devices and improve the SPI communication driving capability by driving the SPI master controller is a technical problem that needs to be solved urgently in this field. Utility Model Content
[0008] The technical problem to be solved by the utility model is to provide a circuit for improving the SPI multi-channel parallel driving capability, which is driven by an SPI master controller, increases the number of SPI slave devices, and improves the SPI communication driving capability.
[0009] The utility model is implemented as follows: a circuit for improving the SPI multi-channel parallel driving capability, comprising:
[0010] SPI master controller, SPI slave device, first push-pull circuit module, second push-pull circuit module, decoder, first open-drain circuit module and second open-drain circuit module;
[0011] The clock signal terminal of the SPI master controller is connected to the input terminal of the first push-pull circuit module, and the output terminal of the first push-pull circuit module is connected to the clock signal terminals of the plurality of SPI slave devices;
[0012] The data signal output end of the SPI master controller is connected to the input end of the second push-pull circuit module, and the output end of the second push-pull circuit module is connected to the data signal input ends of the plurality of SPI slave devices;
[0013] The chip select signal end of the SPI master controller is connected to the input end of the decoder, and the output end of the decoder is connected to the chip select signal ends of the plurality of SPI slave devices;
[0014] The data signal output ends of the multiple SPI slave devices are respectively connected to the input ends of the multiple first open-drain circuit modules, the output ends of the multiple first open-drain circuit modules are all connected to the input end of one second open-drain circuit module, and the output end of the second open-drain circuit module is connected to the data signal input end of the SPI master controller.
[0015] Furthermore, the first open-drain circuit module and the second open-drain circuit module have the same structure, and both include an open-drain circuit module input end, an open-drain circuit module output end, an NMOS transistor, a first resistor, a second resistor, and a third resistor;
[0016] The input end of the open-drain circuit module is connected to the gate of the NMOS tube and one end of the first resistor, the source of the NMOS tube is grounded, the drain of the NMOS tube is connected to the other end of the first resistor and one end of the second resistor, the other end of the second resistor is connected to one end of the third resistor and the output end of the open-drain circuit module, and the other end of the third resistor is connected to the power supply.
[0017] Furthermore, the first push-pull circuit module and the second push-pull circuit module are both chips of model 74LVC244APW.
[0018] Furthermore, the number of output terminals of the decoder is equal to the number of the SPI slave devices, and the number of the SPI slave devices is equal to the number of the first open-drain circuit modules.
[0019] Furthermore, the decoder is a 3-8 decoder, the SPI master controller has three chip select signal terminals, the SPI slave devices have eight terminals, and the first open-drain circuit modules have eight terminals.
[0020] Furthermore, it also includes debugging indicator lights, which are connected to the output end of the decoder, and the number of the debugging indicator lights is equal to the number of the output ends of the decoder.
[0021] Furthermore, a debugging breadboard is included, and the SPI master controller, SPI slave device, first push-pull circuit module, second push-pull circuit module, decoder, first open-drain circuit module and second open-drain circuit module are all fixedly arranged on the debugging breadboard.
[0022] Furthermore, the SPI master controller is an MCU, and the SPI slave device is a user line interface circuit.
[0023] Compared with the background technology, the advantages and beneficial effects of the present invention are:
[0024] The same SPI master controller can drive a larger number of SPI slave devices. A push-pull circuit module is used to strengthen the clock signal and data signal transmitted to the SPI slave device. A decoder is used to expand the chip select capability of the SPI master controller. An open-drain circuit module is used to send the data signal output by the SPI slave device to the SPI master controller to avoid signal interference. The utility model provides a circuit for improving the SPI multi-channel parallel driving capability. The circuit is driven by the SPI master controller, increases the number of SPI slave devices, and improves the SPI communication driving capability. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0026] Figure 1 This is a schematic diagram of a one-to-one connection between an SPI master controller and an SPI slave device in the background art.
[0027] Figure 2 This is a schematic diagram of a SPI master controller connected to three SPI slave devices in the background art.
[0028] Figure 3This is a schematic diagram of a circuit for improving the SPI multi-channel parallel driving capability according to the present invention.
[0029] Figure 4 It is a schematic diagram of an open-drain circuit module in an embodiment of the present utility model.
[0030] Figure 5 It is a schematic diagram of a push-pull circuit module in an embodiment of the present utility model.
[0031] Figure 6 This is a connection diagram of the SPI master controller, 3-8 decoder and SPI slave device in the embodiment of the present utility model. DETAILED DESCRIPTION
[0032] The present invention provides a circuit for improving the SPI multi-channel parallel driving capability, overcoming the shortcomings of the prior art in which a single SPI master controller has limited signal driving capability and cannot meet the requirements of driving a large number of SPI slave devices in parallel. The invention also achieves the technical effect of increasing the number of SPI slave devices and improving the SPI communication driving capability.
[0033] The overall idea of the technical solution of the embodiment of the utility model is as follows:
[0034] A first push-pull circuit module, a second push-pull circuit module, a first open-drain circuit module, a second open-drain circuit module, and a decoder are additionally provided between the SPI master controller and the SPI slave device, so that one SPI master controller can drive a larger number of SPI slave devices. The clock signal and data signal of the SPI master controller are amplified by the push-pull circuit module and sent to multiple SPI slave devices in parallel to avoid signal attenuation and distortion. The chip select signal end of the SPI master controller is connected to the chip select signal ends of more SPI slave devices through the decoder. The data signals of multiple SPI slave devices are sent to the SPI master controller through the open-drain circuit module.
[0035] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.
[0036] See Figures 1 to 6 , a preferred embodiment of the present utility model.
[0037] A circuit for improving SPI multi-channel parallel driving capability, comprising:
[0038] SPI master controller 10, SPI slave device 20, first push-pull circuit module 30, second push-pull circuit module 40, decoder 50, first open-drain circuit module 60 and second open-drain circuit module 70;
[0039] The clock signal terminal 11 of the SPI master controller is connected to the input terminal of the first push-pull circuit module 30, and the output terminal of the first push-pull circuit module 30 is connected to the clock signal terminals 21 of the plurality of SPI slave devices;
[0040] The data signal output terminal 12 of the SPI master controller is connected to the input terminal of the second push-pull circuit module 40, and the output terminal of the second push-pull circuit module 40 is connected to the data signal input terminals 23 of the plurality of SPI slave devices;
[0041] The chip select signal terminal 14 of the SPI master controller is connected to the input terminal of the decoder 50, and the output terminal of the decoder 50 is connected to the chip select signal terminals 24 of the plurality of SPI slave devices;
[0042] The data signal output ends 22 of the multiple SPI slave devices are respectively connected to the input ends of the multiple first open-drain circuit modules 60, the output ends of the multiple first open-drain circuit modules 60 are all connected to the input end of one second open-drain circuit module 70, and the output end of the second open-drain circuit module 70 is connected to the data signal input end 13 of the SPI master controller.
[0043] The beneficial effects of the above technical solution are: the same SPI master controller 10 can drive a larger number of SPI slave devices 20, the push-pull circuit module is used to strengthen the clock signal and data signal transmitted to the SPI slave device 20, the decoder 50 is used to expand the chip select capability of the SPI master controller 10, and the open-drain circuit module is used to send the data signal output by the SPI slave device 20 to the SPI master controller 10 to avoid signal interference; the circuit of improving the SPI multi-channel parallel driving capability of the utility model is driven by the SPI master controller 10, increases the number of SPI slave devices 20, and improves the SPI communication driving capability.
[0044] The first open-drain circuit module 60 and the second open-drain circuit module 70 have the same structure, both including an open-drain circuit module input terminal 61, an open-drain circuit module output terminal 62, an NMOS transistor Q1, a first resistor R1, a second resistor R2 and a third resistor R3;
[0045] The open-drain circuit module input terminal 61 is connected to the gate of the NMOS transistor Q1 and one end of the first resistor R1. The source of the NMOS transistor Q1 is grounded GND. The drain of the NMOS transistor Q1 is connected to the other end of the first resistor R1 and one end of the second resistor R2. The other end of the second resistor R2 is connected to one end of the third resistor R3 and the open-drain circuit module output terminal 62. The other end of the third resistor R3 is connected to the power supply VDDA. The beneficial effect of this technical solution is that when the open-drain circuit module input terminal 61 is at a high level, the gate of the NMOS transistor Q1 is at a high level, and the NMOS transistor Q1 is turned on, so that the open-drain circuit module output terminal 62 is grounded and outputs a low level. When the open-drain circuit module input terminal 61 is at a low level, the gate of the NMOS transistor Q1 is at a low level, and the NMOS transistor Q1 is turned off, so that the open-drain circuit module output terminal 62 is connected to the power supply through the third resistor R3 and outputs a high level.
[0046] The SPI slave device 20 in the selected state sends a high level to the corresponding first open-drain circuit module 60. The first open-drain circuit module 60 sends a low level to the second open-drain circuit module 70. The second open-drain circuit module 70 sends a high level to the SPI master controller 10. This ensures that the high and low levels of the data signal sent from the SPI slave device 20 to the SPI master controller 10 remain unchanged.
[0047] The utility model uses an open-drain circuit module. Each SPI slave device 20 only needs to drive one NMOS tube Q1 switch. The driving capability is provided by the pull-up of the open-drain circuit. Under the premise of not using too many pins of the SPI master controller 10, the driving capability of the SPI slave device 20 is effectively improved, thereby improving the SPI parallel capability. At the same time, the driving load of each channel is only one junction capacitor, which reduces the capacitive load in the case of multi-channel parallel connection, thereby improving the signal communication capability.
[0048] The first push-pull circuit module 30 and the second push-pull circuit module 40 are both chips of model 74LVC244APW. Figure 5 For example, the data signal output terminal 12 of an SPI master controller is fanned out to the data signal input terminals 23 of six SPI slave devices through a chip of model 74LVC244APW.
[0049] The number of output terminals of the decoder 50 is equal to the number of the SPI slave devices 20 , and the number of the SPI slave devices 20 is equal to the number of the first open-drain circuit modules 60 .
[0050] The decoder 50 is a 3-8 decoder, the chip select signal terminals 14 of the SPI master controller are three, the SPI slave devices 20 are eight, and the number of the first open-drain circuit modules 60 is eight. The beneficial effect of this technical solution is that, combined with Figure 6, an SPI master controller 10 drives eight SPI slave devices 20; in the background art Figure 2 , one SPI master controller 10 drives three SPI slave devices 20. In comparison, the present invention does not occupy additional pin resources of the SPI master controller, thereby improving the SPI multi-channel parallel driving capability.
[0051] In another implementation, the SPI master controller has five chip select signal terminals, and four 3-8 decoders are provided to assemble into a 5-32 decoder structure. In this way, the five chip select signal terminals can control a maximum of thirty-two SPI slave devices.
[0052] The circuit further includes debugging indicator lights (not shown), which are connected to the output terminals of the decoder, and the number of the debugging indicator lights is equal to the number of the output terminals of the decoder. This technical solution has the beneficial effect of making it easier for personnel to clearly understand which SPI slave device is currently selected by the SPI master controller when debugging the circuit.
[0053] A debugging breadboard (not shown) is also included, on which the SPI master controller 10, the SPI slave device 20, the first push-pull circuit module 30, the second push-pull circuit module 40, the decoder 50, the first open-drain circuit module 60 and the second open-drain circuit module 70 are all fixedly arranged.
[0054] The SPI master controller 10 is an MCU, and the SPI slave device 20 is a subscriber line interface circuit (SLIC). The subscriber line interface circuit is a chip that performs analog-to-digital conversion and encoding of an analog telephone port.
[0055] The working mode of the present invention is as follows: the MOSI, CLK and other signals output by the SPI master controller 10 are fanned out to each SPI slave device 20 through the corresponding push-pull circuit module, and the SPI slave device 20 is selected and communicated through the push-pull circuit module and SPI serial processing.
[0056] Regarding the MISO signal of the SPI master controller 10, since this SPI slave device 20 is the signal sending end, if a push-pull circuit module is used, the signal will be pulled up and down by different SPI slave devices 20. Therefore, it is necessary to modify the driving method through the open-drain circuit, select a MOS tube with a smaller Cgs parameter for driving, and cascade the SPI slave devices 20 that need to be connected in parallel through a "wired-AND" method, and flip the signal through the second-level open-drain circuit to ensure that the high and low levels of the data signal reaching the SPI master controller 10 remain unchanged; at this time, each SPI slave device 20 only needs to drive one open-drain circuit module, and the driving capability of the subsequent circuit is provided by the driving current provided by the power supply of the open-drain circuit module. The setting resistance of each driving current can be determined by the relationship between voltage and current. value; the CS signal can be decoded by the decoder 50, saving the IO resources of the SPI master controller 10; the communication process is as follows: the SPI master controller 10 outputs the CS signal to select the SPI slave device 20 through the decoder 50, and the CLK and MOSI signals are fanned out through the corresponding push-pull circuit module. Since other SPI slave devices 20 are not selected, the CLK and MOSI signals output by the SPI master controller 10 are only valid for the selected SPI slave device 20; at the same time, since other slave SPI devices are not controlled, they do not affect the state of the open-drain circuit module at this time. Only the selected SPI slave device 20 can control whether the open-drain circuit module is turned on. At this time, the circuit only needs to drive one NMOS tube Q1 to turn on, reducing the overall IO driving capability requirement.
[0057] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.
Claims
1. A circuit for improving SPI multi-channel parallel driving capability, characterized in that: include: SPI master controller, SPI slave device, first push-pull circuit module, second push-pull circuit module, decoder, first open-drain circuit module and second open-drain circuit module; The clock signal terminal of the SPI master controller is connected to the input terminal of the first push-pull circuit module, and the output terminal of the first push-pull circuit module is connected to the clock signal terminals of the plurality of SPI slave devices; The data signal output end of the SPI master controller is connected to the input end of the second push-pull circuit module, and the output end of the second push-pull circuit module is connected to the data signal input ends of the plurality of SPI slave devices; The chip select signal end of the SPI master controller is connected to the input end of the decoder, and the output end of the decoder is connected to the chip select signal ends of the plurality of SPI slave devices; The data signal output ends of the multiple SPI slave devices are respectively connected to the input ends of the multiple first open-drain circuit modules, the output ends of the multiple first open-drain circuit modules are all connected to the input end of one second open-drain circuit module, and the output end of the second open-drain circuit module is connected to the data signal input end of the SPI master controller.
2. A circuit for improving SPI multi-channel parallel driving capability according to claim 1, characterized in that: The first open-drain circuit module and the second open-drain circuit module have the same structure, both including an open-drain circuit module input end, an open-drain circuit module output end, an NMOS transistor, a first resistor, a second resistor and a third resistor; The input end of the open-drain circuit module is connected to the gate of the NMOS tube and one end of the first resistor, the source of the NMOS tube is grounded, the drain of the NMOS tube is connected to the other end of the first resistor and one end of the second resistor, the other end of the second resistor is connected to one end of the third resistor and the output end of the open-drain circuit module, and the other end of the third resistor is connected to the power supply.
3. A circuit for improving SPI multi-channel parallel driving capability according to claim 1, characterized in that: The first push-pull circuit module and the second push-pull circuit module are both chips of model 74LVC244APW.
4. The circuit for improving SPI multi-channel parallel driving capability according to claim 1, characterized in that: The number of output terminals of the decoder is equal to the number of the SPI slave devices, and the number of the SPI slave devices is equal to the number of the first open-drain circuit modules.
5. A circuit for improving SPI multi-channel parallel driving capability according to claim 4, characterized in that: The decoder is a 3-8 decoder, the SPI master controller has three chip select signal terminals, the SPI slave devices have eight terminals, and the first open-drain circuit modules have eight terminals.
6. The circuit for improving SPI multi-channel parallel driving capability according to claim 1, characterized in that: It also includes debugging indicator lights, which are connected to the output end of the decoder, and the number of the debugging indicator lights is equal to the number of the output ends of the decoder.
7. The circuit for improving SPI multi-channel parallel driving capability according to claim 1, characterized in that: It also includes a debugging breadboard, and the SPI master controller, SPI slave device, first push-pull circuit module, second push-pull circuit module, decoder, first open-drain circuit module and second open-drain circuit module are all fixedly arranged on the debugging breadboard.
8. The circuit for improving SPI multi-channel parallel driving capability according to claim 1, characterized in that: The SPI master controller is an MCU, and the SPI slave device is a user line interface circuit.