Power semiconductor device leakage current measuring circuit
The combined circuit accelerates parasitic capacitor charging and operational amplifier negative feedback adjustment, which solves the problems of long test time and low accuracy of traditional leakage current measurement circuits, achieves fast and accurate leakage current measurement, and protects the device.
Patent Information
- Application Number
- CN202422070801.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2025-08-26
- Estimated Expiration
- 2034-08-23
AI Technical Summary
Traditional leakage current measurement circuits have problems such as long test time and low test accuracy.
The combined circuit of excitation power supply, control switch, op amp, diode and feedback resistor is adopted to accelerate the charging process of parasitic capacitors through the diode, and use the negative feedback regulation of the op amp to achieve fast and accurate leakage current measurement.
It greatly reduces test time, improves measurement accuracy, and provides protection for op amps to avoid overvoltage damage in unexpected short circuits.
Smart Images

Figure CN223272630U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of power semiconductor device testing and relates to a power semiconductor device leakage current measuring circuit. Background Art
[0002] Power semiconductor devices such as IGBTs and MOSFETs require reliability assessments during their development, manufacturing, and pre-application processes. Leakage current measurement is a key indicator in this reliability assessment. High-speed, stable leakage current measurement technology is crucial for mass testing of power semiconductor devices. Because the insulated gates of semiconductor devices are capacitive, traditional leakage current measurement suffers from long test times, high amplification factors in the sampling and amplifier circuits, and low test accuracy. Utility Model Content
[0003] The technical solution of the utility model is used to solve the problems of long test time and low test accuracy in traditional leakage current measurement circuits.
[0004] The utility model solves the above technical problems through the following technical solutions:
[0005] A power semiconductor device leakage current measurement circuit includes: an excitation power supply BT1, a control switch S1, an operational amplifier U1, a diode D1, a diode D2, and a feedback resistor R2; one end of the excitation power supply BT1 is connected to one end of the control switch S1, the other end of the excitation power supply BT1 is grounded, the other end of the control switch S1 is connected to the power semiconductor device under test, the leakage current output end of the power semiconductor device under test, the anode of the diode D1, the cathode of the diode D2, and the inverting input end of the operational amplifier U1 are connected together, the cathode of the diode D1 and the anode of the diode D2 are commonly grounded, the non-inverting input end of the operational amplifier U1 is grounded, one end of the feedback resistor R2 is connected to the inverting input end of the operational amplifier U1, and the other end of the feedback resistor R2 is connected to the output end of the operational amplifier U1.
[0006] Furthermore, the excitation power supply BT1 adopts a positive power supply or a negative power supply.
[0007] Furthermore, when the power semiconductor device under test is an IGBT, the gate of the IGBT under test is connected to the control switch S1, the collector and emitter of the IGBT under test are short-circuited, and the emitter of the IGBT under test, the anode of the diode D1, the cathode of the diode D2, and the inverting input terminal of the operational amplifier U1 are connected together.
[0008] Furthermore, when the power semiconductor device under test is a MOSFET, the gate of the MOSFET under test is connected to the control switch S1, the source and drain of the MOSFET under test are short-circuited, and the drain of the MOSFET under test, the anode of the diode D1, the cathode of the diode D2, and the inverting input terminal of the operational amplifier U1 are connected together.
[0009] The advantages of the present invention are:
[0010] The circuit of the utility model uses the leakage current of the power semiconductor device under test as the current input of the operational amplifier, balances the current through the output voltage of the operational amplifier, and ultimately makes the voltage of the power semiconductor device under test tend to be consistent with the loading voltage; the parasitic capacitance charging process of the power semiconductor device under test is accelerated by diodes D1 and D2, greatly reducing the test time; and protects the operational amplifier input from overvoltage, providing additional protection when the power semiconductor device under test is accidentally short-circuited to avoid damage to related devices due to problems such as overvoltage of the measurement output. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 This is a circuit diagram for measuring leakage current of a power semiconductor device according to an embodiment of the present utility model;
[0012] Figure 2 This is an equivalent circuit diagram of a power semiconductor device leakage current measurement circuit according to an embodiment of the present utility model;
[0013] Figure 3 This is a schematic diagram of the scheme for measuring leakage current using a sampling resistor in the prior art of comparative example 1;
[0014] Figure 4 This is a schematic diagram of the scheme of measuring leakage current using an ammeter in the prior art of comparative example 2. DETAILED DESCRIPTION
[0015] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the embodiments described are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.
[0016] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and specific embodiments:
[0017] Example 1
[0018] like Figure 1As shown, the power semiconductor device leakage current measurement circuit of the embodiment of the utility model includes: an excitation power supply BT1, a control switch S1, an IGBT module Q1 under test, an operational amplifier U1, a diode D1, a diode D2, and a feedback resistor R2; one end of the excitation power supply BT1 is connected to one end of the control switch S1, and the other end of the excitation power supply BT1 is grounded. The excitation power supply BT1 can be a positive power supply or a negative power supply; the other end of the control switch S1 is connected to the gate of the IGBT module Q1 under test, the collector and the emitter of the IGBT module Q1 under test are short-circuited, the emitter of the IGBT module Q1 under test, the anode of the diode D1, the cathode of the diode D2 and the inverting input terminal of the operational amplifier U1 are connected together, the cathode of the diode D1 and the anode of the diode D2 are grounded together, the non-inverting input terminal of the operational amplifier U1 is grounded, one end of the feedback resistor R2 is connected to the inverting input terminal of the operational amplifier U1, and the other end of the feedback resistor R2 is connected to the output terminal of the operational amplifier U1.
[0019] The IGBT module under test in this embodiment can be replaced with an insulated gate capacitive device such as MOSFET. In this case, the gate connection of the MOSFET under test is connected to the control switch S1, the source and drain of the MOSFET under test are short-circuited, and the drain of the MOSFET under test, the anode of the diode D1, the cathode of the diode D2, and the inverting input terminal of the operational amplifier U1 are connected together.
[0020] The working principle of the power semiconductor device leakage current measurement circuit of this embodiment is as follows:
[0021] like Figure 2 As shown, the equivalent circuit of the power semiconductor device leakage current measurement circuit of the embodiment of the utility model is that the IGBT module Q1 under test is equivalent to the equivalent resistance R1 of the test device and the parasitic capacitance C1 in parallel, that is, one parallel common end of the equivalent resistance R1 of the test device and the parasitic capacitance C1 is connected to the control switch S1, and the other parallel common end of the equivalent resistance R1 of the test device and the parasitic capacitance C1 is connected to the anode of the diode D1, the cathode of the diode D2 and the inverting input terminal of the operational amplifier U1.
[0022] When the control switch S1 is just closed, the parasitic capacitor C1 is in a nearly short-circuited state due to the presence of the parasitic capacitor C1, generating a large current. This current flows through the diode D1 (the reverse current flows through the diode D2), allowing the parasitic capacitor C1 to be quickly charged. Even when the parasitic capacitor C1 reaches approximately 1uF, this embodiment can complete the charging process of the parasitic capacitor C1 within 0.5ms.
[0023] When the voltage of the parasitic capacitor C1 is stable after it is fully charged, the voltage difference between the parasitic capacitor C1 and the excitation power supply BT1 is lower than the conduction voltage of the diodes D1 and D2. At this time, the input terminal of the operational amplifier U1 is in a virtual short state, and the output terminal 6 of the operational amplifier U1 is in a virtual short state. # The pin is a negative voltage, which generates a current on the feedback resistor R2. The current path is: excitation power supply BT1 → control switch S1 → equivalent resistance R1 of the device under test → feedback resistor R2; the operational amplifier U1 continuously adjusts the depth of the negative voltage through negative feedback, and the inverting input terminal 8 of the operational amplifier U1 is # The voltage of the pin drops to near 0V, and the operational amplifier U1 enters a stable state. # The voltage of the pin is 0V. At this time, diodes D1 and D2 are both in the cut-off state. By measuring the output terminal 6 of the operational amplifier U1, # The voltage Vout of the pin is obtained, and the voltage across the feedback resistor R2 is Vout. At this time, the current flowing through the feedback resistor R2 is equivalent to the leakage current flowing through the equivalent resistor R1 of the device under test, that is, I lou =-Vout / R2, I lou is the leakage current.
[0024] And because one end of the equivalent resistance R1 of the device under test is directly connected to the excitation power supply BT1 through the control switch S1, the other end of the equivalent resistance R1 of the device under test is connected to the inverting input terminal 8 of the operational amplifier U1. # Pin connection, inverting input of operational amplifier U1 8 # The voltage of the pin is 0V, which is equivalent to the other end of the equivalent resistance R1 of the device under test being virtually grounded. That is, the voltage across the equivalent resistance R1 of the device under test is basically equal to the voltage of the excitation power supply BT1. The voltage difference can be controlled within 10uV and does not change with the change of leakage current, thereby reducing the error of the excitation voltage.
[0025] In this embodiment, the feedback resistor R2 can be increased in value without affecting the test speed and the accuracy of the applied voltage. When the feedback resistor R2 is selected to be 10MΩ, a 10mV / nA amplification ratio can be easily generated, which can be directly connected to the ADC without introducing an additional amplification circuit and its associated slow response time and high amplification error.
[0026] Comparative Example 1
[0027] like Figure 3As shown, Comparative Example 1 illustrates a prior art solution for measuring leakage current using a sampling resistor. When control switch S1 is closed, sampling resistor R3 and parasitic capacitor C1 form an RC low-pass filter circuit. This limits the current charging parasitic capacitor C1, significantly increasing the charging time of parasitic capacitor C1. When parasitic capacitor C1 is approximately 1uF and sampling resistor R3 is 10kΩ, the charging time of parasitic capacitor C1 is approximately 62ms, more than a hundred times longer than the 0.5ms in Example 1.
[0028] When charging reaches a stable state, a current flows through the sampling resistor R3, generating a voltage difference across the two ends of the sampling resistor R3. This causes the voltage actually loaded on the equivalent resistance R1 and parasitic capacitance C1 of the device under test to be lower than the set excitation power supply BT1 voltage, and the magnitude of the reduction varies with the leakage current.
[0029] In order to reduce the influence of the sampling resistor R3 on the voltage loaded on the equivalent resistance R1 and parasitic capacitance C1 of the device under test, a smaller sampling resistor value is usually selected, which results in a very low voltage across the sampling resistor itself, further increasing the difficulty of accurately reading the voltage.
[0030] Typically, the sampling resistor is 10kΩ, and the sampling current range is between 1nA and 1000nA; and the loaded test voltage is usually around 20V, that is:
[0031] (1) When the leakage current is 1nA, the voltage on the sampling resistor R3 is only 10uV, which is not only easily affected by electromagnetic interference from the surrounding environment, but also needs to be amplified 100,000 times to amplify the voltage to 1-3V for the next ADC sampling, which is very likely to introduce additional amplification errors. Such a large amplification factor will cause a relatively large signal delay, further reducing the measurement speed.
[0032] (2) If you want to reduce the amplification factor to a reasonable factor of 100 or lower, you need to increase the resistance of the sampling resistor R3 to 1MΩ. Under 1nA conditions, a voltage difference of 1mV can be generated for sampling, but at 1000nA, a voltage difference of 1V will be generated, which will cause the voltage loaded on the device under test to be 1V less than the set value (compared to the set value of 20V, the actual loaded voltage is 5% different).
[0033] Comparative Example 2
[0034] like Figure 4 As shown, comparative example 2 is a solution of measuring leakage current using an ammeter in the prior art. The current is usually designed as a series sampling resistor inside, but related amplification and digital-to-analog conversion devices are added externally. There is no essential difference from solution 1, so it will not be repeated here.
[0035] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.
Claims
1. A power semiconductor device leakage current measurement circuit, characterized in that: include: An excitation power supply BT1, a control switch S1, an operational amplifier U1, a diode D1, a diode D2, and a feedback resistor R2; one end of the excitation power supply BT1 is connected to one end of the control switch S1, the other end of the excitation power supply BT1 is grounded, the other end of the control switch S1 is connected to the power semiconductor device under test, the leakage current output end of the power semiconductor device under test, the anode of the diode D1, the cathode of the diode D2, and the inverting input end of the operational amplifier U1 are connected together, the cathode of the diode D1 and the anode of the diode D2 are grounded together, the non-inverting input end of the operational amplifier U1 is grounded, one end of the feedback resistor R2 is connected to the inverting input end of the operational amplifier U1, and the other end of the feedback resistor R2 is connected to the output end of the operational amplifier U1.
2. The power semiconductor device leakage current measurement circuit according to claim 1, characterized in that: The excitation power supply BT1 adopts a positive power supply or a negative power supply.
3. The power semiconductor device leakage current measurement circuit according to claim 1, characterized in that: When the power semiconductor device under test is an IGBT, the gate of the IGBT under test is connected to the control switch S1, the collector and emitter of the IGBT under test are short-circuited, and the emitter of the IGBT under test, the anode of the diode D1, the cathode of the diode D2 and the inverting input terminal of the operational amplifier U1 are connected together.
4. The power semiconductor device leakage current measurement circuit according to claim 1, characterized in that: When the power semiconductor device under test is a MOSFET, the gate of the MOSFET under test is connected to the control switch S1, the source and drain of the MOSFET under test are short-circuited, and the drain of the MOSFET under test, the anode of the diode D1, the cathode of the diode D2, and the inverting input terminal of the operational amplifier U1 are connected together.