Arithmetic unit, chip, computing power board and computing device
By designing independent clock frequencies for logic control modules and data path modules, the clock correlation problem caused by shared clocks is solved, and a lower power consumption and more stable computing unit design is achieved, adapting to different software algorithms and hardware architectures.
Patent Information
- Application Number
- CN202422221720.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2025-08-26
- Estimated Expiration
- 2034-09-10
AI Technical Summary
The logic control module and the data path module share the same clock and cannot meet their respective clock requirements at the same time, resulting in the high-performance computing core design facing clock correlation problems.
Using an independent clock frequency design, the clock signals of the logic control module and the data path module are generated through the clock components, and the phase-locked loop, frequency divider and distributed clock generator are used to realize their independent clock frequency control. Combined with a multiplexer and distributed clock control unit, the clock frequency is flexibly adjusted to meet their respective performance needs.
Without reducing overall performance, the power consumption of the computing unit is reduced, and timing stability and flexibility are improved, adapting to different software algorithms and hardware architectures.
Smart Images
Figure CN223272829U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of computer science, and in particular to a computing unit and a computing device with multiple computing cores. Background Art
[0002] When computing devices with multiple computing cores perform hash operations, high-performance computing core design faces a technical challenge: the clock correlation between the logic control module and the datapath module. The logic control module requires precise timing control to ensure correct task scheduling and instruction execution, while the datapath module needs to perform hash calculations at a higher rate. Sharing the same clock for both cannot simultaneously meet their respective clock requirements. Utility Model Content
[0003] In order to solve the problem that the logic control module and the data path module share the same clock and cannot simultaneously meet the clock requirements of each, the utility model discloses an operation unit, comprising:
[0004] Multiple computing engines, each of the computing engines includes a logic control module and a data path module connected to each other, the logic control module is used to receive task information, the data path module is used to calculate a calculation result based on the task information and synchronize the calculation result to the logic control module, and the logic control module is further used to obtain task return information based on the calculation result;
[0005] a clock component for generating at least one first clock signal and at least one second clock signal, wherein the first clock signal is provided to the logic control module and the second clock signal can be configured as a clock of the data path module;
[0006] The overall logic control module is connected to the plurality of logic control modules and the clock component, and is used to send task information to the plurality of logic control modules and receive task return information from the plurality of logic control modules.
[0007] In the above-mentioned operation unit, the clock frequency of the first clock signal is lower than the clock frequency of the second clock signal.
[0008] In the above technical solution, when the clock frequency of the data path module does not increase, the clock frequency of the logic control module is lower than the clock frequency of the data path module, which can reduce the power consumption of the operation unit.
[0009] In the above-mentioned computing unit, the clock component further includes:
[0010] A phase-locked loop (PLL) is used to generate a frequency-multiplied clock signal;
[0011] at least one first frequency divider, the first frequency divider being connected to the phase-locked loop and each of the logic control modules, and configured to generate the first clock signal;
[0012] At least one second frequency divider is connected to the phase-locked loop and each of the data path modules, and is configured to generate the second clock signal.
[0013] In the above technical solution, the overall logic control module can flexibly adjust the clock frequencies of the logic control modules and / or data path modules in batches.
[0014] The above-mentioned operation unit also includes: at least one distributed clock generator, each of which is connected to the corresponding data path module, and the distributed clock generator is used to generate a third clock signal, and the third clock signal can be configured as the clock corresponding to the data path module.
[0015] The above-mentioned operation unit further includes: a multiplexer, each of the multiplexers is connected between the corresponding distributed clock generator, the clock component and the corresponding data path module, and the multiplexer is also connected to the overall logic control module. The multiplexer is used to configure one of the second clock signal and the third clock signal as the clock of the corresponding data path module under the control of the overall logic control module.
[0016] In the above-mentioned operation unit, the overall logic control module is connected to the plurality of distributed clock generators, and is used to adjust the clock frequency of the third clock signal generated by the distributed clock generators.
[0017] In the above technical solution, multiple distributed clock generators are used to provide the corresponding data path modules with third clock signals, which can further accurately meet the performance requirements of each data path module based on the task calculation situation of the data path module, thereby reducing the power consumption of the computing unit as a whole.
[0018] In the above-mentioned computing unit, the distributed clock generator is a ring oscillator.
[0019] In the above-mentioned operation unit, the logic control module and the data path module further include: a data synchronization pulse generating circuit for emitting a data synchronization pulse signal; and a data synchronization edge detector circuit for detecting a data synchronization edge signal; wherein the logic control module and the data path module perform data synchronization through the data synchronization pulse signal, the data synchronization edge signal and the register.
[0020] In order to better achieve the purpose of the present invention, the present invention also provides a chip, including one or more computing units of any one of the above items.
[0021] In order to better achieve the purpose of the present invention, the present invention also provides a computing board, including one or more of the above-mentioned chips.
[0022] In order to better achieve the purpose of the present invention, the present invention also provides a computing device, including a power board, a control board, a connecting board, a radiator and a plurality of the aforementioned computing boards, wherein the control board is connected to the computing board through the connecting board, the radiator is arranged around the computing board, and the power board is used to provide power to the connecting board, the control board, the radiator and the computing board.
[0023] The computing unit, chip, hashboard, and computing device disclosed in this utility model enable the logic control module and the data path module to have independent clock frequencies, thereby maximally meeting their respective performance requirements without compromising overall performance. Furthermore, the independent clock frequencies of the logic control module and the data path module can also reduce the power consumption of the computing unit. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 This is a schematic block diagram of the composition of the computing unit in one embodiment of the present invention.
[0025] Figure 2 This is a block diagram of the connection relationship between the overall logic control module and the logic control module in one embodiment of the present utility model.
[0026] Figure 3 This is a schematic block diagram of the composition of the computing unit in another embodiment of the present invention.
[0027] Figure 4 This is a schematic block diagram of the composition of the computing unit in another embodiment of the present invention.
[0028] Figure 5 This is a schematic block diagram of the composition of the computing unit in another embodiment of the present invention.
[0029] Figure 6 This is a schematic diagram of data synchronization between the logic control module and the data path module in one embodiment of the present utility model.
[0030] Figure 7 This is a schematic block diagram of the composition of the computing unit in another embodiment of the present invention.
[0031] Figure 8 Schematic diagram of a computational pipeline for task scheduling in one embodiment of the present invention.
[0032] Figure 9This is a waveform diagram of the forward transmission of the computing unit clock in one embodiment of the present invention.
[0033] Figure 10 This is a waveform diagram of the reverse transmission of the computing unit clock in one embodiment of the present invention.
[0034] Figure 11 This is a schematic diagram of a chip of the present invention.
[0035] Figure 12 This is a schematic diagram of a hash board of the present invention.
[0036] Figure 13 This is a schematic diagram of a computing device according to the present invention.
[0037] Wherein, the reference numerals:
[0038] 1- General logic control module
[0039] 11-Computation Engine
[0040] 111-Logic Control Module
[0041] 113, 113'-first clock signal
[0042] 112-Data Path Module
[0043] 114, 114'-second clock signal
[0044] 2-Clock Component
[0045] 21-Phase-Locked Loop
[0046] 22, 22'-First divider
[0047] 23, 23'-Second divider
[0048] 3-Distributed clock control unit
[0049] 31-Distributed Clock Generator
[0050] 311-third clock signal
[0051] 32-way multiplexer
[0052] 4-External storage
[0053] 10-Arithmetic Unit
[0054] 100-chip
[0055] 101-Control Unit
[0056] 1000-Computing Devices
[0057] 1001-Power board
[0058] 1002 control board
[0059] 1003-Connecting plate
[0060] 1004-Radiator DETAILED DESCRIPTION
[0061] The following is a detailed description of the technical solution of the present invention in conjunction with the accompanying drawings and specific embodiments to further understand the purpose, solution and beneficial technical effects of the present invention. Obviously, the specific embodiments described in the present invention are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments disclosed in the present invention, all other embodiments obtained by ordinary technicians in this field without expending creative work also fall within the scope disclosed by the technical solution of the present invention.
[0062] It should be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, article, or device comprising the element.
[0063] Certain terms are used in this specification and the appended claims to refer to specific components or parts. Persons skilled in the art will understand that technology users or manufacturers may use different nouns or terms to refer to the same component or part. This specification and the appended claims do not distinguish components or parts based on differences in name, but rather on differences in their functions.
[0064] In this utility model, terms such as "upper," "lower," "left," "right," "front," "back," "top," "bottom," "inner," "outer," "center," "vertical," "horizontal," "transverse," and "longitudinal" indicate positions or locations based on the positions or locations shown in the accompanying drawings. These terms are primarily intended to better describe the utility model and its embodiments and are not intended to limit the devices, elements, or components indicated to having a specific orientation, or to being constructed or operated in a specific orientation.
[0065] Furthermore, the terms "installed," "disposed," "provided with," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral structures; mechanical connections or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in this utility model based on the specific circumstances.
[0066] In order to better understand the technical solution of this utility model, please refer to Figure 1 The content shown. Among them, Figure 1 This is a schematic block diagram of the architecture of the computing unit 10 in one embodiment of the present invention.
[0067] In this embodiment, the utility model discloses an operation unit 10, including: multiple computing engines (CE) 11, each computing engine 11 includes a logic control module (CTRL) 111 and a data path module (DP, datapath) 112 connected to each other, the logic control module 111 receives task information, the data path module 112 calculates a calculation result based on the task information and synchronizes the calculation result to the logic control module 111, and the logic control module also obtains task return information based on the calculation result; a clock component 2, the clock component 2 generates one or more first clock signals 113 and one or more second clock signals 114 independent of the first clock signal 113, the first clock signal 113 is provided to the logic control module 111, and the second clock signal 114 can be configured as a clock of the data path module 112; and a total logic control module (TOPCTRL) 1, connected to the multiple logic control modules 111 and the clock component 2 (for the sake of simplicity and ease of viewing, Figure 1 The connection between the overall logic control module 1 and the multiple logic control modules 111 is not shown in the figure), and the overall logic control module 1 sends task information to the multiple logic control modules 111 and receives task return information from the multiple logic control modules 111.
[0068] In this embodiment, the overall logic control module 1 is responsible for distributing task information to each computing engine 11 and receiving task return information from each computing engine 11. The logic control module 111 of each computing engine 11 is responsible for receiving task information sent by the overall logic control module 1 and returning the task information to the overall logic control module 1. At the same time, the logic control module 111 of each computing engine 11 passes the task information to the data path module 112, which performs calculations based on the task information.
[0069] In this embodiment, when a task is characterized by a relatively long execution time, typically on the order of milliseconds or longer, the logic control module 111 of the computing engine 11 completes receiving the task information, initiates the task, and stores the task-related information for ready use by the data path module 112. When the task is completed, the logic control module 111 transmits the information to the overall logic control module 1. During this process, the logic control module 111 remains relatively inactive for most of the time. Furthermore, the time taken up by the stages of receiving the task information from the overall logic control module 1, initiating the task, and transmitting the information to the overall logic control module 1 is very low.
[0070] In this embodiment, the clock component 2 is used to provide at least one first clock signal 113 to the multiple logic control modules 111, and at least one second clock signal 114 independent of the first clock signal 113 to the multiple data path modules 112. This decouples the clocks of the logic control modules 111 and the data path modules 112, allowing the logic control modules 111 and the data path modules 112 to have their own independent working clocks, thereby meeting their respective performance requirements based on the characteristics of the tasks.
[0071] In a specific embodiment of the computing unit 10 of the present invention, the clock frequency of the first clock signal 113 is lower than the clock frequency of the second clock signal 114 .
[0072] In an embodiment of the present invention, if a task takes a long time to execute, the logic control module 111 does not need to use the same high-frequency clock as the data path module 112. In a further embodiment, when the logic control module 111 does not need to participate in task calculations, the clock of the logic control module 111 is turned off under the control of the overall logic control module 1. While the clock frequency of the data path module 112 remains unchanged, reducing or turning off the clock of the logic control module 111 can reduce the power consumption of the computing unit 10.
[0073] In order to better illustrate the implementation scheme of the present utility model, refer to Figure 2 , Figure 2 1 is a block diagram of the connection relationship between the overall logic control module 1 and the logic control module 111 in one embodiment of the present invention.
[0074] In a specific embodiment of the computing unit 10 of the present invention, the overall logic control module 1 is connected to each logic control module 111 . The overall logic control module 1 sends task information to the logic control module 111 and receives task return information from the logic control module 111 .
[0075] See also Figure 1In a specific embodiment of the operation unit 10 of the present invention, the clock component 2 further includes: a phase-locked loop (PLL) 21, which generates a multiplied clock signal; one or more first frequency dividers (DIV1) 22, which are connected to the phase-locked loop 21 and each logic control module 111, wherein the first frequency divider 22 generates a first clock signal 113; and one or more second frequency dividers (DIV2) 23, which are connected to the phase-locked loop 21 and each data path module 112, wherein the second frequency divider 23 generates a second clock signal 114.
[0076] In order to better illustrate the implementation scheme of the present utility model, refer to Figure 3 , Figure 3 FIG. 1 is a schematic block diagram of the composition of the computing unit 10 in another embodiment of the present invention.
[0077] This embodiment and Figure 1 The main difference between the embodiments is that the number of the first frequency dividers (DIV1 and DIV1') and the second frequency dividers (DIV2 and DIV2') is two, which is only for illustration and the present invention is not limited thereto.
[0078] In this embodiment, when the number of the first frequency divider 22 and the second frequency divider 23 is greater than one, the clock frequencies of the multiple first clock signals (for example, 113 and 113') are different from each other, and the clock frequencies of the multiple second clock signals (for example, 114 and 114') are different from each other. The overall logic control module 1 can provide different clocks to the multiple logic control modules 111 by switching the multiple first frequency dividers; it can also provide different clocks to the multiple data path modules 112 by switching the multiple second frequency dividers. At the same time, the overall logic control module 1 can also, according to the characteristics of the task, for example, provide the clock generated by the first frequency divider 22 to a part of the logic control modules 111, and provide the clock generated by the first frequency divider 22' to another part of the logic control modules 111. The same is true for the data path module 112, which will not be elaborated. In the above technical solution, the overall logic control module 1 can flexibly adjust the clock frequency of the logic control module 111 and / or the data path module 112 in batches.
[0079] In a further embodiment, the first frequency divider 22 and the second frequency divider 23 may also be dynamic frequency dividers, and the overall logic control module 1 may adjust the clock frequency of the clock signal generated by the first frequency divider 22 and / or the second frequency divider 23 .
[0080] In order to better illustrate the implementation scheme of the present utility model, please refer to Figure 4 , Figure 4 FIG. 1 is a schematic block diagram of the composition of the computing unit 10 in another embodiment of the present invention.
[0081] In a specific embodiment of the present invention, it also includes:
[0082] At least one distributed clock generator (RO) 31 is provided. Each distributed clock generator 31 is connected to a corresponding data path module 112 . The distributed clock generator 31 generates a third clock signal 311 . The third clock signal 311 can be configured as a clock of the corresponding data path module 112 .
[0083] Furthermore, in a specific embodiment of the present invention, it also includes:
[0084] Multiplexers (MUX) 32 are each connected between a corresponding distributed clock generator 31, clock component 2, and corresponding data path module 112. Multiplexers 32 are also connected to the overall logic control module 1. Under the control of the overall logic control module 1, multiplexers 32 select one of the second clock signal 114 and the third clock signal 311 as the clock for the corresponding data path module 112. Specifically, multiplexers 32 are connected to the second frequency divider 23 and distributed clock generator 31 of the corresponding clock component 2. A selection terminal of multiplexers 32 is connected to the overall logic control module 1.
[0085] In a specific embodiment of the present invention, the overall logic control module 1 is connected to a plurality of distributed clock generators 31 to adjust the clock frequency of the third clock signal 311 generated by the distributed clock generators 31 .
[0086] In this embodiment, through the adjustment of the multiple distributed clock generators 31 by the overall logic control module 1 , the clock frequencies of the multiple third clock signals 311 may be all the same, partially the same, or different from each other.
[0087] In this embodiment, the distributed clock generator 31 is a ring oscillator.
[0088] Compared with the clock signals generated by the phase-locked loop and the frequency divider, the clock signal generated by the ring oscillator has a fast startup speed and a small device area, and is therefore suitable for providing to the data path module 112 of each computing engine 11.
[0089] In the above technical solution, multiple distributed clock generators 31 provide third clock signals 311 to corresponding datapath modules 112. Furthermore, each datapath module 112 can be provided with an independent clock. This allows for more precise performance requirements of each datapath module 112 based on its computational tasks, thereby reducing overall power consumption of the computing unit. Dynamic voltage and frequency scaling (DVFS) technology can be used to adjust the clock for each datapath module.
[0090] In order to better illustrate the implementation scheme of the present utility model, please refer to Figure 5 , Figure 5 FIG. 1 is a schematic block diagram of the composition of the computing unit in another embodiment of the present utility model. Figure 4 The main difference between the embodiment is that the operation unit 10 further includes a distributed clock control unit (ROCTRL) 3 (for the sake of simplicity, Figure 5 (The connection between the first frequency divider 22 and the logic control module 111 is not shown in the figure.) The distributed clock control unit 3 is connected to the overall logic control module 1 and each distributed clock generator 31. The distributed clock control unit 3 receives control instructions from the overall logic control module 1 and adjusts or controls the clock frequency of the target distributed clock generator 31 according to the control instructions. In the above technical solution, the provision of the distributed clock control unit 3 enables a modular architecture, reduces the complexity of the overall logic control module 1, and facilitates debugging and maintenance.
[0091] In a specific embodiment of the present invention, the computing engine 11 uses pipeline technology. After the logic control module 111 receives the task information from the overall logic control module 1, it saves the task information (the task information includes source data and task configuration information) and then starts the task. After starting the task, the data path module 112 begins to execute the task. The data path module 112 performs multiple calculations based on the source data and task configuration information in the task information. Each calculation starts from the head of the pipeline and ends at the tail. The calculation process is divided into multiple stages. If the result of the calculation meets the preset conditions (the conditions come from the task configuration information), the logic control module 111 will be triggered to send the task return information to the overall logic control module 1. Since the clocks of the logic control module 111 and the data path module 112 are independent of each other, data synchronization is required during the execution of the task. The timing for data synchronization can be determined based on the task configuration information. For example, data synchronization can be performed when the data path module 112 receives task information from the logic control module 111, at the beginning, middle, and end of the pipeline, and when the data path module 112 completes the task calculation and returns the task calculation results to the logic control module 111. During other task execution stages, the logic control module 111 and the data path module 112 do not need to be synchronized. Furthermore, because the clock frequency of the logic control module 111 is lower than that of the data path module 112, the power consumption of the computing engine 11 can be reduced. In one embodiment of the present invention, data synchronization can be performed at each stage of the task calculation process based on the task configuration information, thereby improving the accuracy and reliability of the task calculation.
[0092] In order to better illustrate the implementation scheme of the present utility model, please refer to Figure 6 , Figure 6 Schematic diagram of data synchronization between the logic control module 111 and the data path module 112 in one embodiment of the present invention.
[0093] In a specific embodiment of the present invention, the logic control module 111 and the data path module 112 also include:
[0094] A data synchronization pulse generating circuit is used to generate a data synchronization pulse signal; and a data synchronization edge detector circuit is used to detect the data synchronization edge signal; wherein,
[0095] The logic control module 111 and the data path module 112 perform data synchronization through data synchronization pulse signals, data synchronization edge signals and registers.
[0096] Those skilled in the art will appreciate that the data synchronization pulse generating circuit in the above-described embodiment may be a pulse generating circuit composed of an oscillating period, and the data synchronization edge detector circuit may be any of an upper edge detection circuit, a lower edge detection circuit, or a double edge detection circuit. Both the data synchronization pulse generating circuit and the data synchronization edge detector are standard circuits in digital circuits and are not described in detail herein. The register may be a data register, a general register, or another type of register, and this is not limited by the present invention.
[0097] In this embodiment, since the clocks of the data path module 112 and the logic control module 111 are different and independent of each other, the data transmitted between them needs to be synchronized. The working principle of data synchronization through data synchronization pulse signals, data synchronization edge signals and registers is as follows:
[0098] When the logic control module 111 is the data sender, the data path module 112 is the data receiver. When the logic control module 111 is the data receiver, the data path module 112 is the data sender. The data sender stores the data to be synchronized in a register. The data sender initiates a data synchronization edge signal, which is detected by the data synchronization edge detector circuit of the data receiver. The data synchronization pulse generation circuit of the data receiver sends a data synchronization pulse signal. The data receiver reads the data to be synchronized in the register, completing data synchronization.
[0099] In this embodiment, if Figure 6 As shown, when the logic control module 111 notifies the data path module 112 to perform data synchronization, the logic control module 111 stores the task data data0 in the register, and the logic control module 111 then sends a data synchronization edge signal and outputs it to the data path module 112. The data path module 112 detects the data synchronization edge signal through the data synchronization edge detector circuit and generates a data synchronization pulse signal through the data synchronization pulse generating circuit. Then, the data path module 112 reads the data data0 in the register (for example, the data data0 is the task information).
[0100] When data path module 112 notifies logic control module 111 to perform data synchronization, it stores the data to be synchronized, data1, in a register. It then issues a data synchronization edge signal and outputs it to logic control module 111. Logic control module 111 detects this data synchronization edge signal through its data synchronization edge detector circuit and generates a data synchronization pulse signal through its data synchronization pulse generator circuit. Logic control module 111 then reads the data data1 (e.g., data data1 is task return information) from the register, completing data synchronization.
[0101] In order to better illustrate the implementation scheme of the present utility model, please refer to Figure 7 , Figure 7 FIG. 1 is a schematic block diagram of the composition of the computing unit 10 in another embodiment of the present invention.
[0102] In a specific embodiment of the present invention, the data path module 112 and the logic control module 111 perform data synchronization in the external memory 4 .
[0103] In this embodiment, when the amount of task information to be executed is large, it is necessary to use external memory 4 for reading and storage. Before the calculation task begins, the data path module 112 reads the external memory 4 to obtain the task information. After completing the task calculation, the data path module 112 writes to the external memory 4 to store the task return information in the external memory 4, and then synchronizes the task return information to the logic control module 111.
[0104] In order to better illustrate the implementation scheme of the present utility model, please refer to Figure 8 , Figure 8 Schematic diagram of a computational pipeline for task scheduling in one embodiment of the present invention.
[0105] The task scheduling of the neural network processor NPU (Neural Processing Unit) is similar to the hash calculation task, which dispatches multiple large tasks to multiple computing engines 11, and the calculation time is relatively long.
[0106] The logic control module 111 receives a task and splits it into multiple subtasks of a large order of magnitude. Multiple subtasks share the same task configuration control information. Similarly, in the NPU, a large computing task is also split into multiple subtasks of a large order of magnitude, and multiple subtasks share the control information of the same large task. Figure 8 In the command, the main task is TaskCMD and the subtask is Cycle CMD.
[0107] In one embodiment of the present invention, a neural network processor (NPU) is provided, comprising a computing engine 11, a control unit, and a storage unit. The control unit is connected to the computing engine 11 and the storage unit. The computing engine 11 further comprises a data path module 112 and a logic control module 111. The clocks of the data path module 112 and the logic control module 111 are independent of each other. The structure for providing independent clocks for the data path module 112 and the logic control module 111 is the same as the embodiment of the computing unit 10 described above in the present invention and will not be described in detail here. Compared with the logic control module 111 and the data path module 112 sharing the same clock, it has greater flexibility to adapt to different software algorithms and hardware architectures.
[0108] Multiple sub-tasks share the control information of the same large task, reducing the number of scheduling times of the control information. The clocks of the data path module 112 and the logic control module 111 are independent of each other. By reducing the clock frequency of the logic control module 111, the overall power consumption of the NPU is reduced.
[0109] In order to better illustrate the implementation scheme of the present utility model, please refer to Figure 9-10 , Figure 9 1 is a waveform diagram of the clock forward transmission of the computing unit 10 in one embodiment of the present invention. Figure 10 1 is a waveform diagram of the clock reverse transmission of the computing unit 10 in one embodiment of the present invention.
[0110] The clocks of the logic control module 111 and the data path module 112 can be transmitted in a forward direction or a reverse direction.
[0111] In the existing design, both the logic control module 111 and the data path module 112 share the same clock, and the clock is broadcast to each stage of the pipeline, which may cause unstable timing of the pipeline.
[0112] In one embodiment of the present invention, since the clocks of data path module 112 and logic control module 111 are independent, stable timing is ensured during the forward clock propagation of the pipeline. Compared to a broadcast clock, the forward clock propagation in the arithmetic unit 10 of the present invention has a buffer at each stage, i.e., a setup time, which provides sufficient drive capability and thus more stable timing.
[0113] In one embodiment of the present invention, since the clocks of the data path module 112 and the logic control module 111 are independent, accurate timing can be guaranteed when the pipeline clocks are reversed. In the arithmetic unit 10 of the present invention, reverse clock transmission can provide a longer hold time, thereby making the timing more accurate and facilitating back-end design.
[0114] In order to better illustrate the implementation scheme of the present utility model, please refer to Figure 11 , Figure 11 This is a schematic diagram of a chip of the present invention. The present invention also provides a chip, such as Figure 11 As shown, the chip 100 includes a control unit 101 and one or more operation units 10. The control unit 101 inputs data to the operation unit 10 and processes the data output by the operation unit 10.
[0115] In order to better illustrate the implementation scheme of the present utility model, please refer to Figure 12 , Figure 12 This is a schematic diagram of a computing board of the present invention. Figure 12As shown, the present invention also provides a hash board 200, comprising one or more of the above-mentioned chips 100.
[0116] In order to better illustrate the implementation scheme of the present utility model, please refer to Figure 13 , Figure 13 This is a schematic diagram of a computing device according to the present invention.
[0117] like Figure 13 As shown, the present invention also provides a computing device 1000, including a power board 1001, a control board 1002, a connecting board 1003, a radiator 1004 and a plurality of computing boards 200, wherein the control board 1002 is connected to the computing board 200 through the connecting board 1003, and the radiator 1004 is arranged around the computing board 200, and the power board 1001 provides power to the connecting board 1003, the control board 1002, the radiator 1004 and the computing board 200.
[0118] The computing unit, chip, hashboard, and computing device disclosed in this utility model enable the logic control module 111 and the data path module 112 to have independent clock frequencies, thereby maximally meeting their respective performance requirements without compromising overall performance. Furthermore, the independent clock frequencies of the logic control module 111 and the data path module 112 can reduce the power consumption of the computing unit, make the timing of the computing unit more stable, and provide greater flexibility to adapt to different software algorithms and hardware architectures.
[0119] In summary, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, technicians familiar with the field can evolve various corresponding changes and deformations based on the present invention, but these corresponding changes and deformations should all fall within the scope of protection of the patent applied for the present invention.
Claims
1. A computing unit, characterized in that: include: Multiple computing engines, each of the computing engines includes a logic control module and a data path module connected to each other, the logic control module is used to receive task information, the data path module is used to calculate a calculation result based on the task information, synchronize the calculation result to the logic control module, and the logic control module is further used to obtain task return information based on the calculation result; a clock component for generating at least one first clock signal and at least one second clock signal, wherein the first clock signal is provided to the logic control module and the second clock signal can be configured as a clock of the data path module; The overall logic control module is connected to the plurality of logic control modules and the clock component, and is used to send task information to the plurality of logic control modules and receive task return information from the plurality of logic control modules.
2. The computing unit according to claim 1, wherein: A clock frequency of the first clock signal is lower than a clock frequency of the second clock signal.
3. The computing unit according to claim 1, wherein: The clock component further comprises: Phase-locked loop, used to generate a frequency-doubled clock signal; at least one first frequency divider, the first frequency divider being connected to the phase-locked loop and each of the logic control modules, and configured to generate the first clock signal; At least one second frequency divider is connected to the phase-locked loop and each of the data path modules, and is used to generate the second clock signal.
4. The computing unit according to claim 1, wherein: Also includes: At least one distributed clock generator, each of which is connected to a corresponding data path module, and the distributed clock generator is used to generate a third clock signal, and the third clock signal can be configured as a clock corresponding to the data path module.
5. The computing unit according to claim 4, characterized in that: Also includes: A multiplexer, each of the multiplexers is connected between the corresponding distributed clock generator, the clock component and the corresponding data path module, and the multiplexer is also connected to the overall logic control module. The multiplexer is used to configure one of the second clock signal and the third clock signal as the clock of the corresponding data path module under the control of the overall logic control module.
6. The computing unit according to claim 5, characterized in that: The overall logic control module is connected to the plurality of distributed clock generators and is configured to adjust the clock frequency of the third clock signal generated by the distributed clock generators.
7. The computing unit according to claim 6, characterized in that The distributed clock generator is a ring oscillator.
8. The computing unit according to any one of claims 1 to 7, characterized in that: The logic control module and the data path module further include: A data synchronization pulse generating circuit, used for sending a data synchronization pulse signal; The data synchronization edge detector circuit is used to detect the data synchronization edge signal; wherein, The logic control module and the data path module perform data synchronization through a data synchronization pulse signal, a data synchronization edge signal and a register.
9. A chip, characterized in that: The method comprises one or more computing units according to any one of claims 1 to 8.
10. A hashboard, characterized in that: Comprising one or more chips as claimed in claim 9.
11. A computing device, characterized in that The system comprises a power board, a control board, a connection board, a radiator, and a plurality of hash boards as claimed in claim 10, wherein the control board is connected to the hash boards via the connection board, the radiator is arranged around the hash boards, and the power board is used to provide power to the connection board, the control board, the radiator, and the hash boards.