Lead frame structure
By setting up anti-spill grooves and isolation grooves on the base island of the lead frame, the chip is fixed with conductive and insulating glue, and connected by heat dissipation parts, the problems of short circuit and glue diffusion of MOS chips are solved, achieving more stable packaging and higher heat dissipation performance.
Patent Information
- Application Number
- CN202422710806.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-06
- Publication Date
- 2025-08-29
- Estimated Expiration
- 2034-11-06
AI Technical Summary
In the existing lead frame structure, the glue is prone to overflow and short circuit when the MOS chip is fixed, and different glues are prone to diffuse and cause layering risks when the dual-chip packaging.
The anti-spill groove and isolation groove are set on the base island of the lead frame. The MOS chip and the main control chip are fixed respectively using conductive glue and insulating glue, and connected to the pins through the heat dissipation parts to enhance structural stability and heat dissipation performance.
Effectively prevent short circuits of MOS chips and diffusion of glue, improve packaging reliability, reduce layering risks, enhance heat dissipation effect, and improve product stability and service life.
Smart Images
Figure CN223284982U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit packaging, and in particular to a lead frame structure. Background Art
[0002] As the chip carrier for integrated circuits, the lead frame secures the chip, protects internal components, transmits electrical signals, and dissipates heat. As the semiconductor industry continues to pursue cost reduction and multi-functionality, dual-chip and multi-chip packaging are also adopting lead frame structures.
[0003] The lead frame base island in the lead frame structure is usually fixed to the chip with glue. However, since the MOS chip is relatively thin, if there is too much glue when fixing it to the lower surface of the MOS chip, it is easy to overflow to the upper surface of the MOS chip, causing the S pole on the upper surface and the D pole on the lower surface to short-circuit, resulting in product failure. In addition, when fixing a main control chip on the lead frame base island, different glues will be used for the two chips due to different circuit connections. The two glues are easy to diffuse and contaminate on the same plane, and the lead frame structure will have the risk of delamination after reflow soldering. Utility Model Content
[0004] The present application provides a lead frame structure to solve the problem in the current lead frame structure that excessive amount of glue when fixing the lead frame base island and the MOS chip causes short circuit of the MOS chip, and the problem that the lead frame base island has two chips and the glue is easy to diffuse and cause stratification when different glues are used to fix the chips.
[0005] A lead frame structure, comprising:
[0006] The lead frame base island includes a mounting surface and a back surface opposite to the mounting surface, wherein one end of the mounting surface is provided with a plurality of first pins arranged at intervals, and the mounting surface includes an anti-overflow glue area, wherein the anti-overflow glue area is concavely provided with a plurality of anti-overflow glue grooves arranged at intervals;
[0007] The MOS chip is arranged in the anti-glue overflow area.
[0008] By adopting the above technical solution, the MOS chip is located in the anti-overflow glue area on the mounting surface, and the D pole on the lower surface is connected to the first pin through the lead frame base island. When the MOS chip is fixed to the lead frame base island by glue, excess glue can flow into the anti-overflow glue groove, preventing the D pole of the MOS chip and the S pole on the upper surface from being short-circuited through the glue, causing product failure.
[0009] In one embodiment, the anti-glue overflow grooves are square, circular or truncated cone-shaped, and are arranged at intervals along the length direction and width direction of the lead frame base island.
[0010] By adopting the above technical solution, the anti-overflow glue grooves are all square, so that the installation surface area between the anti-overflow glue grooves is larger, the contact area with the MOS chip is larger, and it is more conducive to fixing the MOS chip.
[0011] In one embodiment, conductive glue is provided on the mounting surface between the anti-overflow glue grooves, and the MOS chip is fixed to the mounting surface through the conductive glue.
[0012] By adopting the above technical solution, the conductive adhesive not only fixes the MOS chip to the mounting surface, but also connects the two to facilitate the realization of the circuit function.
[0013] In one embodiment, the area of the anti-glue overflow area is larger than the area of the MOS chip.
[0014] By adopting the above technical solution, the MOS chip is completely located in the anti-overflow glue area, and when glue overflows around the MOS chip, it can also enter the anti-overflow glue groove to avoid short circuit between the upper and lower surfaces of the MOS chip.
[0015] In one embodiment, the lead frame structure further includes a main control chip, which is disposed on the mounting surface. The mounting surface is further provided with an isolation groove, which can isolate the main control chip from the MOS chip.
[0016] By adopting the above technical solution, the lead frame structure uses a single-base island dual-chip process, the main control chip is fixed to the mounting surface with insulating glue, and the isolation groove can effectively isolate the main control chip from the MOS chip to prevent delamination caused by glue diffusion.
[0017] In one embodiment, the isolation groove is provided below the main control chip or between the main control chip and the anti-glue overflow area, and the main control chip is fixed to the mounting surface by insulating glue.
[0018] By adopting the above technical solution, the isolation groove can be arranged below the main control chip and surround the main control chip; or the isolation groove can be arranged between the main control chip and the anti-glue overflow area, both of which can prevent glue from spreading.
[0019] In one embodiment, the lead frame structure further includes a second pin and a third pin, and the second pin and the third pin are both arranged at an end of the lead frame base island opposite to the first pin and are spaced apart from the lead frame base island. The MOS chip and the main control chip can both be electrically connected to the second pin, and the main control chip is also electrically connected to the third pin.
[0020] By adopting the above technical solution, the lead frame structure includes a second pin and a third pin, and the MOS chip is connected to multiple second pins to facilitate the S-pole conduction on the surface; the main control chip can be connected to the second pin and the third pin.
[0021] In one embodiment, the lead frame structure further includes a heat sink, and the MOS chip can be electrically connected to the second pin through the heat sink; the heat sink can also be fixed to the back surface.
[0022] By adopting the above technical solution, the heat sink is connected to the MOS chip and the second pin, which not only has the function of conducting electricity, but also has the effect of heat dissipation. In addition, the heat sink can also be fixed to the back side, achieving the function of double-sided heat dissipation, which is more efficient.
[0023] In one embodiment, the first pin, the second pin and the third pin are each provided with a through hole.
[0024] By adopting the above technical solution, the through holes, anti-glue overflow grooves and isolation grooves on the pins can increase the contact area between the lead frame base island and the package body, making the package body more stable when encapsulating the lead frame base island.
[0025] In one embodiment, the lead frame structure further includes a stress layer, and the stress layer is provided on a side of the MOS chip away from the mounting surface.
[0026] By adopting the above technical solution, a stress layer is provided on the upper surface of the MOS chip, which can be used to prevent the MOS chip from being too thin and warping during the reflow soldering process; the stress layer is directly connected to the electrode on the upper surface of the MOS chip, thereby increasing the effective utilization area of the MOS chip and reducing the parasitic resistance of the device package.
[0027] In summary, this application has at least one beneficial effect:
[0028] 1. The MOS chip is located in the anti-overflow glue area on the mounting surface. The D pole on its lower surface is connected to the first pin through the lead frame base island. When the MOS chip is fixed to the lead frame base island with conductive glue, excess glue can flow into the anti-overflow glue groove, preventing the D pole of the MOS chip and the S pole on the upper surface from being short-circuited through the glue, causing product failure.
[0029] 2. The lead frame structure uses a single-island dual-chip process, so it also has a main control chip. The main control chip is fixed to the mounting surface with insulating glue. The isolation groove can effectively isolate the main control chip from the MOS chip to prevent delamination after the glue diffuses.
[0030] 3. The heat sink is connected to the MOS chip and the second pin, which not only has the function of conducting electricity, but also has the effect of heat dissipation. In addition, the heat sink can also be fixed to the back side, which plays the role of double-sided heat dissipation and is more efficient. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 1 is a schematic top view of a lead frame base island provided in an embodiment of the present application;
[0032] Figure 2 This is a schematic structural diagram of a lead frame structure including dual chips provided in an embodiment of the present application;
[0033] Figure 3 This is a schematic diagram of a structure in which a MOS chip is fixed to a second pin via a heat sink, as provided in an embodiment of the present application;
[0034] Figure 4 This is a side view schematic diagram of a lead frame structure provided in an embodiment of the present application;
[0035] Figure 5 This is a schematic top view of a MOS chip having a stress layer on its upper surface provided by the second embodiment of the present application;
[0036] Figure 6 This is a side structural schematic diagram of a lead frame structure provided in the second embodiment of the present application.
[0037] Explanation of the accompanying drawings: 1. Lead frame structure; 11. Lead frame base island; 111. Mounting surface; 112. Back side; 113. First pin; 114. Anti-overflow glue area; 115. Anti-overflow glue groove; 116. Conductive glue; 117. Isolation groove; 118. Insulating glue; 12. MOS chip; 121. Upper surface; 13. Main control chip; 14. Second pin; 15. Third pin; 16. Heat sink; 17. Through hole; 18. Stress layer. DETAILED DESCRIPTION
[0038] The following is combined with Figure 1-6 The lead frame structure provided in this application is further described in detail.
[0039] Example 1
[0040] See also Figure 1-6 The lead frame structure 1 provided in an embodiment of the present application includes a lead frame base island 11 and a MOS chip 12.
[0041] like Figure 1As shown, the lead frame base island 11 includes a mounting surface 111 and a back surface 112 opposite to the mounting surface 111. One end of the mounting surface 111 protrudes outward and is provided with a plurality of first pins 113 arranged at intervals. The mounting surface 111 includes an anti-overflow glue area 114, and the anti-overflow glue area 114 is concave with a plurality of anti-overflow glue grooves 115 arranged at intervals.
[0042] The leadframe base island 11 can be made of a metal material, such as copper, iron, or an aluminum alloy. Metal materials offer excellent electrical conductivity and mechanical strength, ensuring the structural stability and reliability of the leadframe base island 11. The mounting surface 111 is provided with a plurality of first pins 113. These first pins 113 can have a needle-like, flat, or wedge-shaped structure. The shape of these first pins 113 can be adjusted to achieve optimal electrical connection depending on the specific application. These first pins 113 can be made of a conductive metal, such as copper or a copper alloy, to ensure good electrical conductivity.
[0043] like Figure 2 As shown, the mounting surface 111 includes an anti-overflow glue area 114, which is recessed with a plurality of spaced anti-overflow glue grooves 115. Conductive glue 116 may be provided on the mounting surface 111 between two adjacent anti-overflow glue grooves 115. The MOS chip 12 is disposed in the anti-overflow glue area 114 and is fixed to the mounting surface 111 via the conductive glue 116. Specifically, the area of the anti-overflow glue area 114 needs to be larger than that of the MOS chip 12 to ensure that any conductive glue 116 overflowing from the surrounding areas of the MOS chip 12 when the MOS chip 12 is fixed to the mounting surface 111 flows into the anti-overflow glue grooves 115 to avoid short circuits.
[0044] The anti-overflow glue groove 115 can be square, circular or truncated cone-shaped, and is spaced apart along the length and width directions of the lead frame base island 11 to cover the entire anti-overflow glue area 114. In this embodiment, the anti-overflow glue area 114 and the anti-overflow glue groove 115 are both square, the anti-overflow glue area 114 can be 0.3mm away from the edge of the lead frame base island 11, the length, width and depth of the anti-overflow glue groove 115 can all be 0.1mm, and the spacing between two adjacent anti-overflow glue grooves 115 can also be 0.1mm. By adopting a square anti-overflow glue groove 115, the area of the mounting surface 111 between the anti-overflow glue grooves 115 is larger, which can be better fixed to the MOS chip 12. The anti-overflow glue groove 115 can be formed by mechanical processing to ensure the dimensional accuracy and shape stability of the groove. For example, if the processing speed needs to be increased, a stamping forming method can be adopted; if higher precision is required, a laser engraving method can be adopted.
[0045] Conductive adhesive 116 includes, but is not limited to, epoxy resin, silicone, or silver paste. The placement of conductive adhesive 116 can be designed based on actual application requirements to ensure effective electrical connection and securement between MOS chip 12 and mounting surface 111. In this embodiment, conductive adhesive 116 can be applied quickly and accurately using a dispensing method.
[0046] The lead frame structure 1 further includes a main control chip 13 , which is disposed on the mounting surface 111 . An isolation groove 117 is recessed on the mounting surface 111 . The isolation groove 117 can isolate the main control chip 13 from the MOS chip 12 .
[0047] Specifically, the main control chip 13 is fixed to the mounting surface 111 by insulating glue 118. The insulating glue 118 can be made of a material with good insulation properties, such as epoxy resin, polyurethane, etc. The placement of the insulating glue 118 can be precisely controlled using a glue gun to ensure the stability of the main control chip 13 after it is fixed.
[0048] The main control chip 13 can be disposed in the isolation groove 117 or the isolation groove 117 can be disposed between the main control chip 13 and the anti-glue overflow area 114. The isolation groove 117 has a certain depth and width to ensure the isolation effect between the main control chip 13 and the MOS chip 12. The shape of the isolation groove 117 can be square, circular, or irregular, and the specific design depends on the relative position relationship between the MOS chip 12 and the main control chip 13. In this embodiment, the main control chip 13 is disposed in the isolation groove 117. The isolation groove 117 is square and adapts to the main control chip 13. The length of the isolation groove 117 can be 1.7 mm, the width can be 2.3 mm, and the depth can be 0.05 mm. The isolation groove 117 is separated from the anti-glue overflow area 114 by 0.2 mm.
[0049] The leadframe base island 11 may further include a second pin 14 and a third pin 15. Both the second pin 14 and the third pin 15 are located on the end of the leadframe base island 11 opposite the first pin 113 and are spaced apart from the leadframe base island 11. In this embodiment, there are two second pins 14 and one third pin 15. The surface of the MOS chip 12 facing away from the mounting surface 111 is the top surface 121, which is connected to both second pins 14. The main control chip 13 can be connected to both the second pin 14 and the third pin 15. The second pin 14 and the third pin 15 can also be shaped like needles, flat plates, or wedges, and can be electrically connected to the MOS chip 12 and the main control chip 13 via wires or other means.
[0050] like Figure 3 and Figure 4As shown, the leadframe structure 1 further includes a heat sink 16, through which the MOS chip 12 can be electrically connected to the second pin 14. The heat sink 16 can also be fixed to the back surface 112. Specifically, the heat sink 16 can be a heat sink made of materials such as aluminum or copper, which has excellent thermal and electrical conductivity. This allows the heat generated by the MOS chip 12 during operation to be promptly transferred away, thereby improving the heat dissipation performance of the overall leadframe structure 1 and ensuring electrical continuity between the MOS chip 12 and the second pin 14. The heat sink 16 can be fixed to the back surface 112 by adhesive, welding, or riveting.
[0051] Specifically, through-holes 17 are defined in the first pin 113, the second pin 14, and the third pin 15. The primary function of through-holes 17 is to increase the contact area between the lead frame structure 1 and the package body when the package body is encapsulated, thereby enabling the package body to be more tightly secured to the lead frame structure 1. Through-holes 17 can be fabricated by drilling or laser drilling to ensure dimensional accuracy and shape stability. The diameter of through-holes 17 can be determined by actual application requirements and also ensures effective electrical connection between the pins and external components.
[0052] The working principle of this embodiment is as follows: by providing an anti-overflow glue groove 115 and an isolation groove 117 on the lead frame base island 11, the main control chip 13 and the MOS chip 12 are effectively prevented from overflowing when being fixed to the lead frame base island 11, and the MOS chip 12 will not short-circuit. At the same time, the insulating glue 118 and the conductive glue 116 will not diffuse into each other, further ensuring the electrical isolation between the main control chip 13 and the MOS chip 12, making delamination difficult. In addition, the structural design of the heat sink 16 and the through-holes 17 on the first pin 113, the second pin 14, and the third pin 15 all help to improve the heat dissipation performance and electrical connection reliability of the overall structure.
[0053] Example 2
[0054] like Figures 5 and 6 As shown, this embodiment differs from the above-described embodiments in that the leadframe base island 11 further includes a stress layer 18. The stress layer 18 is disposed on the upper surface 121 of the MOS chip 12, and the heat sink 16 can be disposed above the stress layer 18. The stress layer 18 can be made of a metal or polymer material to increase the overall structural stability of the leadframe structure 1 and reduce the stress effects on the MOS chip 12 during installation. The stress layer 18 can be fixed to the MOS chip 12 by bonding, such as using double-sided tape or epoxy resin adhesive.
[0055] Specifically, the provision of stress layer 18 can improve the stability of MOS chip 12 during installation and operation. In particular, during the packaging process, stress caused by temperature fluctuations or other external factors can cause deformation, cracking, or damage to MOS chip 12. Stress layer 18 acts as a buffer and vibration dampener, preventing warping and deformation of MOS chip 12, making it less susceptible to damage and thereby increasing the overall service life of the product. The thickness of stress layer 18 can be adjusted according to the actual application environment to further optimize the compressive strength of the entire structure.
[0056] In this embodiment, the isolation groove 117 is arranged between the main control chip 13 and the anti-overflow glue area 114. The insulating glue 118 overflowing when the main control chip 13 is fixed to the mounting surface 111 can also flow into the isolation groove 117, and the insulating glue 118 can also be prevented from diffusing into the anti-overflow glue area 114.
[0057] The working principle of this embodiment is as follows: by providing a stress layer 18 on the upper surface 121 of the MOS chip 12 of the lead frame, the overall stability and stress resistance of the lead frame structure 1 can be enhanced, and the impact of stress changes on the MOS chip 12 during installation can be reduced. This effectively improves the reliability and service life of the product.
[0058] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.
Claims
1. A lead frame structure, characterized in that: include: A lead frame base island (11) comprises a mounting surface (111) and a back surface (112) opposite to the mounting surface (111); a plurality of first pins (113) arranged at intervals are provided at one end of the mounting surface (111); the mounting surface (111) comprises an anti-glue overflow area (114); a plurality of anti-glue overflow grooves (115) arranged at intervals are concavely provided in the anti-glue overflow area (114); The MOS chip (12) is arranged in the anti-glue overflow area (114).
2. The lead frame structure according to claim 1, wherein: The anti-overflow glue grooves (115) are square, circular or truncated cone-shaped, and the anti-overflow glue grooves (115) are arranged at intervals along the length direction and width direction of the lead frame base island (11).
3. The lead frame structure according to claim 2, wherein: Conductive glue (116) is provided on the mounting surface (111) between the anti-overflow glue grooves (115), and the MOS chip (12) is fixed to the mounting surface (111) via the conductive glue (116).
4. The lead frame structure according to claim 3, wherein: The area of the anti-glue overflow area (114) is larger than the area of the MOS chip (12).
5. The lead frame structure according to claim 1, wherein: The lead frame structure (1) further comprises a main control chip (13), the main control chip (13) being arranged on the mounting surface (111), and the mounting surface (111) is further provided with an isolation groove (117), the isolation groove (117) being capable of isolating the main control chip (13) from the anti-glue overflow area (114).
6. The lead frame structure according to claim 5, characterized in that: The main control chip (13) is arranged in the isolation groove (117) or the isolation groove (117) is arranged between the main control chip (13) and the anti-overflow glue area (114), and the main control chip (13) is fixed to the mounting surface (111) by means of insulating glue (118).
7. The lead frame structure according to claim 5, characterized in that: The lead frame structure (1) further comprises a second pin (14) and a third pin (15), wherein the second pin (14) and the third pin (15) are both arranged on an end of the lead frame base island (11) opposite to the first pin (113) and are spaced apart from the lead frame base island (11); the MOS chip (12) and the main control chip (13) can both be electrically connected to the second pin (14), and the main control chip (13) is also electrically connected to the third pin (15).
8. The lead frame structure according to claim 7, characterized in that: The lead frame structure (1) further comprises a heat sink (16), through which the MOS chip (12) can be electrically connected to the second pin (14); the heat sink (16) can also be fixed to the back surface (112).
9. The lead frame structure according to claim 7, wherein: The first pin (113), the second pin (14) and the third pin (15) are all provided with through holes (17).
10. The lead frame structure according to claim 1, wherein: The lead frame structure (1) further comprises a stress layer (18), wherein the stress layer (18) is provided on a side of the MOS chip (12) away from the mounting surface (111).