Chip, glass substrate and electronic equipment

Abstract

The utility model discloses a chip, a glass substrate and an electronic device. The chip comprises a glass base material; a first copper layer formed on a surface of the glass substrate; the first copper layer is formed on the surface of the glass substrate, the second copper layer is formed on the first copper layer, the second copper layer copies the first copper layer, the projection of the first copper layer on the surface of the glass substrate covers the projection of the second copper layer on the surface of the glass substrate, and the preset thickness of the second copper layer is greater than the thickness of the first copper layer. The beneficial effects of the utility model are that the thin first copper layer is firstly formed on the surface of the base material, then the second copper layer which is thicker than the first copper layer is processed through electroplating, only the thin first copper layer needs to be processed during subsequent etching, the thick second copper layer does not need to be processed, and a high-precision and high-yield chip can be rapidly manufactured in a short time; and the production efficiency is improved.

Description

Technical Field

[0001] The present application belongs to the field of chip processing technology, and in particular relates to a chip, a glass substrate and an electronic device. Background Art

[0002] A chip, usually an integrated circuit (IC), is a tiny electronic device made of conductive and semiconductor materials. Chips integrate functional components such as circuits, sensors, or memory, and are connected to external power supplies and other electronic components via tiny circuit boards, pins, or through-holes. Chips use lithography to precisely engrave circuit patterns onto a substrate, and various functional areas are created through processes such as doping and etching. Chip production typically requires complex processes and sophisticated equipment, making them a core component of modern, highly integrated electronic products. They are currently widely used in a variety of electronic devices, from electronic watches and calculators to computers, communications equipment, and military weapon systems.

[0003] Currently, the basic chip manufacturing process is: depositing a conductive layer → electroplating the entire board → multiple etching steps → forming a conductive pattern → cutting. However, traditional chip manufacturing faces the following challenges: 1. Difficulty in etching: The conductive patterns on the chip require low resistance, so they must be thick. However, due to the small size of the chip board, the conductive pattern is formed by patterning the conductive layer. If the conductive pattern is thick, it is difficult to etch and separate the gaps between the conductive patterns. Furthermore, traditional processing methods require electroplating the entire chip board, which wastes plating materials and is time-consuming, making it unsuitable for industrial production.

[0004] Therefore, there is an urgent need for a chip that can reduce etching difficulty, improve graphic accuracy, and have a high product yield. Utility Model Content

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of this application is to provide a chip, a glass substrate and an electronic device to solve the problems of difficult etching, low graphic accuracy and low product yield during the production of existing chips.

[0006] To achieve the above-mentioned and other related purposes, the present application provides a chip, characterized in that it includes:

[0007] Glass substrate;

[0008] forming a first copper layer on a surface of a glass substrate;

[0009] A second copper layer is formed on the first copper layer, wherein the second copper layer conforms to the first copper layer, a projection of the first copper layer on the surface of the glass substrate covers a projection of the second copper layer on the surface of the glass substrate, and a thickness of the second copper layer is greater than a thickness of the first copper layer.

[0010] Preferably, the glass substrate is a plate-shaped glass substrate, the first copper layer is formed on the glass substrate, and the second copper layer is formed on the first copper layer.

[0011] Preferably, the ratio of the thickness of the first copper layer to the thickness of the second copper layer is in the range of 1:8-20.

[0012] More preferably, the ratio of the thickness of the first copper layer to the thickness of the second copper layer is in the range of 1:10.

[0013] Preferably, the first copper layer is a transition conductive layer made of copper material, and the thickness of the first copper layer is in the range of 7000-10000 angstroms.

[0014] More preferably, the thickness of the first copper layer is 8000 angstroms.

[0015] Preferably, the material of the second copper layer is the same as that of the first copper layer, and the material of the glass substrate is glass.

[0016] Preferably, the second copper layer is a functional circuit pattern made of copper material, with a thickness ranging from 2 to 25 μm.

[0017] More preferably, the thickness of the second copper layer is in the range of 10-15 μm.

[0018] More preferably, the thickness of the second copper layer is 15 μm.

[0019] Preferably, the first copper layer and the second copper layer are made of the same material. Since the chip substrate is a glass substrate that is not conductive, the first copper layer sputtered on the surface of the glass substrate serves as a cathode for electroplating, allowing subsequent electroplating to proceed normally. After the first copper layer is etched, the first copper layer and the second copper layer have the same shape. Moreover, since the first copper layer and the second copper layer are made of the same material, the first copper layer, in addition to serving as an electroplating seed layer, also forms a patterned functional circuit together with the second copper layer. The thinner first copper layer is directly formed on the surface of the glass substrate by magnetron sputtering, while the thicker second copper layer is formed by electroplating. The first copper layer and the second copper layer are formed in a step-by-step formation method. Therefore, the first copper layer in this embodiment can not only serve as an electroplating cathode, but also reduce the difficulty of etching. In addition, it can form a patterned functional circuit together with the second copper layer.

[0020] Preferably, an adhesion layer is provided between the surface of the glass substrate and the first copper layer.

[0021] Preferably, the adhesion layer is made of metal materials such as copper, gold, titanium, nickel, silver, platinum, chromium or alloys.

[0022] More preferably, the adhesion layer is a Ti layer made of Ti material, and the thickness of the Ti layer ranges from 500 to 4000 angstroms.

[0023] Preferably, the chip is an inductor chip, and on the plane where the surface of the glass substrate is located, the first copper layer and the second copper layer are in a coil shape, and the first copper layer and the second copper layer together constitute an inductor coil layer.

[0024] Preferably, the first copper layer in the chip prepared in the present application is a transition conductive layer, the second copper layer is a functional circuit pattern, and the thickness of the second copper layer is greater than that of the first copper layer. If the traditional chip preparation method is adopted, it is necessary to electroplate the second copper layer on the entire surface of the first copper layer, and then etch the second copper layer to process the functional circuit pattern. This not only greatly increases the difficulty of etching, but also greatly prolongs the etching time, thereby reducing the circuit accuracy on the second copper layer, thereby affecting the yield of the chip product. The present application coats photoresist on the surface of the first copper layer, and patterns the photoresist into a preset pattern, and then uses electroplating to directly electroplate the second copper layer in the preset pattern area. This method only requires etching the first copper layer, which can effectively ensure the processing accuracy of the circuit pattern and improve the product yield.

[0025] The present application also provides a glass substrate, characterized by comprising:

[0026] Glass substrate;

[0027] forming a first copper layer on a surface of the glass substrate; and

[0028] forming a second copper layer on the first copper layer, wherein the second copper layer conforms to the first copper layer, a projection of the first copper layer on the surface of the glass substrate covers a projection of the second copper layer on the surface of the glass substrate, and a thickness of the second copper layer is greater than a thickness of the first copper layer;

[0029] The glass substrate is in a plate shape and is used for cutting to form a plurality of the chips after a patterned first copper layer is formed on the surface.

[0030] The present application also provides an electronic device, characterized in that it includes the chip.

[0031] The present application also provides a chip manufacturing method for processing a second copper layer of a preset thickness on a glass substrate, characterized by comprising the following steps:

[0032] providing a glass substrate;

[0033] depositing a first copper layer on a surface of a glass substrate;

[0034] forming an insulating layer on the first copper layer, wherein the thickness of the insulating layer is the same as or similar to the preset thickness of the second copper layer;

[0035] forming a preset pattern on the insulating layer to expose the first copper layer in the preset pattern area;

[0036] Electroplating a second copper layer on the surface of the first copper layer in the preset pattern area;

[0037] removing the insulating layer to expose the first copper layer not covered by the second copper layer;

[0038] The first copper layer is etched based on the shape of the second copper layer to form a patterned first copper layer, wherein a projection of the first copper layer on the surface of the glass substrate covers a projection of the second copper layer on the surface of the glass substrate, and a predetermined thickness of the second copper layer is greater than a thickness of the first copper layer.

[0039] Preferably, the step of depositing a first copper layer on the surface of the glass substrate comprises:

[0040] depositing an adhesion layer on a surface of a glass substrate;

[0041] A first copper layer is sputtered over the adhesion layer.

[0042] Preferably, the step of forming the second copper layer by electroplating on the surface of the first copper layer in the preset pattern area includes:

[0043] The glass substrate with a preset pattern is placed in an electroplating device for electroplating, and the thickness of the second copper layer on the first copper layer is increased at a linear speed of 0.8 to 2.0 mm / min.

[0044] Preferably, the step of forming an insulating layer on the first copper layer includes:

[0045] Cleaning the first copper layer and etching the first copper layer with a chemical solution, wherein the etching thickness of the first copper layer is controlled to be 1000-3000 angstroms;

[0046] An insulating layer having a thickness that is the same as or similar to the preset thickness of the second copper layer is coated on the surface of the first copper layer by a coating machine.

[0047] Preferably, the insulating layer is a photoresist, and the step of forming a preset pattern on the insulating layer includes:

[0048] Expose the insulating layer (i.e., photoresist) using a photomask;

[0049] The exposed photoresist is removed by developing with a developer to obtain a preset pattern.

[0050] Preferably, the surface of the glass substrate includes an effective area and an ineffective area, and the ineffective area surrounds the effective area;

[0051] The step of depositing the first copper layer on the surface of the glass substrate is specifically as follows: forming the first copper layer in the effective area of ​​the glass substrate.

[0052] Preferably, the step of forming a second copper layer by electroplating on the surface of the first copper layer in the preset pattern area further comprises:

[0053] At the same time, an auxiliary shunt layer is formed by electroplating on the surface of the ineffective area.

[0054] Preferably, the step of forming a second copper layer by electroplating on the surface of the first copper layer in the preset pattern area further comprises:

[0055] The auxiliary shunt layer and the first copper layer in the invalid area are removed.

[0056] More preferably, the step of forming the auxiliary shunt layer by electroplating on the surface of the ineffective area is specifically as follows:

[0057] forming a shunt pattern on the insulating layer in the ineffective area so that the first copper layer in the shunt pattern area is exposed;

[0058] An auxiliary shunt layer is formed by electroplating on the surface of the first copper layer in the shunt pattern area.

[0059] Preferably, the area of ​​the effective region is the plated area, and the plated area accounts for 30-50% of the surface of the glass substrate.

[0060] The beneficial effects of the present application are: a thinner first copper layer is first formed on the surface of the substrate, and then a second copper layer thicker than the first copper layer is electroplated. During subsequent etching, only the thinner first copper layer needs to be processed, and there is no need to process the thicker second copper layer. High-precision, high-yield chips can be quickly manufactured in a short time, thereby improving production efficiency. The yield of chips prepared by this method is greatly improved, and production efficiency is significantly increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 Shown is a schematic structural diagram of a chip manufactured according to one embodiment of the present application.

[0062] Figure 2 Shown is a schematic structural diagram of the glass substrate described in this application.

[0063] Figure 3 Display as Figure 2 The partial AA cross-sectional diagram of FIG. 1 shows the positional relationship between the adhesion layer, the first copper layer and the glass substrate.

[0064] Figure 4 Shown is a schematic diagram of a chip manufacturing process according to an embodiment of the present application.

[0065] Figure 5Shown is a schematic diagram of a chip structure processed with an auxiliary shunt layer according to an embodiment of the present application.

[0066] Figure 6 Shown is a schematic diagram of a chip structure with an auxiliary shunt layer according to another embodiment of the present application.

[0067] Figure 7 Shown is a schematic diagram of a chip manufacturing process according to an embodiment of the present application.

[0068] Figure 8 Shown is a schematic diagram of the chip fabrication process according to one embodiment of the present application.

[0069] In the figure: 1 is a chip; 100 is a glass substrate; 110 is an active area; 120 is an inactive area; 111 is a first copper layer; 112 is a second copper layer; 113 is an adhesion layer; 114 is an auxiliary shunt layer; and 115 is an insulating layer. DETAILED DESCRIPTION

[0070] The following describes the embodiments of the present application through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present application from the disclosure herein. The present application may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present application.

[0071] It should be noted that the process equipment or devices not specifically specified in the following embodiments are all conventional equipment or devices in the art.

[0072] In addition, it should be understood that one or more method steps mentioned in this application do not exclude the presence of other method steps before or after the combination step or the insertion of other method steps between these explicitly mentioned steps, unless otherwise specified; it should also be understood that the combination connection relationship between one or more devices / apparatuses mentioned in this application does not exclude the presence of other devices / apparatuses before or after the combination device / apparatus or the insertion of other devices / apparatuses between these two explicitly mentioned devices / apparatuses, unless otherwise specified. Moreover, unless otherwise specified, the numbering of each method step is merely a convenient tool for identifying each method step, and is not intended to limit the order of arrangement of each method step or to define the scope of implementation of this application. Changes or adjustments to their relative relationships, without substantially changing the technical content, should also be considered as the scope of implementation of this application.

[0073] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0074] In the description of this application, it should be understood that the terms "upper", "lower", "left", "right", "inner", "outer", "axial", "circumferential", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application. In addition, features defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "multiple" means two or more.

[0075] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0076] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0077] The present application is further described below in conjunction with specific embodiments, but the protection scope of the present application is not limited thereto.

[0078] See also Figure 1 , the present application provides a chip 1, comprising:

[0079] Glass substrate 100;

[0080] A first copper layer 111 is formed on the glass substrate 100;

[0081] A second copper layer 112 is formed on the first copper layer 111, wherein the second copper layer 112 conforms to the first copper layer 111, a projection of the first copper layer 111 on the surface of the glass substrate 100 covers a projection of the second copper layer 112 on the surface of the glass substrate 100, and a thickness of the second copper layer 112 is greater than a thickness of the first copper layer 111.

[0082] In this embodiment, the glass substrate 100 is a plate-shaped glass substrate. The first copper layer 111 is formed on the glass substrate 1 , and the second copper layer 112 is formed on the first copper layer 111 .

[0083] In some embodiments of the present application, the ratio of the thickness of the first copper layer 111 to the thickness of the second copper layer 112 is in a range of 1:8 to 20, preferably 1:10.

[0084] In some embodiments of the present application, the first copper layer is a transition conductive layer made of copper material, and the thickness of the first copper layer is in the range of 7000-10000 angstroms, preferably 8000 angstroms.

[0085] In some embodiments of the present application, the material of the second copper layer is the same as that of the first copper layer, and the material of the glass substrate is glass.

[0086] In some embodiments of the present application, the second copper layer is a functional circuit pattern made of copper material, with a thickness ranging from 2 to 25 μm, preferably 10 to 15 μm, and most preferably 15 μm.

[0087] In some embodiments of the present application, the first copper layer 111 and the second copper layer 112 are made of the same material. Since the substrate of the chip 1 is a non-conductive glass substrate, the first copper layer 111 is sputtered onto the surface of the glass substrate 100 to serve as a cathode for electroplating, allowing subsequent electroplating to proceed normally. After etching, the first copper layer 111 and the second copper layer 112 have the same shape. Moreover, since the first copper layer 111 and the second copper layer 112 are made of the same material, the first copper layer 111 not only serves as an electroplating seed layer but also forms a patterned functional circuit together with the second copper layer 112. The thinner first copper layer 111 is formed directly on the surface of the glass substrate using magnetron sputtering, while the thicker second copper layer 112 is formed by electroplating. The first copper layer 111 and the second copper layer 112 are formed in a step-by-step manner. Therefore, in this embodiment, the first copper layer 111 not only serves as an electroplating cathode but also reduces the difficulty of etching. Furthermore, it can form a patterned functional circuit together with the second copper layer 112.

[0088] In some embodiments of the present application, an adhesion layer 113 is disposed between the surface of the glass substrate 100 and the first copper layer 111 .

[0089] In some embodiments of the present application, the adhesion layer 113 is made of metal materials such as copper, gold, titanium, nickel, silver, platinum, chromium or alloys.

[0090] In some embodiments of the present application, the adhesion layer 113 is a Ti layer made of Ti material, and the thickness of the Ti layer ranges from 500 to 4000 angstroms.

[0091] In some embodiments of the present application, the chip 1 is an inductor chip, and on the plane where the surface of the glass substrate 100 is located, the first copper layer 111 and the second copper layer 112 are coil-shaped, and the first copper layer 111 and the second copper layer 112 together constitute an inductor coil layer.

[0092] In some embodiments of the present application, the first copper layer 111 in the chip 1 prepared in the present application is a transition conductive layer, the second copper layer 112 is a functional circuit pattern, and the thickness of the second copper layer 112 is greater than the thickness of the first copper layer 111. If a traditional chip preparation method is used, it is necessary to electroplate the second copper layer 112 on the entire surface of the first copper layer 111, and then etch the second copper layer 112 to process the functional circuit pattern. This not only greatly increases the etching difficulty, but also greatly prolongs the etching time, thereby reducing the circuit accuracy on the second copper layer 112, thereby affecting the yield of the chip product. However, the present application coats a photoresist on the surface of the first copper layer 111, patterns the photoresist into a preset pattern, and then uses electroplating to directly electroplate the second copper layer in the preset pattern area. This method only requires etching the first copper layer, which can effectively ensure the processing accuracy of the circuit pattern and improve the product yield.

[0093] In some embodiments of the present application, an adhesion layer 113 is disposed between the surface of the glass substrate 100 and the first copper layer 111 , in order to improve the bonding strength between the first copper layer 111 and the glass substrate 100 .

[0094] In some embodiments of the present application, the first copper layer 111 and the second copper layer are made of the same material. Since the substrate of the chip is a glass substrate and is not conductive, the first copper layer 111 sputtered on the surface of the glass substrate serves as a cathode for electroplating, allowing subsequent electroplating to proceed normally. After the first copper layer 111 is etched, the first copper layer 111 and the second copper layer have the same shape. Moreover, since the first copper layer 111 and the second copper layer are made of the same material, in addition to serving as an electroplating seed layer, they also form a functional conductive layer together with the second copper layer. The thinner first copper layer 111 is directly formed on the surface of the glass substrate by magnetron sputtering, while the thicker second copper layer is formed by electroplating. The first copper layer 111 and the second copper layer are formed in a step-by-step manner, which can both play a conductive role and reduce the difficulty of etching.

[0095] That is, in this embodiment, the first copper layer 111 and the second copper layer are made of the same material. The transition conductive layer not only serves as the electroplating cathode material, but also serves as a part of the second copper layer, thereby reducing the resistance of the second copper layer. This also reduces the difficulty of etching during the manufacturing process.

[0096] In some embodiments of the present application, the glass substrate includes an active area 110 and an inactive area 120. The active area 110 is sequentially formed with an adhesion layer 113, a first copper layer 111, and a second copper layer 112 from bottom to top. An auxiliary shunt layer 114 is formed on the surface of the inactive area 120. The uniformity of the pattern electroplating is controlled to ±0.5μm. The area of ​​the active area is the plated area, which accounts for 30-50% of the glass substrate surface. This prevents excessive current during the electroplating process, which can cause board burns.

[0097] Figure 1 Chip 1, prepared in accordance with one embodiment of the present application, is an inductor chip. On the surface of the glass substrate, second copper layer 112 and first copper layer 111 are coiled together, forming the inductor coil layer. The inductor coil layer is fabricated in stages, requiring only the thinner transition conductive layer for subsequent etching and cutting, eliminating the need for processing the thicker functional circuit patterns. This allows for rapid production of high-precision, high-yield chips in a short period of time, improving production efficiency.

[0098] In other embodiments, the chip provided by this embodiment can also be a resistor chip, a capacitor chip, or other passive chips such as resonance chips. The corresponding second copper layer can be a resistor pattern, an electrode pattern, an inductor pattern, or a combination thereof.

[0099] like Figure 2 As shown, the present application also provides a glass substrate, comprising:

[0100] Glass substrate 100;

[0101] a first copper layer 111 formed on a surface of the adhesion layer 113; and

[0102] a second copper layer 112 formed on the first copper layer 111, wherein the second copper layer 112 conforms to the first copper layer 111, a projection of the first copper layer 111 on the surface of the glass substrate 100 covers a projection of the second copper layer 112 on the surface of the glass substrate 100, and a thickness of the second copper layer is greater than a thickness of the first copper layer 111;

[0103] The glass substrate is in a plate shape and is used for cutting into a plurality of chips after forming the patterned first copper layer 111 .

[0104] The present application also provides an electronic device, comprising the chip 1 manufactured in the present application.

[0105] See also Figure 8 , Figure 8 It is a flowchart of a manufacturing method of an embodiment of the chip of the present application. It should be noted that if there is substantially the same result, the method of the present application is not based on Figure 8 The process sequence shown is limited.

[0106] This application provides a chip manufacturing method, comprising the following steps:

[0107] Step S1 provides a glass substrate, and performs cleaning treatments such as polishing, grinding, cleaning, and drying on the surface of the glass substrate to remove dirt, impurities, and water stains on the surface of the glass substrate, thereby ensuring the cleanliness and flatness of the surface of the glass substrate and facilitating subsequent operations on the glass substrate.

[0108] The glass substrate in this application can be made of any known material without particular limitation, and can be a glass substrate, a ceramic substrate, a silicon substrate, or a polymer substrate. The glass substrate in this embodiment is preferred, but this application is not limited to using a glass substrate. Figure 4 As shown in (a), the glass substrate may be a rectangular plate structure. The thickness of the glass substrate ranges from 5 μm to 10 mm. Preferably, the thickness of the glass substrate ranges from 200 μm to 500 μm.

[0109] Step S2: Depositing an adhesion layer on the surface of the glass substrate.

[0110] like Figure 4 As shown in (b), in order to increase the bonding strength between the first copper layer 111 and the glass substrate, an adhesion layer 113 is formed between the surface of the glass substrate and the first copper layer 111. The adhesion layer 113 can be formed by magnetron sputtering. Before preparing the first copper layer, it is first deposited on the surface of the glass substrate. The adhesion layer 113 can be made of any conventionally known material without particular limitation, and can be copper, gold, titanium, nickel, silver, platinum, chromium, or an alloy, but is not limited to these metals. In this embodiment, the adhesion layer 113 is made of titanium, and the sputtering thickness of the titanium layer ranges from 500 to 4000 angstroms. In this manner, the bonding strength between the first copper layer 111 and the glass substrate can be increased. In other embodiments, the method for making the adhesion layer and the first copper layer 111 can also use other processes such as evaporation.

[0111] Specifically, the step of depositing an adhesion layer on the surface of the glass substrate includes:

[0112] The glass substrate with a cleaned surface is fed into a PVD line, and an adhesion layer 113 is sputtered on a single side of the surface of the glass substrate by a magnetron sputtering method, wherein the thickness of the adhesion layer 113 is in the range of 500-4000 angstroms.

[0113] S3 depositing a first copper layer 111 on the surface of the glass substrate.

[0114] Since the substrate of the chip 1 is a glass substrate and is not conductive, the first copper layer 111 sputtered on the surface of the glass substrate serves as a cathode for electroplating, so that subsequent electroplating can proceed normally. After the first copper layer 111 is etched, the first copper layer 111 and the second copper layer 112 have the same shape. Moreover, since the first copper layer 111 and the second copper layer 112 are made of the same material, the first copper layer 111 not only serves as an electroplating seed layer, but also forms a patterned functional circuit together with the second copper layer. The thinner first copper layer 111 is directly formed on the surface of the glass substrate by magnetron sputtering, while the thicker second copper layer is formed by electroplating. The first copper layer 111 and the second copper layer 112 are formed in a step-by-step manner. Therefore, the first copper layer 111 in this embodiment can not only serve as an electroplating cathode, but also reduce the difficulty of etching. In addition, it can form a patterned functional circuit layer together with the second copper layer 112.

[0115] Specifically, the step of depositing the first copper layer 111 on the surface of the glass substrate includes:

[0116] The cleaned glass substrate is fed into a PVD line, where a first copper layer 111 is deposited on the surface of the adhesion layer using magnetron sputtering. The thickness of first copper layer 111 ranges from 7,000 to 10,000 angstroms. This formation of first copper layer 111 on the adhesion layer serves as a seed layer (cathode material) for electroplating, ensuring smooth subsequent electroplating.

[0117] like Figure 4As shown in (c), a first copper layer 111 is deposited on the surface of the adhesion layer 113. The first copper layer 111 can be made of any known material without particular limitation, including copper, gold, titanium, nickel, silver, platinum, chromium, or alloys thereof, but is not limited to these metals. In this application, copper is preferred, being considered the most suitable circuit material based on a combination of resistivity, production cost, and physical stability. However, this application is not limited to copper. The thickness of the first copper layer 111 is 7,000-10,000 angstroms. In this embodiment, the first copper layer 111 is a transitional conductive layer with a thickness of 8,000 angstroms. The second copper layer 112 formed on the surface of the first copper layer 111 is a functional circuit pattern. The thickness of the second copper layer 112 is greater than that of the first copper layer 111. The first copper layer 111 and the second copper layer 112 together constitute the chip's patterned functional circuit layer. For example, in the case of an inductor chip, the first copper layer 111 and the second copper layer 112 together constitute the chip's inductor coil layer.

[0118] In another embodiment of the present application, the first copper layer 111 is directly deposited on the surface of the glass substrate 100 for manufacturing the chip by magnetron sputtering.

[0119] Step S4: forming an insulating layer 115 on the surface of the first copper layer 111 . The thickness of the insulating layer is the same as the predetermined thickness of the second copper layer.

[0120] like Figure 4 As shown in (d), the insulating layer 115 is formed on the surface of the first copper layer 111. The insulating layer 115 is made of a photoresist sprayed on the surface of the conductive layer. The thickness of the second copper layer is limited by the thickness of the preset pattern, which facilitates the subsequent process without etching a thick circuit layer. The thickness of the photoresist ranges from 2 to 25 μm. In this embodiment, the thickness of the photoresist is selected to be 15 μm. The desired thickness is achieved by controlling the spraying amount and the number of passes. The thickness of the preset pattern is 15 μm.

[0121] Specifically, the step of forming an insulating layer on the first copper layer 111 includes:

[0122] The first copper layer 111 is cleaned and etched with a chemical solution. The etched thickness of the first copper layer 111 is controlled to be 1000-3000 angstroms. The chemical solution is a sulfuric acid-hydrogen peroxide or sulfuric acid-sodium persulfate micro-etching solution used in conventional chemical etching processes. In this embodiment, the first copper layer 111 is treated with a sulfuric acid-hydrogen peroxide micro-etching solution containing 8% sulfuric acid, 5% hydrogen peroxide, 3% potassium dichromate, and the remainder water.

[0123] An insulating layer having a thickness that is the same as or similar to the preset thickness of the second copper layer is coated on the surface of the first copper layer 111 by a coating machine.

[0124] In step S5, a predetermined pattern is formed on the insulating layer 115 so that the first copper layer 111 in the predetermined pattern area is exposed.

[0125] A patterned photoresist method is used to process a preset pattern on the insulating layer. The patterned photoresist method is performed as follows:

[0126] The insulating layer is exposed once using a photomask, where the mask covers the exposure pattern to be formed and exposes the rest of the layer to light (such as ultraviolet rays).

[0127] The exposed insulating layer is immersed in a 2.38% developer solution for photochemical reaction and development. The unexposed photoresist is insoluble in the developer solution. This method can be used to remove the exposed photoresist and process the preset pattern on the insulating layer. The developer solution was purchased from Shanghai Ruiyi Trading Co., Ltd.; model number is AZ400K. Figure 4 As shown in (e), a patterned photoresist method is used to form a preset pattern on the insulating layer 115 to facilitate exposing the first copper layer 111 in the preset pattern area in preparation for subsequent electroplating.

[0128] Step S6: Electroplating forms a second copper layer on the surface of the first copper layer 111 in the preset pattern area.

[0129] The second copper layer 112 can be made of any known material without particular limitation, and may be copper, gold, titanium, nickel, silver, platinum, chromium, or alloys thereof, but is not limited to these metals. Copper is preferred in this application, and is considered the most suitable material for the circuit in terms of resistivity, production cost, physical stability, etc., but this application is not limited to copper. Specifically, this embodiment uses copper as an example, and is produced using pulse plating or DC plating. This application uses DC plating, and is specifically carried out in the following steps:

[0130] like Figure 4 As shown in (f), a second copper layer is formed by electroplating on the surface of the first copper layer 111 within the preset pattern area. In this step, the second copper layer can be formed by electroplating on the surface of the first copper layer 111. Specifically, the process is as follows: the glass substrate with the preset pattern produced in step S5 is placed in a vertical continuous electroplating apparatus for electroplating. Under the conditions of a nozzle pressure of 30Hz-50Hz and a current density of 0.5-2.5A / ㎡ (abbreviated as ASD), the second copper layer on the first copper layer 111 is thickened to a thickness of 15μm in a copper tank at a line speed of 1.0m / min. The glass substrate with the preset pattern produced is loaded onto a vertical electroplating line guide frame by a robot and thickened to a preset thickness in the copper tank at a line speed of 1.0m / min. Since the thickness of the preset pattern is determined based on the preset thickness of the second copper layer, the second copper layer is considered to have reached the preset thickness when it is flush with the preset pattern.

[0131] Step S7: removing the insulating layer to expose the first copper layer 111 not covered by the second copper layer;

[0132] Figure 4 As shown in (g), after the second copper layer reaches the required thickness, the insulating layer has completed its function. A stripping solution is then used to completely remove the remaining photoresist, exposing the first copper layer 111 not covered by the second copper layer for subsequent etching. In this embodiment, the mass fraction of the stripping solution is 3%-5%, the stripping temperature is 55-65°C, and the stripping speed is 0.8-2.0 m / min.

[0133] Step S8: Etching the first copper layer 111 and the adhesion layer 113 based on the shape of the second copper layer to form a patterned first copper layer 111 and an adhesion layer. The shapes of the patterned first copper layer 111 and the patterned adhesion layer are consistent with the shape of the second copper layer. The first copper layer 111 and the second copper layer 112 together constitute a patterned functional circuit layer. The projection of the first copper layer 111 on the front surface of the glass substrate covers the projection of the second copper layer on the front surface of the glass substrate. The preset thickness of the second copper layer 112 is greater than the thickness of the first copper layer 111. Figure 4 As shown in (h), the first copper layer 111 and the adhesion layer 113 are etched based on the shape of the second copper layer 112, so that the shapes of the first copper layer 111 and the adhesion layer 113 are consistent with the shape of the second copper layer. After etching, the first copper layer 111 and the second copper layer together constitute a patterned functional circuit layer. In this embodiment, a metal chloride etching process is used to etch the first copper layer 111 and the adhesion layer 113, where the specific gravity of copper chloride is 1.25-1.35 g / mL and the etching temperature is 48-55°C. After stripping the photoresist, the second copper layer protrudes from the conductive layer, and the first copper layer 111 needs to be etched. This application uses the first copper layer 111 as the copper layer for illustration. Generally, because the thickness of the second copper layer is 8 times or more than the thickness of the first copper layer 111, the second copper layer is the functional circuit pattern, and the first copper layer 111 is the transition conductive layer. Since the second copper layer has been prepared in advance by patterning the insulating layer rather than by whole-plate electroplating, there is no need to etch the second copper layer 112, but only the first copper layer 111 needs to be etched, which greatly reduces the etching time and ensures the processing accuracy of the circuit pattern.

[0134] like Figure 5 、 6As shown, the surface of the glass substrate 100 used to make the chip is divided into an active area 110 and an inactive area 120. The inactive area surrounds the active area, and an auxiliary shunt layer 114 is formed on the surface of the inactive area 120. In this embodiment, while electroplating the second copper layer on the surface of the first copper layer 111 in the preset pattern area, an auxiliary shunt layer is electroplated on the surface of the inactive area; after the electroplating is completed, the auxiliary shunt layer can be removed. The purpose of adding the auxiliary shunt layer 114 is to prevent excessive current from burning the board during the electroplating process. The purpose of the auxiliary shunt is to distribute the current during electroplating to avoid burning the board.

[0135] Specifically, the steps of electroplating the auxiliary shunt layer on the surface of the ineffective area are as follows:

[0136] forming a shunt pattern on the insulating layer in the ineffective area so that the first copper layer 111 in the shunt pattern area is exposed;

[0137] An auxiliary shunt layer is formed by electroplating on the surface of the first copper layer 111 in the shunt pattern area.

[0138] While making the second copper layer, in order to perform auxiliary shunt on the glass substrate at the same time, an auxiliary shunt layer can be processed at the same time. The surface of the invalid area is sequentially formed with an adhesion layer, a first copper layer 111 and an auxiliary shunt layer. The thickness of the auxiliary shunt layer is consistent with the thickness of the second copper layer. The auxiliary shunt layer is formed by simultaneous electroplating when the second copper layer is electroplated. The purpose of auxiliary shunt is to share the current during electroplating to avoid burning the board. The uniformity of graphic electroplating is controlled at ±0.5μm. The area of ​​the effective area is the plated area. The area of ​​the auxiliary shunt layer accounts for 30~50% of the plated area. If the plated area is too small, the board surface will be easily burned and rough. If the plated area is too large, the entire board surface will be electroplated or the current will be dispersed, resulting in local uneven electroplating.

[0139] Figure 7 The application is shown Figure 6 FIG. 1 is a schematic diagram of the chip manufacturing process. In this embodiment, the auxiliary shunt layer is processed while the second copper layer is being manufactured. Figure 7 The production process of the display Figure 4 The production process of the display is the same, but Figure 7 (e)~(h) and Figure 4 (e) to (h) in are slightly different, among which Figure 7 (e) shows that while forming a preset pattern on the insulating layer 115, a shunt pattern needs to be formed at the same time, in order to expose the first copper layer 111 in the shunt pattern area to prepare for the subsequent electroplating of an auxiliary shunt layer. Figure 7 In (f), while the second copper layer is formed by electroplating on the surface of the first copper layer 111 in the preset pattern area, an auxiliary shunt layer can be formed by electroplating on the surface of the first copper layer 111 in the shunt pattern area. Figure 7 (h) shows that the first copper layer 111 and the adhesion layer are etched based on the shape of the second copper layer and the shunt pattern. While forming the functional pattern, the auxiliary shunt layer can be formed.

[0140] Step S9 After forming the patterned first copper layer and the adhesive layer, the glass substrate is cut to form a plurality of chips. Figure 2 As shown, the glass substrate before cutting is in a plate shape, and multiple patterned functional circuit layers can be simultaneously produced on the surface of each glass substrate. The patterned functional circuit layers are arranged in a matrix form on the surface of the glass substrate, and etching seams are left between each patterned functional circuit layer to facilitate subsequent etching of the glass substrate without damaging the patterned functional circuit layers on the surface of the glass substrate.

[0141] The present application adopts the method of first forming a thin first copper layer 111 on the surface of the substrate, then coating the surface of the first copper layer 111 with photoresist, and patterning the photoresist into a preset pattern, and directly electroplating a second copper layer thicker than the first copper layer 111 in the preset pattern area by electroplating. During subsequent etching, only the thinner first copper layer 111 needs to be processed, and there is no need to process the thicker second copper layer. High-precision and high-yield chips can be quickly manufactured in a short time, thereby improving product yield and production efficiency.

[0142] The first copper layer 111, the first copper layer 111, the first copper layer 111, the first copper layer 111, the first copper layer 111, the first copper layer 111, the first copper layer 111, the first copper layer 111, the first copper layer 111, the first copper layer 111, the first copper layer 111, the first copper layer 111, serves as auxiliary evidence of the inventiveness of the claims of the present application. The present application also discloses the following important beneficial effects:

[0143] (1) Overcoming technical bias: In traditional chip manufacturing processes, organic materials such as semiconductor materials such as silicon are used as substrates to make chips. Glass, as an inorganic non-metallic material, has physical and chemical properties different from those of semiconductor materials. Glass substrates have good thermal stability and can remain stable in high-temperature environments. During the packaging process, they can withstand higher temperatures better than silicon substrates, thereby avoiding distortion or errors in signal transmission and reducing warping and deformation. In addition, the high flatness of glass substrates can ensure the accuracy of the signal transmission path. Although glass is relatively brittle, due to the small size of the chip in this application, it is not affected during chip production and subsequent use. In addition, glass has the characteristics of low interference with electromagnetic waves and good high-voltage resistance (tens of thousands of volts), making it a microelectronic device with broad application prospects.

[0144] (2) Expected benefits and commercial value: The cost of glass substrates is relatively low. Chips are core components of electronic components. The chips in this application made of glass substrates have been recognized by foreign customers and have great promotion value.

[0145] (3) This application solves a technical problem that people have been eager to solve but have never been able to solve successfully:

[0146] How to improve chip production efficiency is the core issue of effectively increasing chip production capacity. The chip production method established in this application addresses the problem of low production capacity. This method does not require electroplating the entire substrate, and subsequent etching and cutting only require processing the thinner first copper layer. High-precision, high-quality chips can be quickly manufactured in a short period of time, reducing costs while greatly improving production efficiency.

[0147] The above examples are for the purpose of illustrating the embodiments disclosed in the present application and are not to be construed as limiting the present application. In addition, the various modifications listed herein and the variations of the methods and compositions in the application will be apparent to those skilled in the art without departing from the scope and spirit of the present application. Although the present application has been specifically described with reference to various specific preferred embodiments of the present application, it should be understood that the present application should not be limited to these specific embodiments. In fact, various modifications apparent to those skilled in the art as described above will be included within the scope of the present application.

Claims

1. A chip, characterized in that: include: Glass substrate (100); a first copper layer (111) formed on the surface of the glass substrate (100); as well as A second copper layer (112) is formed on the first copper layer (111), wherein the second copper layer (112) is shaped like the first copper layer (111), a projection of the first copper layer (111) on the surface of the glass substrate (100) covers a projection of the second copper layer (112) on the surface of the glass substrate (100), and a predetermined thickness of the second copper layer (112) is greater than a thickness of the first copper layer (111).

2. A chip according to claim 1, characterized in that: The ratio of the thickness of the first copper layer (111) to the thickness of the second copper layer (112) ranges from 1:8 to 20.

3. A chip according to claim 2, characterized in that: The ratio of the thickness of the first copper layer (111) to the thickness of the second copper layer (112) is in the range of 1:

10.

4. The chip according to claim 1, wherein: The thickness of the first copper layer (111) ranges from 7000 to 10000 angstroms.

5. The chip according to claim 1, wherein: The thickness of the second copper layer (112) ranges from 2 to 25 μm.

6. The chip according to claim 1, wherein: An adhesion layer (113) is provided between the surface of the glass substrate (100) and the first copper layer (111).

7. A chip according to claim 6, characterized in that: The thickness of the adhesion layer (113) ranges from 500 to 4000 angstroms.

8. The chip according to claim 1, wherein: The chip is an inductor chip, and on the plane where the surface of the glass substrate (100) is located, the second copper layer (112) and the first copper layer (111) are in a coil shape, and the second copper layer and the first copper layer (111) together constitute an inductor coil layer.

9. A glass substrate, characterized in that: include: Glass substrate (100); a first copper layer (111) formed on the surface of the glass substrate (100); as well as a second copper layer (112) formed on the first copper layer (111), wherein the second copper layer (112) is shaped like the first copper layer (111), a projection of the first copper layer (111) on the surface of the glass substrate (100) covers a projection of the second copper layer (112) on the surface of the glass substrate (100), and a thickness of the second copper layer (112) is greater than a thickness of the first copper layer (111); The glass substrate is in a plate shape and is used for forming a patterned first copper layer (111) on the surface and then cutting the first copper layer (111) to form a plurality of chips as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the chip according to any one of claims 1 to 8.

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