Multilayer circuit board
Through the multi-layer circuit board structure, a circuit layer covered in the dielectric layer is first formed and connected by conductive vias, which solves the problem of difficult control of circuit fineness in the prior art, and realizes the thinner and high yield of the circuit board.
Patent Information
- Application Number
- CN202422486596.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-08-29
- Estimated Expiration
- 2034-10-15
AI Technical Summary
The fineness of the circuits on existing printed circuit boards is not easy to control, resulting in low process yield and difficulty in achieving thinning.
Using a multi-layer circuit board structure, the first top line layer is formed first and coated in the second dielectric layer. The conductive via holes penetrate through the multi-layer dielectric layer to ensure that the plating additive does not affect the quality of the first line layer, and the electronic devices are accommodated through the top accommodating cavity to realize the wiring connection of different layers.
The yield rate of the circuit layer is improved, the circuit board is reduced in thickness, while maintaining fine line connection capabilities.
Smart Images
Figure CN223285987U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a circuit board, in particular to a multi-layer circuit board. Background Art
[0002] Circuits on existing printed circuit boards (PCBs) are primarily formed by plating or etching. Common circuit fabrication methods include additive, subtractive, and semi-additive processes to meet varying circuit fabrication requirements. As the size of packaged devices soldered to PCBs continues to shrink, the circuits on existing PCBs used to connect these packaged devices are becoming increasingly refined. Consequently, existing PCBs often utilize a variety of these fabrication methods to complete overall circuit fabrication.
[0003] See also Figure 2 A conventional circuit board 80 includes at least one blind hole 81 and at least one through hole 82. During the manufacturing process of the circuit board 80, a metal M is electroplated near the at least one blind hole 81 to form a first circuit 83, and the metal M is electroplated near the at least one through hole 82 to form a second circuit 84. Since the position of the first circuit 83 corresponds to the position where the subsequent packaged device is connected, the area adjacent to the first circuit 83 is more refined than that adjacent to the second circuit 84. Although the first circuit 83 and the second circuit 84 can be manufactured simultaneously, if the total thickness of the circuit board 80 is increased, the first circuit 83 and the second circuit 84 must be manufactured separately using different electroplating additives.
[0004] However, if Figure 2 As shown, since the first circuit 83 and the second circuit 84 are formed on the same dielectric layer 85, it is difficult to control the effect of different plating additives on their corresponding circuits during the electroplating process. For example, to prevent the plating additive applied to the second circuit 84 from contaminating the first circuit 83, the first circuit 83 needs to be covered with photoresist during the electroplating process of the second circuit 84. When the photoresist is subsequently removed, the photoresist may remain on the first circuit 83 and contaminate the first circuit 83. Therefore, it is difficult to control the fineness of the circuit board 80, and thus it is difficult to control the process yield of the circuit board. Utility Model Content
[0005] In view of this, the main purpose of the present invention is to provide a multi-layer circuit board to overcome the problem that the fineness of circuits in existing circuit boards is difficult to control.
[0006] The utility model multilayer circuit board comprises:
[0007] a substrate;
[0008] a first top dielectric layer disposed on the substrate;
[0009] a first top circuit layer, disposed on the first top dielectric layer;
[0010] a second top dielectric layer, disposed on the first top circuit layer;
[0011] At least one top accommodating cavity is formed in the second top dielectric layer, and each top accommodating cavity exposes a portion of the first top circuit layer; and
[0012] At least one conductive via penetrates the substrate, the first top dielectric layer and the second top dielectric layer. Each conductive via has a top via ring formed on an upper surface of the second top dielectric layer.
[0013] During fabrication, the multi-layer circuit board of the present invention first forms the first top circuit layer. When forming the at least one conductive via, the first top circuit layer is encapsulated within the second top dielectric layer. Therefore, process additives used in the at least one conductive via will not affect the first top circuit layer, thereby stabilizing the quality of the first top circuit layer and improving the yield rate. Furthermore, the portion of the first top circuit layer exposed within the at least one top accommodating cavity can be used for soldering and securing other electronic devices (e.g., a packaged device), allowing the electronic device to be accommodated within the at least one top accommodating cavity. Compared to the prior art, the present invention can reduce the overall thickness (the thickness of the multi-layer circuit board of the present invention plus the thickness of the electronic device), achieving a thinner profile while simultaneously realizing circuit functions of different layers (the first top dielectric layer having the first top circuit layer for assembling delicate electronic devices, and the second top dielectric layer having the top via ring of the at least one conductive via for electrical connection to other electronic devices). BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E 、 Figure 1F 、 Figure 1G 、 Figure 1H 、 Figure 1I 、 Figure 1J This is a schematic diagram of the manufacturing process of the multi-layer circuit board of the utility model.
[0015] Figure 2 A schematic cross-sectional view of an existing circuit board. DETAILED DESCRIPTION
[0016] In order to understand the technical features and practical effects of the present invention in detail and to realize the present invention in accordance with the present invention, the following embodiments are further described in detail as shown in the drawings:
[0017] The present invention is a multi-layer circuit board, which may be a high-layer printed circuit board (HLC PCB). The following describes the structure of the multi-layer circuit board according to the present invention in conjunction with the production process.
[0018] See also Figure 1A , circuit layers are formed on opposite sides of a substrate 10. Specifically, the substrate 10 can be an organic resin material layer and has a first surface 100 and a second surface 101 opposite to each other. A top substrate circuit layer 11 is formed on the first surface 100, and a bottom substrate circuit layer 12 is formed on the second surface 101. For example, the top substrate circuit layer 11 and the bottom substrate circuit layer 12 can be formed by electroplating of metals such as copper and gold.
[0019] See also Figure 1B A first top dielectric layer 21 and a first bottom dielectric layer 22 are formed on the substrate 10. Specifically, the first top dielectric layer 21 is formed on the first surface 100 of the substrate 10 and the top substrate circuit layer 11, so that the top substrate circuit layer 11 is covered in the first top dielectric layer 21. The first bottom dielectric layer 22 is formed on the second surface 101 of the substrate 10 and the bottom substrate circuit layer 12, so that the bottom substrate circuit layer 12 is covered in the first bottom dielectric layer 22. For example, the first top dielectric layer 21 and the first bottom dielectric layer 22 can be formed by laminating, and the material of the first top dielectric layer 21 and the first bottom dielectric layer 22 can be BT resin (Bismaleimide). The first top dielectric layer 21 and the first bottom dielectric layer 22 may each be provided with a copper foil layer 23. The copper foil layer 23 is used to flatten the first top dielectric layer 21 and the first bottom dielectric layer 22 to facilitate subsequent circuit fabrication.
[0020] See also Figure 1C At least one blind hole 24 is formed in the first top dielectric layer 21 and the first bottom dielectric layer 22, respectively. The at least one blind hole 24 in the first top dielectric layer 21 exposes the top substrate circuit layer 11, and the at least one blind hole 24 in the first bottom dielectric layer 22 exposes the bottom substrate circuit layer 12. For example, the at least one blind hole 24 can be formed by laser, drilling, or the like.
[0021] See also Figure 1DA first top circuit layer 31 is formed on the first top dielectric layer 21, and a first bottom circuit layer 32 is formed on the first bottom dielectric layer 22. Specifically, the first top circuit layer 31 and the first bottom circuit layer 32 can also be formed by electroplating a metal such as copper or gold. During the electroplating process, the metal used for electroplating is also deposited on the inner wall of the at least one blind hole 24, so that at least one top conductive blind hole 33 is formed in the first top dielectric layer 21, and at least one bottom conductive blind hole 34 is formed in the first bottom dielectric layer 22. The at least one top conductive blind hole 33 electrically connects the top substrate circuit layer 11 and the first top circuit layer 31, and the at least one bottom conductive blind hole 34 electrically connects the bottom substrate circuit layer 12 and the first bottom circuit layer 32. In one embodiment of the present invention, the first top circuit layer 31, the first bottom circuit layer 32, the at least one top conductive blind hole 33, and the at least one bottom conductive blind hole 34 can be formed by a semi-additive process. The PCB is formed by using a modified semi-additive process or a hole-filling process or a resin-filled process.
[0022] See also Figure 1E A protective film A is respectively provided on the first top circuit layer 31 and the first bottom circuit layer 32, and the protective film A on the first top circuit layer 31 corresponds to the position of the at least one top conductive blind via 33, and the protective film A on the first bottom circuit layer 32 corresponds to the position of the at least one bottom conductive blind via 34, wherein the protective film A is removable, for example, a release film.
[0023] See also Figure 1F A second top dielectric layer 41 is formed on the first top dielectric layer 21, the first top wiring layer 31, and the protective film A. A second bottom dielectric layer 42 is formed on the first bottom dielectric layer 22, the first bottom wiring layer 32, and the protective film A. For example, the second top dielectric layer 41 and the second bottom dielectric layer 42 can also be formed by lamination. The materials of the second top dielectric layer 41 and the second bottom dielectric layer 42 can be, but are not limited to, BT resin (Bismaleimide Triazine), epoxy resin, polyoxyethylene / polyphenylene oxide (PPE / PPO), hydrocarbon, etc. A copper foil layer 43 can be disposed on each of the second top dielectric layer 41 and the second bottom dielectric layer 42. The copper foil layer 43 is used to flatten the second top dielectric layer 41 and the second bottom dielectric layer 42 to facilitate subsequent circuit fabrication.
[0024] See also Figure 1G, at least one through hole 50 is formed in the circuit board. Specifically, the at least one through hole 50 can penetrate the second top dielectric layer 41, the first top dielectric layer 21, the substrate 10, the first bottom dielectric layer 22 and the second bottom dielectric layer 42. For example, the at least one through hole 50 can be formed by laser, drilling, etc.
[0025] See also Figure 1H A second top wiring layer 61 is formed on the second top dielectric layer 41, and a second bottom wiring layer 62 is formed on the second bottom dielectric layer 42. Specifically, the second top wiring layer 61 and the second bottom wiring layer 62 can also be formed by electroplating a metal such as copper or gold. During the electroplating process, the aforementioned metal used for electroplating is also deposited on the inner wall of the at least one through hole 50, so that the at least one through hole 50 is at least one conductive through hole (plating through hole) 51. That is, the at least one conductive through hole 51 can be formed by drilling and electroplating. Each conductive through hole 51 has a top hole ring 510 and a bottom hole ring 511. The top hole ring 510 is formed on an upper surface 411 of the second top dielectric layer 41, and the bottom hole ring 511 is formed on a lower surface 421 of the second bottom dielectric layer 42.
[0026] The second top circuit layer 61 can be electrically connected to the top substrate circuit layer 11 through the at least one conductive through-hole 51, the second bottom circuit layer 62 can be electrically connected to the bottom substrate circuit layer 12 through the at least one conductive through-hole 51, and the top substrate circuit layer 11 can be electrically connected to the bottom substrate circuit layer 12 through the at least one conductive through-hole 51. In one embodiment of the present invention, the second top circuit layer 61, the second bottom circuit layer 62, and the at least one conductive through-hole 51 can be formed by drilling and electroplating.
[0027] Next, the protective film A on the first top circuit layer 31 and the second top dielectric layer 41 and the second top circuit layer 61 on the protective film A are removed, and the protective film A on the first bottom circuit layer 32 and the second bottom dielectric layer 42 and the second bottom circuit layer 62 on the protective film A are removed. Specifically, Figure 1I As shown, the second top dielectric layer 41 and the second top circuit layer 61 corresponding to the position of the protective film A can be laser cut or mechanically processed so that the protective film A on the first top circuit layer 31 and the second top dielectric layer 41 and the second top circuit layer 61 on the protective film A can together form a first cover body 71. Similarly, the second bottom dielectric layer 42 and the second bottom circuit layer 62 corresponding to the position of the protective film A can be laser cut or mechanically processed so that the protective film A on the first bottom circuit layer 32 and the second bottom dielectric layer 42 and the second bottom circuit layer 62 on the protective film A can together form a second cover body 72.
[0028] like Figure 1JAs shown, the first cover 71 and the second cover 72 are removed to form at least one top accommodating cavity 410 in the second top dielectric layer 41, and at least one bottom accommodating cavity 420 in the second bottom dielectric layer 42, and each top accommodating cavity 410 exposes a portion of the first top circuit layer 31, and each bottom accommodating cavity 420 exposes a portion of the first bottom circuit layer 32; in addition, since the protective film A on the first top circuit layer 31 originally corresponds to the position of the at least one top conductive blind via 33, and the protective film A on the first bottom circuit layer 32 originally corresponds to the position of the at least one bottom conductive blind via 34, after removing the first cover 71 and the second cover 72, the position of the at least one top accommodating cavity 410 corresponds to the position of the at least one top conductive blind via 33, and the position of the at least one bottom accommodating cavity 420 corresponds to the position of the at least one bottom conductive blind via 34.
[0029] According to the aforementioned Figures 1A to 1J After the production process is completed, the multi-layer circuit board of the present invention is formed (see Figure 1J ), the multi-layer circuit board of the present invention is first formed in the production of the first top circuit layer 31 and the first bottom circuit layer 32, and when forming the circuits other than the first top circuit layer 31 and the first bottom circuit layer 32 (for example, the at least one conductive through hole 51), the first top circuit layer 31 and the first bottom circuit layer 32 are respectively covered in the second top dielectric layer 41 and the second bottom dielectric layer 42, so that the process additives used for the circuits other than the first top circuit layer 31 and the first bottom circuit layer 32 will not affect the first top circuit layer 31 and the first bottom circuit layer 32, thereby stabilizing the quality of the first top circuit layer 31 and the first bottom circuit layer 32 and improving the yield rate; furthermore, the portion of the first top circuit layer 31 exposed in the at least one top accommodating cavity 410 is not affected by the process additives used for the circuits other than the first top circuit layer 31 and the first bottom circuit layer 32. The circuit layer 31 and the portion of the first bottom circuit layer 32 exposed in the at least one bottom accommodating cavity 420 can be used for soldering and fixing other electronic devices (such as packaging devices), so that the electronic devices can be accommodated in the at least one top accommodating cavity 410 and the at least one bottom accommodating cavity 420. Compared with the circuit board 80 described in the prior art, the present invention can reduce the overall thickness (the thickness of the multi-layer circuit board of the present invention plus the thickness of the electronic devices), achieve thinness and simultaneously realize the circuit functions of different layers (the first top dielectric layer 21 has the first top circuit layer 31 for assembling fine electronic devices, and the second top dielectric layer 41 has the top hole ring 510 of the at least one conductive through hole 51 for electrical connection of other electronic devices).
[0030] The above description merely describes the implementation methods or examples of the technical means employed by this utility model to solve the problem, and is not intended to limit the scope of implementation of this utility model patent. In other words, all equivalent variations and modifications that are consistent with the scope of this utility model patent, or that are made in accordance with the scope of this utility model patent, are covered by this utility model patent.
Claims
1. A multi-layer circuit board, characterized in that: Include: a substrate; a first top dielectric layer disposed on the substrate; a first top circuit layer, disposed on the first top dielectric layer; a second top dielectric layer, disposed on the first top circuit layer; At least one top accommodating cavity is formed in the second top dielectric layer, and each top accommodating cavity exposes a portion of the first top circuit layer; and At least one conductive via penetrates the substrate, the first top dielectric layer and the second top dielectric layer. Each conductive via has a top via ring formed on an upper surface of the second top dielectric layer.
2. The multilayer circuit board according to claim 1, wherein: A top substrate circuit layer is formed on the substrate, and the top substrate circuit layer is covered in the first top dielectric layer; At least one top conductive blind via is formed in the first top dielectric layer. The at least one top conductive blind via is electrically connected to the top substrate circuit layer and the first top circuit layer.
3. The multilayer circuit board according to claim 2, wherein: The position of the at least one top conductive blind hole corresponds to the position of the at least one top accommodating cavity.
4. The multilayer circuit board according to claim 2, wherein: Further including: A second top circuit layer is disposed on the second top dielectric layer. The second top circuit layer is electrically connected to the top substrate circuit layer through the at least one conductive through hole.
5. The multilayer circuit board according to claim 1, wherein: The substrate has a first surface and a second surface opposite to each other, the first top dielectric layer is disposed on the first surface, and the circuit board further comprises: a first bottom dielectric layer disposed on the second surface of the substrate; a first bottom circuit layer, disposed on the first bottom dielectric layer; a second bottom dielectric layer disposed on the first bottom circuit layer; and At least one bottom accommodating cavity is formed in the second bottom dielectric layer, and each bottom accommodating cavity exposes a portion of the first bottom circuit layer.
6. The multilayer circuit board according to claim 5, wherein: The at least one conductive via further penetrates the first bottom dielectric layer and the second bottom dielectric layer; Each conductive through hole also has a bottom hole ring, and the bottom hole ring is formed on a lower surface of the second bottom dielectric layer.
7. The multilayer circuit board according to claim 5, wherein: A bottom substrate circuit layer is formed on the second surface of the substrate, and the bottom substrate circuit layer is covered in the first bottom dielectric layer; At least one bottom conductive blind hole is formed in the first bottom dielectric layer. The at least one bottom conductive blind hole is electrically connected to the bottom substrate circuit layer and the first bottom circuit layer.
8. The multi-layer circuit board according to claim 7, wherein: The position of the at least one bottom conductive blind hole corresponds to the position of the at least one bottom accommodating cavity.
9. The multi-layer circuit board according to claim 7, wherein: Further including: A second bottom circuit layer is disposed on the second bottom dielectric layer. The second bottom circuit layer is electrically connected to the bottom substrate circuit layer through the at least one conductive through hole.
10. The multi-layer circuit board according to claim 1, wherein: A top substrate circuit layer and a bottom substrate circuit layer are formed on opposite sides of the substrate. The top substrate circuit layer is electrically connected to the bottom substrate circuit layer through the at least one conductive through hole.