Semiconductor structure

Abstract

In some embodiments, a semiconductor structure includes a substrate, a first transistor, a second transistor, and a first gate contact. The first transistor is located above the substrate, the first transistor belongs to an inductive amplifier or a power connector of the memory element, and the first transistor comprises a channel region, a gate structure surrounding the channel region and a plurality of source / drain regions located on opposite sides of the gate structure. The second transistor is positioned above the first transistor and belongs to a memory unit; the semiconductor device includes a gate electrode, a gate dielectric layer over the gate electrode, an indium gallium zinc oxide layer over the gate dielectric layer, a first titanium nitride source / drain electrode formed on a first side of the indium gallium zinc oxide layer, and a second titanium nitride source / drain electrode formed on a second side of the indium gallium zinc oxide layer. The first gate contact is over the gate electrode. From an upper view, the indium gallium zinc oxide layer surrounds the first gate contact.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure. Background Art

[0002] The manufacturing of semiconductor integrated circuits (ICs) has experienced rapid progress. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. However, these advances have increased the complexity of processing and manufacturing ICs, and to achieve these advances, similar developments in IC processing and manufacturing are required.

[0003] In the evolution of integrated circuits, functional density (i.e., the number of interconnected elements per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be formed using a manufacturing process) has decreased. This scaling process generally brings benefits by increasing production efficiency and reducing associated costs. This scaling also results in relatively high power dissipation values, which can be addressed by using low-power components, such as complementary metal-oxide-semiconductor (CMOS) components. Utility Model Content

[0004] In some embodiments, a semiconductor structure includes a substrate, a first transistor, a second transistor, and a first gate contact. The first transistor is located above the substrate and is a sense amplifier or power supply terminal of a memory device. The first transistor includes a channel region, a gate structure surrounding the channel region, and a plurality of source / drain regions located on opposite sides of the gate structure. The second transistor is located above the first transistor and is a memory cell. The second transistor includes a gate electrode, a gate dielectric layer located above the gate electrode, an indium gallium zinc oxide layer located above the gate dielectric layer, a first titanium nitride source / drain electrode formed on a first side of the indium gallium zinc oxide layer, and a second titanium nitride source / drain electrode formed on a second side of the indium gallium zinc oxide layer. The first gate contact is located above the gate electrode. From a top view, the indium gallium zinc oxide layer surrounds the first gate contact.

[0005] In some embodiments, a semiconductor structure includes a substrate, a first active region, a second active region, a first gate structure, a second gate structure, a first gate contact, and a second gate contact. The first active region is located in a memory region of the substrate. The second active region is located in a peripheral region of the substrate. The first gate structure spans the first active region, wherein the first gate structure belongs to a first transistor, and the first transistor is of a first conductivity type. The second gate structure spans the second active region, wherein the second gate structure belongs to a second transistor, and the second transistor is of a second conductivity type opposite to the first conductivity type. The first gate contact is located above the first gate structure, wherein the first gate contact overlaps the first active region. The second gate contact is located above the second gate structure, wherein the second gate contact does not overlap the second active region.

[0006] In some embodiments, a semiconductor structure includes a semiconductor substrate, a plurality of fin structures, a first gate strip structure, a second gate strip structure, a plurality of source / drain structures, a first gate contact, and a second gate contact. The plurality of fin structures extend upward from the semiconductor substrate within a memory bit cell. The first gate strip structure extends across the plurality of fin structures. The second gate strip structure extends across the plurality of fin structures. The plurality of source / drain structures are located on the plurality of fin structures. The first gate contact is located above the first gate strip structure, wherein, from a top view, the first gate contact is located within a region defined by a first outer edge of a first outermost of the plurality of fin structures and a second outer edge of a second outermost of the plurality of fin structures, the second outermost being located on an opposite side of the first outermost. The second gate contact is located above the second gate strip structure, wherein, from a top view, the second gate contact is located outside the region defined by the first outer edge and the second outer edge of the first outermost and second outermost fin structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A A top view of a memory system illustrating a semiconductor structure according to some embodiments of the present disclosure is shown;

[0009] Figure 1BA diagram illustrating threshold voltage characteristics of an n-channel metal-oxide-semiconductor (NMOS) transistor considering different gate contact positions on the transistor gate structure according to some embodiments of the present disclosure is shown;

[0010] Figure 1C A diagram illustrating threshold voltage characteristics of a p-channel metal-oxide-semiconductor (PMOS) transistor considering different gate contact positions on the transistor gate structure according to some embodiments of the present disclosure is shown;

[0011] Figure 1D A circuit diagram of an electronic fuse (efuse) memory cell according to some embodiments of the present disclosure is shown;

[0012] Figure 1E 、 Figure 1H and Figure 1K depicts perspective views of exemplary fin-like field-effect transistor (FinFET) devices, nano-FET devices, and thin film transistor (TFT) devices according to some embodiments of the present disclosure;

[0013] Figure 1F and Figure 1G Some embodiments of the present disclosure are shown Figure 1A Cross-sectional views of the semiconductor structure obtained by reference cross section AA', reference cross section BB', reference cross section CC', reference cross section DD', reference cross section EE', and reference cross section FF';

[0014] Figure 1I and Figure 1L Some embodiments of the present disclosure are shown. Figure 1E A corresponding cross-sectional view of a semiconductor structure having a nano-field effect transistor element and a thin film transistor element;

[0015] Figure 1J and Figure 1M Some embodiments of the present disclosure are shown. Figure 1F A corresponding cross-sectional view of a semiconductor structure having a nano-field effect transistor element and a thin film transistor element;

[0016] Figure 1N 、 Figure 1P and Figure 1Rdepicts a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure;

[0017] Figure 1O and Figure 1Q Some embodiments of the present disclosure are shown. Figure 1N and Figure 1P A local enlarged view of the semiconductor structure corresponding to regions C7 and C8;

[0018] Figures 2A to 7B depicts a cross-sectional view of an intermediate stage of forming a semiconductor structure according to some embodiments of the present disclosure;

[0019] Figure 8A A circuit diagram of an anti-fuse memory cell according to some embodiments of the present disclosure is shown;

[0020] Figures 8B to 10 depicts different views of a bit cell in a memory array according to some embodiments of the present disclosure;

[0021] Figures 11A to 14 depicts different views of a semiconductor structure in a peripheral area of ​​a memory system according to some embodiments of the present disclosure;

[0022] Figure 15 A diagram illustrating an electronic design automation (EDA) system according to some embodiments of the present disclosure is shown;

[0023] Figure 16 is a block diagram of an integrated circuit manufacturing system and related integrated circuit manufacturing process according to some embodiments of the present disclosure.

[0024]

Explanation of symbols

[0025] 100:Memory system

[0026] 101:Memory array area

[0027] 102: Peripheral circuit area

[0028] 103: bit unit

[0029] 103a: bit unit

[0030] 103b: bit unit

[0031] 103c: bit unit

[0032] 104: Fuse resistor

[0033] 104a: bottom electrode layer

[0034] 104b: Fuse layer

[0035] 104c: top electrode layer

[0036] 110: Base material

[0037] 111: Isolation Structure

[0038] 112a: Channel area

[0039] 112b: Channel area

[0040] 112c: Channel area

[0041] 113: Gate spacer structure

[0042] 114: Sacrificial gate dielectric layer

[0043] 115: Sacrificial gate

[0044] 116: Gate dielectric layer

[0045] 117: Gate electrode layer

[0046] 118: interlayer dielectric layer

[0047] 128: interlayer dielectric layer

[0048] 130: Sacrificial gate structure

[0049] 210: Base material

[0050] 211: Dielectric isolation structure

[0051] 213: Gate spacer structure

[0052] 214: Fin structure

[0053] 216: Gate dielectric layer

[0054] 217: Gate electrode layer

[0055] 219: Internal compartment structure

[0056] 228: interlayer dielectric layer

[0057] 310: Base material

[0058] 312a: Channel area

[0059] 312b: Channel area

[0060] 312c: Channel area

[0061] 316: Gate dielectric layer

[0062] 317: Gate electrode layer

[0063] 320: Insulation layer

[0064] 322: Source / drain through hole

[0065] 330: Back-end process wiring structure

[0066] 331: dielectric layer

[0067] 332: dielectric layer

[0068] 334:Metal wiring

[0069] 335:Metal wiring

[0070] 336: dielectric layer

[0071] 412a: Channel area

[0072] 512a: Channel area

[0073] 516: Gate dielectric layer

[0074] 517: Gate electrode layer

[0075] 612a: Channel area

[0076] 616: Gate dielectric layer

[0077] 617: Gate electrode layer

[0078] 710: Gate terminal

[0079] 711: First terminal

[0080] 712: Second terminal

[0081] 720: Gate terminal

[0082] 721: First terminal

[0083] 722: Second terminal

[0084] 1600: Electronic Design Automation System

[0085] 1602: Crafts

[0086] 1604: Computer readable storage medium

[0087] 1606: Instructions

[0088] 1607: Design Layout

[0089] 1608: Bus

[0090] 1609: Design Rule Checking Platform

[0091] 1610: Input / Output Interface

[0092] 1612: Network interface

[0093] 1614: Network

[0094] 1616: User Interface

[0095] 1620: Integrated Circuit Manufacturing

[0096] 1750: Integrated Circuit Manufacturing

[0097] 1622: Integrated Circuit Manufacturing Tools

[0098] 1630:Mask Factory

[0099] 1730: Mask Factory

[0100] 1632:Mask creation tools

[0101] 1700: Integrated Circuit Manufacturing System

[0102] 1720: Design

[0103] 1722: Design Layout

[0104] 1732: Data Preparation

[0105] 1744:Mask Manufacturing

[0106] 1745:Light Mask

[0107] 1752: Wafer

[0108] 1753: Wafer

[0109] A-A': cross section

[0110] B11: Edge

[0111] B11': Edge

[0112] B11”: Edge

[0113] B12: Edge

[0114] B12': Edge

[0115] B12": Edge

[0116] B13: Edge

[0117] B13': Edge

[0118] B13”: Edge

[0119] B-B': cross section

[0120] B2-B2': cross section

[0121] B3-B3': Cross section

[0122] BL: bit line

[0123] BL11: bit line

[0124] C1: Curve

[0125] C2: Curve

[0126] C3: Curve

[0127] C4: Curve

[0128] C5: Curve

[0129] C6: Curve

[0130] C7: Area

[0131] C8: Area

[0132] C-C': cross section

[0133] C2-C2': cross section

[0134] C3-C3': cross section

[0135] D1: Distance

[0136] D2: Distance

[0137] D3: Distance

[0138] D4: Distance

[0139] D5: Distance

[0140] D6: Distance

[0141] D7: Distance

[0142] D5': distance

[0143] D6': Distance

[0144] D7': Distance

[0145] D-D': cross section

[0146] D2-D2': cross section

[0147] D3-D3': cross section

[0148] E-E': cross section

[0149] E2-E2': cross section

[0150] E3-E3': Cross section

[0151] F-F': cross section

[0152] G11: Gate structure

[0153] G11': Gate structure

[0154] G11": Gate structure

[0155] G12: Gate structure

[0156] G12': Gate structure

[0157] G12": Gate structure

[0158] G13: Gate structure

[0159] G13': Gate structure

[0160] G13": Gate structure

[0161] G21": Gate structure

[0162] G31": Gate structure

[0163] G41": Gate structure

[0164] MD11: Source / Drain Contact

[0165] MD11': Source / Drain Contact

[0166] MD11": Source / Drain Contact

[0167] MD12: Source / Drain Contact

[0168] MD12': Source / Drain Contact

[0169] MD12”: Source / Drain Contact

[0170] MD13': Source / Drain Contact

[0171] MD13': Source / Drain Contact

[0172] MD13”: Source / Drain Contact

[0173] MD21": Source / Drain Contacts

[0174] MD31”: Source / Drain Contact

[0175] MD41": Source / Drain Contacts

[0176] OD11: Active region

[0177] OD11': active region

[0178] OD11": Active area

[0179] OD12: Active area

[0180] OD12': active region

[0181] OD12": Active area

[0182] OD13: Active region

[0183] OD13': active region

[0184] OD13": Active area

[0185] OD21": Active area

[0186] OD31": Active area

[0187] OD41": Active area

[0188] R1: vertical size

[0189] R3: Vertical size

[0190] R4: vertical size

[0191] R5: vertical size

[0192] R6: Vertical size

[0193] S / D11: Source / Drain region

[0194] S / D11': Source / Drain region

[0195] S / D11”: Source / Drain region

[0196] S / D12: Source / Drain region

[0197] S / D12': Source / Drain region

[0198] S / D12”: Source / Drain region

[0199] S / D13: Source / Drain region

[0200] S / D13': Source / Drain region

[0201] S / D13”: Source / Drain region

[0202] S / D21”: Source / Drain region

[0203] S / D31”: Source / Drain region

[0204] S / D41”: Source / Drain region

[0205] SL: Source

[0206] SL11: Source line

[0207] T11: Transistor

[0208] T11': Transistor

[0209] T11": Transistor

[0210] T12: Transistor

[0211] T12': Transistor

[0212] T12": Transistor

[0213] T13: Transistor

[0214] T13': Transistor

[0215] T13": Transistor

[0216] T21": Transistor

[0217] T31": Transistor

[0218] T41": Transistor

[0219] TR : Read transistor

[0220] TP: Programmed Transistor

[0221] VG11: Gate contact

[0222] VG11': Gate contact

[0223] VG11": Gate contact

[0224] VG12: Gate contact

[0225] VG12': Gate contact

[0226] VG12": Gate contact

[0227] VG13: Gate contact

[0228] VG13': Gate contact

[0229] VG13": Gate contact

[0230] W1: lateral dimension

[0231] WL11: word line

[0232] WLP: Programming Word Line

[0233] WLR: Read word line DETAILED DESCRIPTION

[0234] Many different embodiments or examples for implementing the different features of the present disclosure are provided below. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and do not limit the scope of the present disclosure. For example, in the description below, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or text in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0235] Furthermore, spatially relative terms (e.g., "below," "beneath," "above," "over," and related terms) are used herein to simply describe the relationship of an element or feature as shown in the figures to another element or feature. During use or operation, these spatially relative terms encompass various orientations of the elements in addition to the orientation depicted in the figures. Furthermore, the elements may be rotated (90 degrees or other angles), and the spatially relative descriptors used herein should be interpreted accordingly.

[0236] As used herein, "about," "approximately," "substantially" may mean within 20%, within 10%, or within 5% of a given value or range. However, one skilled in the art will understand that the values ​​or ranges recited throughout this description are merely examples and may decrease as integrated circuits scale. The values ​​disclosed herein are approximate, meaning that the terms "about," "approximately," "substantially," or the like can be inferred unless explicitly stated.

[0237] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as idealized or overly formalized unless expressly defined herein.

[0238] The embodiments of the present disclosure relate to, but are not limited to, fin-like field-effect transistor (FinFET) devices. For example, the FinFET device can be a complementary metal-oxide-semiconductor (CMOS) device, including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will use one or more FinFET examples to illustrate various embodiments of the present disclosure. However, it is understood that the application should not be limited to a specific type of device unless otherwise stated.

[0239] The fin structure can be patterned using any suitable method. For example, the fin structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the formation of patterns having, for example, a smaller pitch than can be achieved using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins.

[0240] The gate all around (GAA) transistor structure can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the formation of patterns having, for example, a smaller pitch than can be obtained with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the gate surround structure.

[0241] The present disclosure relates to integrated circuit (IC) structures and methods for forming the same. More specifically, some embodiments of the present disclosure relate to gate-wrap devices including improved isolation structures to reduce channel-to-substrate current leakage. A gate-wrap device includes a device having a gate structure or portion thereof formed on four sides of a channel region (e.g., surrounding a portion of the channel region). The channel region of the gate-wrap device may include a nanosheet channel, a rod-shaped channel, and / or other suitable channel configurations. In some embodiments, the channel region of the gate-wrap device may include multiple horizontal nanosheets or vertically spaced horizontal bars, such that the gate-wrap device is a stacked horizontal gate-wrap (S-HGAA) device. The gate-wrap device disclosed herein includes a p-type metal oxide semiconductor (MOSFET) gate-wrap device and an n-type metal oxide semiconductor (MOSFET) gate-wrap device stacked together. Furthermore, the gate-wrap device may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure or multiple gate structures. Persons of ordinary skill in the art will recognize other examples of semiconductor devices that may benefit from various aspects of the present disclosure. In some embodiments, a nanosheet may be interchangeably referred to as a nanowire, a nanoslab, a nanoring, or a nanostructure having nanoscale dimensions (e.g., a few nanometers), depending on its geometry. Furthermore, embodiments of the present disclosure may also be applied to various metal oxide semiconductor transistors (e.g., complementary field effect transistors (CFETs) and fin field effect transistors).

[0242] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects of use in planar components, such as planar FETs or FinFETs. For example, a FinFET may include fin structures on a substrate that serve as a channel region for the FinFET. Similarly, a planar FET may include a substrate, a portion of which serves as a channel region for the planar FET.

[0243] In the evolution of integrated circuits, components embedded in or around N-type / P-type metal oxide semiconductor (N / PMOS) memory cell areas may use the same gate contact (VG) placement method. Maintaining a consistent gate contact placement method across different components in a memory system can result in insufficient design flexibility. Each component in a memory system may have unique operating requirements that may not be consistent with a uniform gate contact placement method. This can limit the layout designer's ability to effectively balance component performance (e.g., power efficiency, read / write speeds, and data retention).

[0244] Thus, various embodiments of the present disclosure provide flexibility in the location of gate contacts within memory bit cells and certain peripheral components. For example, in an n-type metal oxide semiconductor (NMOS) memory cell, the gate contact can be located within the active region, as viewed from above. Furthermore, this disclosure enables three-dimensional (3D) stacking of indium gallium zinc oxide (IGZO) thin film transistor (TFT) components. This configuration can provide increased threshold voltage shift, thereby increasing cell current or reducing cell leakage. Furthermore, for a peripheral sense amplifier (e.g., including a PMOS transistor), the gate contact can be located within the active region, as viewed from above. This configuration can provide reduced threshold voltage shift, thereby expanding the read window and enhancing the performance of the sense amplifier. Furthermore, for a power header (e.g., including NMOS / PMOS transistors), the gate contact can be located outside the active region, as viewed from above. The aforementioned configuration can provide threshold voltage stability, thereby contributing to efficient power utilization in the memory system.

[0245] refer to Figure 1A . Figure 1AA top view of a memory system 100 including a semiconductor structure according to some embodiments of the present disclosure is shown. Memory system 100 may include a memory array region 101 and a peripheral circuit region 102 for accessing one or more portions of memory array region 101. Peripheral circuit region 102 includes components for reading from and / or writing to one or more portions of memory array region 101. In some embodiments, the peripheral circuit area 102 may include sense amplifiers, power headers for providing power to the various units in the peripheral circuit area 102, write driver circuitry connected to the bit lines, write logic, write assist circuitry, built-in self-test (BIST) / data input circuitry, pre-charge / equalization circuitry for the bit lines, read column multiplexers, pre-charge / equalization circuitry for the bit lines of the memory array area 101, data output circuitry, and column redundancy circuitry. Other structures and configurations of the peripheral circuit area 102 are within the scope of the present disclosure. Figure 1A As shown, memory system 100 may include at least one transistor T11 in a bit-cell 103 and at least one transistor T12 and at least one transistor T13 in a peripheral circuit region 102. In some embodiments, bit-cell 103 may include, but is not limited to, an electronic fuse (eFuse) memory cell, an anti-fuse memory cell, a magnetoresistive random-access memory (MRAM) cell, etc. In some embodiments, transistor T12 may be a sense amplifier and interchangeably referred to as a sense amplifier transistor, and transistor T13 may be a power tap and interchangeably referred to as a power tap transistor.

[0246] In some embodiments, the memory array region 101 may be formed at the same height as the peripheral circuit region 102 (see Figures 2A to 7B), so that the peripheral circuit region 102 can laterally surround the memory array region 101, and the transistors in the peripheral circuit region 102 can be at the same height as the transistors in the memory array region 101. In some embodiments, the memory array region 101 can be formed at a different height from the peripheral circuit region 102 (see Figures 1N to 1R ), so that the peripheral circuit region 102 can be distributed in the memory array region 101 in the same device area (i.e., the same footprint), and the transistors in the peripheral circuit region 102 can overlap with the transistors in the memory array region 101. For example, the memory array region 101 can be located at a higher height than the peripheral circuit region 102 (see Figures 1N to 1R In some embodiments, the memory array region 101 may be located at a lower height than the peripheral circuit region 102 .

[0247] In some embodiments, transistor T11, transistor T12, and / or transistor T13 may include an n-type transistor and / or a p-type transistor, but embodiments are not limited thereto. Transistor T11, transistor T12, and / or transistor T13 may be any suitable type of transistor, including but not limited to a metal oxide semiconductor field effect transistor, a complementary metal oxide semiconductor transistor, a p-type metal oxide semiconductor, an n-type metal oxide semiconductor, a bipolar junction transistor (BJT), a high voltage transistor, a high frequency transistor, p-type and / or n-type field effect transistors (PFETs / NFETs), a fin field effect transistor, a planar metal oxide semiconductor transistor with a raised source / drain, a nanosheet field effect transistor, a nanowire field effect transistor, a thin film transistor, and the like.

[0248] In memory system 100, adjusting the threshold voltages of various circuits or transistors within bit cell 103 can enhance overall system performance. These optimizations depend on the transistor's role within memory system 100. For example, a higher threshold voltage for transistor T11 within bit cell 103 can reduce leakage current. This reduced leakage current effectively reduces unnecessary energy loss, improves data retention, and enhances the memory system's operational efficiency. Conversely, transistor T12 within the peripheral sense amplifier can benefit from a lower threshold voltage. A lower threshold voltage increases the switching speed of transistor T12, resulting in a wider read window. This optimization speeds up read operations and enhances the overall read performance of memory system 100. Furthermore, transistor T13 in the peripheral power connector, without threshold voltage shift, enables more energy-efficient operation. Stable threshold voltages reduce the risk of unexpected power spikes, enabling the system to maintain relatively low and stable power consumption. To fully utilize these features, appropriate threshold voltages can be designed for transistors located in different areas of memory system 100. This optimization may involve controlling the relationship between gate contact VG11, gate contact VG12, and gate contact VG13 and their active regions (e.g., active region OD11, active region OD12, and active region OD13) located in the transistor, which in turn controls the threshold voltage of the transistor. By adjusting this positional relationship, the threshold voltage of the transistor in each region can be adjusted. In some embodiments, the active region can be interchangeably referred to as oxide definition (OD). Other embodiments may include more or fewer active regions. In some embodiments, the number of active regions OD11, active regions OD12, or active regions OD13 can be between about 1 and about 10, for example, about 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0249] Furthermore, the effect of gate contact position on threshold voltage can vary depending on the type of transistor. For example, n-type MOS and p-type MOS transistors may respond differently to the same gate contact and gate structure position due to their inherently different operating characteristics, which will be explained below.

[0250] refer to Figure 1B and Figure 1C . Figure 1B FIG1 shows a graph showing the effect of different gate contact positions on the threshold voltage characteristics of an n-type metal oxide semiconductor transistor according to some embodiments of the present disclosure, wherein curves C1, C2, and C3 represent the effects of different gate contact positions on the threshold voltage characteristics of an n-type metal oxide semiconductor transistor having 2, 4, and 6 active regions (e.g., Figure 1A The transistors in the active region OD11, the active region OD12 or the active region OD13 are shown. Figure 1CFIG4 shows a graph illustrating threshold voltage characteristics of a p-type metal oxide semiconductor transistor considering different gate contact positions according to some embodiments of the present disclosure, wherein curves C4, C5, and C6 represent threshold voltage characteristics of a p-type metal oxide semiconductor transistor having 2, 4, and 6 active regions (e.g., Figure 1A In some embodiments, as shown in FIG. Figure 1A The active region OD11, the active region OD12, and the active region OD13 shown may be formed on the substrate 110 and extend along the X direction in the memory array region 101 and the peripheral circuit region 102. The transistors T11, T12, and T13 may be formed on the active region OD11, the active region OD12, and the active region OD13.

[0251] like Figure 1B As shown, for an n-type metal oxide semiconductor transistor, it can be observed that the gate contact position (e.g., Figure 1A The invention also relates to pattern configurations of gate contacts VG11, gate contacts VG12, and gate contacts VG13 (shown in FIG. 1 ), and observes the effect of gate contact positions on the threshold voltage of an n-type metal oxide semiconductor transistor. When the gate contact overlaps the active region and is further from the edge of the active region, the threshold voltage of the n-type metal oxide semiconductor transistor tends to increase. In some embodiments, the edge of the active region (e.g., as shown in FIG. 1 ) is not necessarily the same as the gate contact position. Figure 1A The edges B11, B12, and B13 of the active regions OD11, OD12, and OD13 shown can extend perpendicular to the length of the gate structure G11. Beyond a distance D1, the threshold voltage reaches stability, indicating that the n-type metal oxide semiconductor transistor has reached its operating conditions for the aforementioned configuration. Conversely, when the gate contact is located outside the active region and further from the edge of the active region, the n-type metal oxide semiconductor transistor exhibits a trend toward a stable threshold voltage and does not change. After reaching a distance D2, the threshold voltage remains stable, indicating that the n-type metal oxide semiconductor transistor is insensitive to further changes in the gate contact position. Figure 1BThe trends of curves C1, C2, and C3 represent these characteristics. Curves C1, C2, and C3 provide the relationship between gate contact position and threshold voltage for n-type metal oxide semiconductor transistors with different amounts of active regions, illustrating how to optimize n-type metal oxide semiconductor transistor performance by controlling the gate contact position. In some embodiments, distance D1 may be greater than approximately 5 nanometers, such as approximately 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15 nanometers. In some embodiments, distance D2 may be greater than approximately 15 nanometers, such as approximately 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, or 25 nanometers.

[0252] also, Figure 1B Curves C1, C2, and C3 in the diagram illustrate the impact of the number of active regions on the threshold voltage in determining the gate contact location. N-type metal oxide semiconductor transistors with fewer active regions are more sensitive to changes in the gate contact location. For example, when the gate contact overlaps the active region, an n-type metal oxide semiconductor transistor with two active regions can achieve a higher threshold voltage than an n-type metal oxide semiconductor transistor with four active regions. Similarly, when the gate contact overlaps the active region, an n-type metal oxide semiconductor transistor with four active regions can achieve a higher threshold voltage than an n-type metal oxide semiconductor transistor with six active regions. This pattern configuration demonstrates an inverse relationship between the number of active regions and the threshold voltage achievable at a given gate contact location.

[0253] like Figure 1C As shown, for a p-type metal oxide semiconductor transistor, it can be observed that the gate contact position (e.g., Figure 1A Figure 1 shows a pattern configuration related to gate contacts VG11, VG12, and VG13 (shown), and observes the effect of gate contact position on the threshold voltage of a p-type metal oxide semiconductor transistor. When the gate contact overlaps the active region and is further from the edge of the active region, the threshold voltage of the p-type metal oxide semiconductor transistor tends to decrease. Beyond a distance D3, this threshold voltage reaches stability, indicating that the p-type metal oxide semiconductor transistor has reached its operating conditions for this configuration. Conversely, when the gate contact is located outside the active region and further from the edge of the active region, the p-type metal oxide semiconductor transistor shows a trend of stabilizing its threshold voltage and not changing. After reaching a distance D4, the threshold voltage remains stable, indicating that the p-type metal oxide semiconductor transistor is insensitive to further changes in the gate contact position. Figure 1CThe trends of curves C4, C5, and C6 represent these characteristics. Curves C4, C5, and C6 provide the relationship between gate contact position and threshold voltage for p-type metal oxide semiconductor transistors with varying amounts of active regions, illustrating how to optimize the performance of p-type metal oxide semiconductor transistors by controlling the gate contact position. In some embodiments, distance D3 can be greater than approximately 5 nanometers, such as approximately 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15 nanometers. In some embodiments, distance D4 can be greater than approximately 15 nanometers, such as approximately 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, or 25 nanometers.

[0254] also, Figure 1C Curves C4, C5, and C6 in the graph illustrate that the number of active regions plays a role in determining the extent to which the gate contact position affects the threshold voltage. P-type metal oxide semiconductor transistors with fewer active regions appear to be more sensitive to changes in the gate contact position. For example, when the gate contact overlaps the active region, a p-type metal oxide semiconductor transistor with two active regions can achieve a lower threshold voltage than a p-type metal oxide semiconductor transistor configured with four active regions. Similarly, when the gate contact overlaps the active region, a p-type metal oxide semiconductor transistor with four active regions can achieve a lower threshold voltage than a p-type metal oxide semiconductor transistor configured with six active regions. This pattern configuration indicates an inverse relationship between the number of active regions and the threshold voltage achievable at a given gate contact position.

[0255] refer to Figures 1A to 1C .exist Figure 1A In the illustrated bit cell 103 of the memory array region 101, leakage in the memory system 100 can be minimized by increasing the threshold voltage of transistor T11. Therefore, transistor T11 can be an n-type metal oxide semiconductor transistor with its gate contact VG11 overlapping the active region OD11 of transistor T11. This configuration increases the threshold voltage, thereby reducing current leakage.

[0256] In addition, for Figure 1A The sense amplifier in the peripheral circuit region 102 shown in FIG. 3 can achieve an improved read window by lowering the threshold voltage of transistor T12, which serves as the sense amplifier. Therefore, transistor T12 can be a p-type metal oxide semiconductor transistor with its gate contact VG12 overlapping the active region OD12 of transistor T12. This configuration reduces the threshold voltage, thereby expanding the read window and improving the performance of the sense amplifier.

[0257] In addition, for Figure 1AThe power connection in the peripheral circuit region 102 shown in FIG. can achieve efficient power utilization by stabilizing the threshold voltage of transistor T13 as the power connection. Therefore, transistor T13 can be an n-type metal oxide semiconductor transistor or a p-type metal oxide semiconductor transistor, with its gate contact VG13 not overlapping the active region OD13 of transistor T13. This configuration maintains a stable threshold voltage of transistor T13 without threshold voltage fluctuations, contributing to efficient power utilization within the memory system 100.

[0258] refer to Figures 1D to 1R . Figure 1D According to some embodiments of the present disclosure, a memory array region 101 (see Figure 1A ) within a one-time programmable (OTP) memory element (e.g., an electronic fuse memory cell), wherein the OTP memory element may include a one-transistor and one-resistor (1T1R) configuration. Figure 1E to Figure 1R The diagrams of FinFET devices, Nano-FET devices and Thin Film Transistor devices according to some embodiments of the present disclosure are shown. Specifically, Figure 1E 、 Figure 1H and Figure 1K A perspective view of a FinFET device, a Nano-FET device, and a Thin Film Transistor device according to some embodiments of the present disclosure is shown. Figure 1F 、 Figure 1G 、 Figure 1I 、 Figure 1L 、 Figure 1J 、 Figure 1M and Figures 1N to 1R Cross-sectional views of corresponding FinFET devices, nano-FET devices, and / or thin film transistor devices according to some embodiments of the present disclosure are shown.

[0259] In some embodiments, the peripheral circuit area 102 (see Figure 1A ) can be connected to the memory array region 101 (see Figure 1A ) have the same device type, such as FinFET devices, gate-around devices, thin-film transistor devices, or other devices such as Figure 1F 、 Figure 1G 、 Figure 1I 、 Figure 1J 、 Figure 1L and Figure 1M Suitable elements as shown. For example, Figure 1F and Figure 1GAs shown, the transistors in the peripheral circuit region 102 and the memory array region 101 can both be FinFET devices. Figure 1I and Figure 1J As shown, the transistors in the memory array region 101 and the peripheral circuit region 102 can all be nano-field effect transistor devices. Figure 1L and Figure 1M As shown, the transistors in the memory array region 101 and the peripheral circuit region 102 can all be thin film transistor elements. Figures 1N to 1R As shown, the transistors in the peripheral circuit region 102 may be of different device types than the transistors in the memory array region 101. For example, the transistors in the peripheral circuit region 102 may be gate-around devices, while the transistors in the memory array region 101 may be thin film transistors.

[0260] refer to Figures 1D to 1G . Figure 1F and Figure 1G Some embodiments of the present disclosure are shown. Figure 1A , a cross-sectional view of the semiconductor structure obtained by reference cross-sections AA', BB', CC', D-D', EE', and FF'. Specifically, at least one transistor (e.g., Figure 1A The transistors T11, T12 and T13 shown in FIG. 1 can use fin field effect transistors (see FIG. Figure 1E The FinFET device may be a non-planar multi-gate transistor, which is built on a substrate 110, such as a silicon substrate. The substrate 110 may be made of a suitable elemental semiconductor (e.g., silicon, diamond, or germanium), a suitable alloy or compound semiconductor (e.g., Group IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), germanium tin (GeSn), silicon tin (SiSn), silicon germanium tin (SiGeSn), Group III-V compound semiconductors (e.g., gallium arsenide (GaAs), indium gallium arsenide, indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide, indium gallium antimonide, or gallium indium gallium phosphide), etc.). The substrate 110 may also include an epitaxial layer, which may be strained for performance enhancement and / or may include a silicon-on-insulator (SOI) structure. An n-type well and a p-type well are formed in the substrate 110. A p-type FinFET is formed on the n-type well, and an n-type FinFET is formed on the p-type well.

[0261] Specifically, the thin silicon-containing fin structure forms the active regions OD11, OD12, and OD13 of the transistors T11, T12, and T13. The fin structure extends along the X direction and protrudes upward from the electrical isolation structure 111, as shown in FIG. Figure 1E As shown. The fin width W of the fin structure fin Measured along the Y direction, the aforementioned direction is orthogonal to the X direction. Each of the active region OD11, the active region OD12, and the active region OD13 can be defined by a first outer edge B11, B12, or B13 of the first outermost of the plurality of fin structures and a second outer edge B11, B12, or B13 of the second outermost of the plurality of fin structures. From a top view, the second outer edges B11, B12, or B13 of the aforementioned plurality of fin structures are opposite to the first outer edges B11, B12, or B13. A portion of the fin structure surrounded by the gate structure G11, the gate structure G12, and the gate structure G13 can serve as the channel region 112a, the channel region 112b, and the channel region 112c of the FinFET element (see Figure 1F and Figure 1G ). The effective channel length of the FinFET device is determined by the size of the fin structure. In some embodiments, the channel region 112a, the channel region 112b, and the channel region 112c may be interchangeably referred to as a channel pattern, a fin structure, or a fin pattern. Figure 1E to Figure 1G As shown, transistor T11 may include a channel region 112a, source / drain regions S / D11 located on both sides of and connected to channel region 112a, and a gate structure G11 surrounding channel region 112a. Transistor T12 may include a channel region 112b, source / drain regions S / D12 located on both sides of and connected to channel region 112a, and a gate structure G12 surrounding channel region 112b. Transistor T13 may include a channel region 112c, source / drain regions S / D13 located on both sides of and connected to channel region 112c, and a gate structure G13 surrounding channel region 112c. Transistor T11 may be located in memory array region 101, while transistors T12 and T13 may be located in peripheral circuit region 102.

[0262] like Figure 1E to Figure 1GThe integrated circuit structure in the illustrated memory system 100 may further include an isolation structure 111, such as shallow trench isolation (STI) formed on the N-type well and the P-type well of the substrate 110. The isolation structure 111 may define and electrically isolate the active regions OD11, OD12, and OD13 of the transistors T11, T12, and T13. Forming the shallow trench isolation regions 111 includes patterning the semiconductor substrate 110 using suitable photolithography and etching techniques to form one or more insulating materials (e.g., silicon oxide) that completely fill trenches in the substrate 110. A planarization process (e.g., a chemical mechanical polishing (CMP) process) is then performed to make the isolation structure 111 flush with the top surfaces of the active regions OD11, OD12, and OD13. The insulating material of the isolation structure 111 can be deposited using one or more suitable methods, such as high-density plasma chemical vapor deposition (HDP-CVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCVD), spin-on coating, or a combination thereof. After deposition, an annealing process or a curing process can be performed, particularly when flowable chemical vapor deposition is used to form the isolation structure 111. In some embodiments, the isolation structure 111 can be further recessed (e.g., by an etchback process) below the top surfaces of the active regions OD11, OD12, and OD13 so that the active regions OD11, OD12, and OD13 protrude from the top surface of the recessed isolation structure 111 to form a fin-like structure, thereby allowing fin field-effect transistor devices to be formed on the active regions OD11, OD12, and OD13.

[0263] like Figure 1E to Figure 1GThe integrated circuit structure in the memory system 100 shown may also include a gate structure G11, a gate structure G12, and a gate structure G13 extending within the memory array region 101 and the peripheral circuit region 102, and crossing the active region OD11, the active region OD12, and the active region OD13 along the Y direction, wherein the Y direction is perpendicular to the X direction. The gate structure G11, the gate structure G12, and the gate structure G13 have a strip shape in the top view, and therefore can be interchangeably referred to as metal gate strips in this context. In some embodiments, the gate structure G11, the gate structure G12, and the gate structure G13 can be interchangeably referred to as a gate, a metal gate, a gate layer, or a gate pattern. Figure 1A As shown, in some embodiments, the gate structure G11 , the gate structure G12 , and the gate structure G13 are arranged in a first row along the X direction. The gate structure G11 , the gate structure G12 , and the gate structure G13 are disposed at the same height.

[0264] In some embodiments, gate structure G11, gate structure G12, and gate structure G13 are functional high-k metal gate (HKMG) gate structures. Functional high-k metal gate structures G11, G12, and G13 are formed using the same gate-last process flow (interchangeably referred to as a gate replacement flow in this context), which will be explained in more detail below. As a result of the gate-last process flow, each of gate structure G11, gate structure G12, and gate structure G13 includes one or more gate electrode layers 117 and a gate dielectric layer 116 on the bottom surface and sidewalls of the substrate, so that the gate dielectric layer 116 has a Figure 1F U-shaped cross section shown.

[0265] like Figure 1E to Figure 1GThe integrated circuit structure in the illustrated memory system 100 may further include a plurality of source / drain regions S / D11, S / D12, and S / D13 within the active regions OD11, OD12, and OD13. The source / drain regions S / D11, S / D12, and S / D13 are doped semiconductor regions located on either side of the corresponding gate structures G11, G12, and G13. In some embodiments, the source / drain regions S / D11, S / D12, and S / D13 include p-type dopants or impurities, such as boron, to form functional p-type field-effect transistors within the active regions OD11, OD12, and OD13. In some other embodiments, the source / drain regions S / D11, S / D12, and S / D13 include n-type dopants or impurities, such as phosphorus, for forming functional n-type FETs in the active regions OD11, OD12, and OD13. In some embodiments, a set of source / drain contacts MD11, MD12, and MD13 may be formed (see FIG. Figure 1A ) to land on the corresponding source / drain regions S / D11, S / D12, and S / D13 in the active regions OD11, OD12, and OD13. In some embodiments, the source / drain contacts MD11, MD12, and MD13 may include one or more suitable metals, such as W, Cu, etc., or a combination thereof.

[0266] In some embodiments, the source / drain region S / D11 , the source / drain region S / D12 , and the source / drain region S / D13 may be epitaxial growth regions. For example, by forming a gate spacer structure 113 next to a sacrificial gate structure (to be replaced by gate structure G11, gate structure G12, and gate structure G13), a recess may be formed by first etching the active regions OD11, OD12, and OD13, and then a crystalline semiconductor material may be filled in the recesses of the active regions OD11, OD12, and OD13 by a selective epitaxial growth (SEG) process to self-align to the gate spacer structure 113 to form source / drain regions S / D11, S / D12, and S / D13. In some embodiments, the recesses may be filled to form raised source / drain epitaxial structures that extend further beyond the original surfaces of the recessed active regions OD11, OD12, and OD13. The crystalline semiconductor material may be an elemental semiconductor (e.g., Si, Ge, etc.) or an alloy semiconductor (e.g., Si 1-x C x 、Si 1- x Ge x The selective epitaxial growth process may use any appropriate epitaxial growth method, such as vapor / solid / liquid phase epitaxy (VPE / SPE / LPE), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), etc. A high dose (e.g., about 10 14 cm -2 to 10 16 cm -2 ) can be added in situ during the selective epitaxial growth, or by an ion implantation process after the selective epitaxial growth, or a combination of the two.

[0267] like Figure 1E to Figure 1GThe integrated circuit structure in the memory system 100 may further include a plurality of gate contacts VG11, VG12, and VG13 located above the corresponding gate structures G11, G12, and G13, wherein at least two of the gate contacts VG11, VG12, and VG13 have different contact positions on the corresponding gate structures G11, G12, and G13. For example, Figure 1F As shown, gate contact VG11 may be located between outermost edges B11 of active region OD11, gate contact VG12 may be located between outermost edges B12 of active region OD12, and gate contact VG13 may be located outside outermost edges B13 of active region OD13. This gate contact configuration can increase the threshold voltage of transistor T11 in memory array region 101, thereby reducing current leakage, lower the threshold voltage of transistor T12 in the sense amplifier, thereby expanding the read window and improving the performance of the sense amplifier, and maintain a stable threshold voltage of transistor T13, thereby reducing threshold voltage drift, which contributes to efficient energy utilization within memory system 100.

[0268] In some embodiments, gate contact VG11 and / or gate contact VG12 may overlap with active region OD11 and / or active region OD12. In some embodiments, gate contact VG11 and / or gate contact VG12 may not overlap with active region OD11 and / or active region OD12. In some embodiments, gate contact VG11 has a lateral distance D5 from edge B11 of active region OD11, gate contact VG12 has a lateral distance D6 from edge B12 of active region OD12, and gate contact VG13 has a lateral distance D7 from edge B13 of active region OD13. For example, distance D5 may be in a range of approximately 5 to 60 nanometers, such as approximately 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 20, 25, 30, 35, 40, 45, 50, 55, or 60 nanometers. In some embodiments, distance D6 can be in the range of about 5 to 60 nanometers, such as about 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 20, 25, 30, 35, 40, 45, 50, 55, or 60 nanometers. In some embodiments, distance D7 can be in the range of about 15 to 60 nanometers, such as about 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 30, 35, 40, 45, 50, 55, or 60 nanometers.

[0269] In some embodiments, the gate contacts VG11, VG12, and VG13 may include a conductive material, such as copper (Cu), tungsten (W), cobalt (Co), or other suitable metals. Forming the gate contacts VG11, VG12, and VG13 may include etching contact openings in an interlayer dielectric (ILD) layer 118 on the gate structures G11, G12, and G13, and then depositing one or more conductive materials in the contact openings and planarizing the one or more conductive materials using, for example, a chemical mechanical polishing process.

[0270] Reference Figure 1D , the bit cell 103 having the memory array region 101 may be an electronic fuse cell. The bit cell 103 may be implemented as a single crystal and single resistor configuration, for example, the fuse resistor 104 may be connected in series to the access transistor T11. However, it should be understood that the bit cell 103 may use one of various other fuse configurations having fuse characteristics, such as a 2-diode-1-resistor (2D1R) configuration, a multi-transistor-1-resistor (manyT1R) configuration, etc., and still fall within the scope of the present disclosure. In some embodiments, the fuse resistor 104 may be formed by one or more metal structures. For example, the fuse resistor 104 may be one of one or more interconnect structures located above the access transistor T11. Specifically, the access transistor T11 is formed on the substrate 110 (see Figure 1E to Figure 1G During the FEOL process, multiple metal layers, including multiple interconnect (e.g., metal) structures, are typically formed, sometimes referred to as part of the back-end of line (BEOL). During the BEOL process, or between the FEOL and BEOL processes, there may be process steps that form local electrical connections between transistors and metal gate contacts during the middle-end of line (MEOL) process.

[0271] In some embodiments, the fuse resistor 104 may include a bottom electrode layer 104a and a top electrode layer 104c (see Figure 1N ) and the fuse layer 104b between the bottom electrode layer 104a and the top electrode layer 104c (see Figure 1NIn some embodiments, one of the source / drain regions S / D11 of the access transistor T11 can be electrically connected to the source line SL11, the other source / drain region S / D11 of the access transistor T11 can be electrically connected to the bit line BL11, and the gate structure G11 can be electrically connected to the word line WL11. When programming the fuse resistor 104 (in the form of a metal structure) in the bit cell 103, the access transistor T11 (if implemented as an n-type transistor) can be turned on by applying a signal (e.g., a voltage) corresponding to a logic high electrical state to the gate structure G11 of the access transistor T11 via the word line WL11. Simultaneously or subsequently, a sufficiently high signal (e.g., a voltage) can be applied to one of the terminals of the fuse resistor 104 on the bit line BL11. By turning on access transistor T11 to provide a (e.g., program) path from bit line BL11 through fuse resistor 104 and access transistor T11 to source line SL11, such a high voltage signal can burn a portion of the corresponding metal structure (e.g., fuse resistor 104), thereby transitioning fuse resistor 104 from a first state (e.g., a short circuit) to a second state (e.g., an open circuit). Therefore, bit cell 103 can irreversibly transition from a first logic state (e.g., a logic 0) to a second logic state (e.g., a logic 1), and a (read) path can be provided by applying a relatively low voltage signal to bit line BL11 and turning on access transistor T11.

[0272] refer to Figures 1H to 1J . Figure 1I A cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown, which includes Figure 1F Corresponding nano field-effect transistor components. Figure 1J Some embodiments of the present disclosure are shown. Figure 1G The corresponding cross-sectional view of the semiconductor structure includes a nano field effect transistor element. Specifically, Figure 1A At least one of the transistors T11, T12, and T13 in the memory system 100 may be replaced by Figure 1HAt least one of the transistors T11', T12' and T13' in the nano field effect transistor element shown in , such as a nanowire field effect transistor, a nanosheet field effect transistor, etc. The nano field effect transistor can be a nanosheet field effect transistor (NSFET), a nanowire field effect transistor (NWFET), a gate-all-around field effect transistor (GAAFET), etc. Figures 1H to 1J As shown, transistor T11', transistor T12' and transistor T13' include active regions OD11', active regions OD12' and active regions OD13' (such as nanostructures, nanosheets, nanowires, etc.) on the fin structure 214 on the substrate 210, wherein the active regions OD11', active regions OD12' and active regions OD13' serve as channel regions of transistors T11', transistor T12' and transistor T13'. In some embodiments, from a top view, each of the active region OD11', the active region OD12', and the active region OD13' can be defined by a first outer edge B11', B12', or B13' of a channel region (e.g., a nanostructure, a nanosheet, a nanowire, etc.) and a second outer edge B11', B12', or B13' of the channel region (e.g., a nanostructure, a nanosheet, a nanowire, etc.), wherein the second outer edge B11', B12', or B13' is disposed relative to the first outer edge B11', B12', or B13'.

[0273] A dielectric isolation structure 211 such as shallow trench isolation (STI) may be formed to laterally surround the fin structure 214. The dielectric isolation structure 211 may define and electrically isolate the active regions OD11', OD12', and OD13' of the transistors T11', T12', and T13'.

[0274] In some embodiments, the active regions OD11', OD12', and OD13' may include p-type nanostructures, n-type nanostructures, or a combination thereof, and extend along the X direction. In some embodiments, the active regions OD11', OD12', and OD13' may be interchangeably referred to as channel patterns, channel regions, nanostructures, nanosheets, and nanowires. The structure and material of the substrate 210 are similar to those of the substrate 210. Figure 1E to Figure 1G The structure 110 shown is basically the same, and the relevant detailed description can be referred to the previous paragraphs and will not be repeated here.

[0275] In some embodiments, transistor T11′ may include an active region OD11′, source / drain regions S / D11′ located on either side of and connected to the active region OD11′, and a gate structure G11′ surrounding the active region OD11′. Transistor T12′ may include an active region OD12′, source / drain regions S / D12′ located on either side of and connected to the active region OD12′, and a gate structure G12′ surrounding the active region OD11′. Transistor T13′ may include an active region OD13′, source / drain regions S / D13′ located on either side of and connected to the active region OD13′, and a gate structure G13′ surrounding the active region OD13′. Transistor T11′ may be located in the memory array region 101, while transistors T12′ and T13′ may be located in the peripheral circuit region 102. The gate spacer structure 213 may be formed on one side of the sacrificial gate structure G11', the gate structure G12', and the gate structure G13' (see FIG. Figure 1J ). The structure and material of the gate spacer structure 213 are similar to Figure 1E to Figure 1G The gate spacer structures 113 shown are substantially the same, and the related detailed description can be referred to the aforementioned paragraphs and will not be repeated here.

[0276] Therefore, if Figure 1A The bit cell 103 of the memory array region 101 in the memory system 100 shown can minimize current leakage by increasing the threshold voltage of the transistor T11'. Therefore, the transistor T11' can be an n-type metal oxide semiconductor transistor, whose gate contact VG11' overlaps with the active region OD11' of the transistor T11'. This configuration can increase the threshold voltage, thereby reducing current leakage. In addition, for example, Figure 1A The sense amplifier in the peripheral circuit area 102 shown can achieve an improved read window by reducing the threshold voltage of the transistor T12' used as the sense amplifier. Therefore, the transistor T12' can be a p-type metal oxide semiconductor transistor, whose gate contact VG12' overlaps the active region OD12' of the transistor T12'. This configuration can reduce the threshold voltage, thereby expanding the read window and improving the performance of the sense amplifier. In addition, for example, Figure 1AThe power connection within the peripheral circuit region 102 shown can achieve efficient power utilization by maintaining a stable threshold voltage for transistor T13', which serves as the power connection. Therefore, transistor T13' can be an n-type metal oxide semiconductor transistor or a p-type metal oxide semiconductor transistor, with its gate contact VG13' not overlapping the active region OD13' of transistor T13'. This configuration maintains a stable threshold voltage for transistor T13', eliminating threshold voltage drift, thereby facilitating efficient power utilization within the memory system 100.

[0277] Specifically, an interlayer dielectric layer 228 may be formed on the gate structures G11', G12', and G13' of the transistors T11', T12', and T13' using appropriate deposition techniques. Gate contacts VG11', VG12', and VG13' may then be formed within the interlayer dielectric layer 228 and covering the respective gate structures G11', G12', and G13'. At least two gate contacts VG11', VG12', and VG13' may have different contact locations on the respective gate structures G11', G12', and G13'. For example, Figure 1IAs shown, gate contact VG11' can be located between the outermost edges B11' of active region OD11', gate contact VG12' can be located between the outermost edges B12' of active region OD12', and gate contact VG13' can be located in the space outside the outermost edge B13' of active region OD13'. This gate contact configuration can increase the threshold voltage of transistor T11' in memory array region 101, thereby reducing current leakage, lower the threshold voltage of transistor T12' in the sense amplifier, thereby expanding the read window and enhancing the performance of the sense amplifier. It also maintains a stable threshold voltage of transistor T13', reducing threshold voltage drift, and contributing to efficient power utilization within memory system 100. In some embodiments, the interlayer dielectric layer 228 may include silicon dioxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), a low dielectric constant (low-k) dielectric material such as fluorosilicate glass (FSG), siliconoxycarbide (SiOCH), carbon-doped oxide (CDO), flowable oxide, or porous oxides (e.g., xerogels / aerogels), or a combination thereof.

[0278] In some embodiments, gate contact VG11' and / or gate contact VG12' may overlap with active region OD11' and / or active region OD12'. In some embodiments, gate contact VG11' and / or gate contact VG11' may not overlap with active region OD11' and / or active region OD12'. In some embodiments, the lateral distance between gate contact VG11' and edge B11' of active region OD11' is at least D5', the lateral distance between gate contact VG12' and edge B12' of active region OD12' is at least D6', and the lateral distance between gate contact VG13' and edge B13' of active region OD13' is at least D7'. For example, distance D5' may be in a range of approximately 5 to 60 nanometers, such as approximately 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 20, 25, 30, 35, 40, 45, 50, 55, or 60 nanometers. In some embodiments, distance D6' can be in the range of about 5 to 60 nanometers, such as about 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 20, 25, 30, 35, 40, 45, 50, 55, or 60 nanometers. In some embodiments, distance D7' can be in the range of about 15 to 60 nanometers, such as about 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 30, 35, 40, 45, 50, 55, or 60 nanometers.

[0279] In some embodiments, each of the gate structure G11', the gate structure G12', and the gate structure G13' includes one or more gate electrode layers 217 and a gate dielectric layer 216. The gate dielectric layer 216 can be formed on the top surface of the fin structure 214 and along the top surface, sidewalls, and bottom surfaces of the active region OD11', the active region OD12', and the active region OD13'. The gate electrode layer 217 is formed on the gate dielectric layer 216. In some embodiments, the gate dielectric layer 216 can include a dielectric material having a k value of approximately 7.0 or greater, such as a metal oxide or silicate of tungsten, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, etc. Although Figures 1H to 1J A single layer gate dielectric layer 216 is depicted in FIG, but the gate dielectric layer 216 may include any number of interfacial layers and main layers, as will be described in more detail later. In some embodiments, the gate electrode layer 217 may include a metal-containing material such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multilayer structures thereof, or the like. Although Figures 1H to 1J, a single gate electrode layer 217 is depicted, but the gate electrode layer 217 may include any number of work function tuning layers, any number of barrier layers, any number of adhesion layers, and filler materials. In some embodiments, the gate electrode layer 217 may be made of a material selected from the group consisting of TiN, TaN, TiAl, TiAlN, TaAl, TaAlN, TaAlC, TaCN, WNC, Co, Ni, Pt, W, or combinations thereof.

[0280] In some embodiments, source / drain regions S / D11′, source / drain regions S / D12′, and source / drain regions S / D13′ are formed to be disposed on the fin structures 214 on opposite sides of the gate dielectric layer 216 and the gate electrode layer 217. The source / drain regions S / D11′, source / drain regions S / D12′, and source / drain regions S / D13′ may be shared between various fin structures 214. For example, adjacent source / drain regions S / D11′, S / D12′, and S / D13′ may be electrically isolated by epitaxial growth, or by coupling the source / drain regions S / D11′, source / drain regions S / D12′, and source / drain regions S / D13′ to have the same source / drain contact. An interlayer dielectric layer 218 covering the source / drain region S / D11′, source / drain region S / D12′, and source / drain region S / D13′ can be formed by depositing a dielectric material on substrate 210. In some embodiments, interlayer dielectric layer 218 can include silicon dioxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, a low-k dielectric material such as fluorosilicate glass, silicon-oxygen-carbon-hydrogen, a carbon-doped oxide, a fluid oxide, or a porous oxide (e.g., xerogels / aerogels), or a combination thereof. Source / drain contacts MD11′, MD12′, and MD13′ can be formed to land on the corresponding source / drain region S / D11′, source / drain region S / D12′, and source / drain region S / D13′.

[0281] In some embodiments, a fuse resistor (not shown) may be connected in series to the access transistor T11'. The structure and function of the elements and their relationship between the transistor T11' and the fuse resistor are substantially the same as those in FIG. Figures 1D to 1G The transistor T11 and the fuse resistor 104 shown in FIG are the same. For detailed descriptions thereof, reference may be made to the aforementioned paragraphs and will not be repeated here.

[0282] In some embodiments, an internal spacer structure 219 may be formed between the source / drain region S / D11′, the source / drain region S / D12′, and the source / drain region S / D13′ and the corresponding gate structure G11′, the gate structure G12′, and the gate structure G13′ to isolate the gate structure G11′, the gate structure G12′, and the gate structure G13′ from the source / drain region S / D11′, the source / drain region S / D12′, and the source / drain region S / D13′. The internal spacer structure 219 may be a low-k dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxycarbide (SiCO), silicon nitrogen carbon nitride (SiCN), or silicon oxycarbon nitride (SiOCN). The internal spacer structure 219 may be formed using chemical vapor deposition (including low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition (PECVD)), physical vapor deposition, atomic layer deposition (ALD), or other suitable processes. Figure 1J In the embodiment, the sidewalls of the inner spacer structure 219 are substantially aligned with the sidewalls of the active region OD11 ′, the active region OD12 ′, and the active region OD13 ′.

[0283] In some embodiments, dielectric isolation structures 211, such as shallow trench isolation (STI) regions, are disposed between adjacent fin structures 214, and the fin structures 214 may protrude from between the dielectric isolation structures 211. Although the dielectric isolation structures 211 are described / illustrated as being separate from the substrate 210, and although the bottoms of the fin structures 214 are shown as being a single continuous material with the substrate 210, the bottoms of the fin structures 214 and / or the substrate 210 may comprise a single material or multiple materials.

[0284] refer to Figures 1K to 1M . Figure 1L A cross-sectional view of a semiconductor structure having a thin film transistor device according to some embodiments of the present disclosure is shown, corresponding to Figure 1F . Figure 1M A cross-sectional view of a semiconductor structure having a thin film transistor device according to some embodiments of the present disclosure is shown, corresponding to Figure 1G Specifically, if Figure 1A In the memory system 100 shown, at least one of the transistors T11, T12, and T13 may be configured as follows: Figure 1K In some embodiments, the transistor T11" may include a channel region 312a, a source / drain region S / D11 located on both sides of the channel region 312a and connected to the channel region 312a (see Figure 1M) and a gate structure G11 located on the channel region 312a. The transistor T12" may include a channel region 312b, a source / drain region S / D12 located on both sides of the channel region 312b and connected to the channel region 312b (see Figure 1M ) and a gate structure G12 located on the channel region 312b. The transistor T13" may include a channel region 312c, a source / drain region S / D13 located on both sides of the channel region 312c and connected to the channel region 312c (see Figure 1M ) and a gate structure G13 ″ located on the channel region 312 c . The transistor T11 ″ may be located in the memory array region 101 , while the transistor T12 ″ and the transistor T13 ″ may be located in the peripheral circuit region 102 .

[0285] Therefore, if Figure 1A The bit cell 103 of the illustrated memory array region 101 can minimize current leakage in the memory system 100 by increasing the threshold voltage of the transistor T11″. Therefore, the transistor T11″ can be an n-type metal oxide semiconductor transistor, whose gate contact VG11″ overlaps the active region OD11″ of the transistor T11″. This configuration can increase the threshold voltage, thereby reducing current leakage. In some embodiments, when viewed from above, the active region OD11″, the active region OD12″, and the active region OD13″ can each be bounded by a first outer edge B11″, B12″, or B13″ of the channel region 312a, the channel region 312b, or the channel region 312c, and a second outer edge B11″, B12″, or B13″ of the channel region 312a, the channel region 312b, or the channel region 312c, wherein the first outer edge B11″, B12″, or B13″ is disposed opposite to the second outer edge B11″, B12″, or B13″.

[0286] In addition, for Figure 1A The sense amplifier in the peripheral circuit region 102 shown can achieve an improved read window by lowering the threshold voltage of the transistor T12″ serving as the sense amplifier. Therefore, the transistor T12″ can be a p-type metal oxide semiconductor transistor, whose gate contact VG12″ overlaps with the active region OD12″ of the transistor T12″. This configuration can lower the threshold voltage, thereby extending the read window and enhancing the performance of the sense amplifier. In addition, for example, Figure 1AThe power connection within the peripheral circuit region 102 shown can achieve efficient power utilization by stabilizing the threshold voltage of the transistor T13″ serving as the power connection. Therefore, the transistor T13″ can be an n-type metal oxide semiconductor transistor or a p-type metal oxide semiconductor transistor, whose gate contact VG13″ does not overlap with the active region OD13″ of the transistor T13″. This configuration maintains a stable threshold voltage of the transistor T13″, preventing threshold voltage drift, and contributing to efficient power utilization within the memory system 100.

[0287] like Figure 1L and Figure 1M As shown, the gate contact VG11″, the gate contact VG12″, and the gate contact VG13″ may be formed on the respective gate contacts G11″, G12″, and G13″ of the transistors T11″, T12″, and T13″, and at least two of the gate contacts VG11″, VG12″, and VG13″ may have different contact positions on the respective gate structures G11″, G12″, and G13″. For example, as shown in FIG. Figure 1L As shown, the gate contact VG11″ may be located between the outermost edges B11″ of the active region OD11″, the gate contact VG12″ may be located between the outermost edges B12″ of the active region OD12″, and the gate contact VG13″ may be located outside the space defined between the outermost edges B13″ of the active region OD13″. This gate contact configuration can increase the threshold voltage of the transistor T11″ in the memory array region 101, thereby reducing current leakage, lower the threshold voltage of the transistor T12″ in the sense amplifier, thereby expanding the read window and enhancing the performance of the sense amplifier, and maintain a stable threshold voltage of the transistor T13″, reducing threshold voltage drift, thereby contributing to efficient power utilization within the memory system 100.

[0288] In some embodiments, the gate contact VG11″ and / or the gate contact VG12″ may overlap with the active region OD11″ and / or the active region OD12″. In some embodiments, the gate contact VG11″ and / or the gate contact VG11″ may not overlap with the active region OD11″ and / or the active region OD12″. In some embodiments, the gate contact VG11″ is spaced apart from an edge B11″ of the active region OD11″ by at least a lateral distance D5″, the gate contact VG12″ is spaced apart from an edge B12″ of the active region OD12 by at least a lateral distance D6″, and the gate contact VG13″ is spaced apart from an edge B13″ of the active region OD13″ by at least a lateral distance D7″. By way of example, and not limitation of the present disclosure, the distance D5″ may be in the range of approximately 5 to 60 nm, for example, approximately 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 20, 25, 30, 35, 40, 45, 50, 55, or 60 nm. In some embodiments, distance D6" may be in the range of about 5 to 60 nm, such as about 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 20, 25, 30, 35, 40, 45, 50, 55, or 60 nm. In some embodiments, distance D7" may be in the range of about 15 to 60 nm, such as about 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 30, 35, 40, 45, 50, 55, or 60 nm.

[0289] In some embodiments, a method of forming a transistor T11 ″, a transistor T12 ″, and a transistor T13 ″ may be described as an example. For example, an insulating layer 320 may be formed on a substrate 310. The structure and material of the substrate 310 may be similar to those of FIG. Figure 1E to Figure 1G The structure 110 shown is substantially the same, and a detailed description thereof may be referred to in the preceding paragraph and will not be repeated here. Subsequently, gate structures G11″, G12″, and G13″ may be formed on the insulating layer 320. Each gate structure G11″, gate contact G12″, and gate contact G13″ may include a gate electrode layer 317 and a gate dielectric layer 316.

[0290] By way of example, and not limitation, the gate material can be formed on the insulating layer 320 by a physical vapor deposition (PVD) process, followed by exposure to radiation and dry etching to obtain the gate electrode layer 317. In some embodiments, the gate electrode layer 317 can include Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt, WN, Ru, combinations thereof, or the like. Subsequently, the gate dielectric layer 316 can be conformally deposited as a blanket layer overlying the gate electrode layer 317. In some embodiments, the gate dielectric layer 316 includes one or more high-k dielectric layers. High-k dielectric materials used and described herein include dielectric materials having a high dielectric constant, such as a dielectric constant greater than that of thermal silicon oxide (approximately 3.9). The high dielectric constant dielectric material of the gate dielectric layer 316 may include, for example, hafnium tantalate (HfO2), hafnium tantalum silicon oxide (HfSiO), hafnium tantalum silicon oxide nitride (HfSiON), hafnium tantalum titanate (HfTaO), hafnium tantalum titanium oxide (HfTiO), hafnium zirconate (HfZrO), lanthanum oxide (La2O3), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), ytterbium oxide (Y2O3), strontium titanium iron titanate (SrTiO3, STO), barium titanate (BaTiO3, BTO), barium zirconate (BaZrO), lanthanum scandium oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), etc., or a combination thereof.

[0291] Subsequently, the active region OD11″, the active region OD12″, and the active region OD13″ may be conformally formed on the gate structure G11″, the gate structure G12″, and the gate structure G13″. Specifically, the channel material may be conformally deposited as a blanket layer covering the gate dielectric layer 316, and patterned by photolithography and etching processes (as described above) to separate the continuous channel material into individual active regions OD11″, active regions OD12″, and active regions OD13″, which conformally cover the gate dielectric layer 316. In some embodiments, the channel material may be patterned by a selective etching process. Since the channel material may be formed of a material different from the gate dielectric layer 316, the etching chemistry of the selective etching process may be selected so that the etching rate of the channel material is faster than the etching rate of the gate dielectric layer 316. In some embodiments, the active region OD11″, the active region OD12″, and the active region OD13″. Each of the active regions OD11″, OD12″, and OD13″ may be made of a semiconductor material that can form an ohmic contact with a source line (not shown). Therefore, the active regions OD11″, OD12″, and OD13″ may have source / drain regions S / D11″, S / D12″, and S / D13″ that do not require doped regions, such as n-type or p-type doped regions in the bulk silicon of a complementary metal oxide semiconductor transistor. In some embodiments, the active regions OD11″, OD12″, and OD13″ may include semiconductor materials such as indium gallium zinc oxide (InGaZnO, IGZO), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tungsten oxide (IWO), or combinations thereof. In some embodiments, the active region OD11″, the active region OD12″, and the active region OD13″ may have a channel region 312a, a channel region 312b, and a channel region 312c located between the corresponding source / drain region S / D11″, the source / drain region S / D12″, and the source / drain region S / D13″.

[0292] Subsequently, source / drain contacts MD11″, MD12″, and MD13″ may be conformally formed on the active region OD11″, the active region OD12″, and the active region OD13″. Specifically, the source / drain contact material may be conformally deposited as a blanket layer covering the active region OD11″, the active region OD12″, and the active region OD13″, and then patterned to separate the continuous source / drain contact material into individual source / drain contacts MD11″. For example, for the active region OD11″, the active region OD12″, and the active region OD13″ of the transistors T11″, the transistor T12″, and the transistor T13″ comprising a metal oxide semiconductor, such as indium gallium zinc oxide, these regions may be intrinsic (i.e., neither n-type nor p-type). The behavior of an n-type metal oxide semiconductor or a p-type metal oxide semiconductor may be determined by the voltage applied to the gate structure G11″, the gate structure G12″, and the gate structure G13″ and the work function of the material of the source / drain contact MD11″, the source / drain contact MD12″, and the source / drain contact MD13″. Basically, the transistors T11″, T12″, and T13″ can be designed to accumulate electrons or holes at the interfaces between the active regions OD11″, OD12″, OD13″, and the gate dielectric layer 316, depending on the applied gate voltage and the work functions of the source / drain contacts MD11″, MD12″, and MD13″, so that they function similarly to n-type metal oxide semiconductor (NMOS) or p-type metal oxide semiconductor (PMOS) devices. For example, if the work functions of the source / drain contacts MD11″, MD12″, and / or MD13″ can be aligned with the conduction band of the semiconductor, then when an appropriate gate voltage is applied, an electron accumulation layer can be formed at the interface, thereby obtaining an N-type transistor. If the work function of the source / drain contact MD11 ″, the source / drain contact MD12 ″ and / or the source / drain contact MD13 ″ can be aligned with the valence band of the semiconductor, a hole accumulation layer can be formed, thereby obtaining a p-type transistor.

[0293] Therefore, the portions of the active region OD11″, the active region OD12″, and the active region OD13″ covered by the source / drain contact MD11″, the source / drain contact MD12″, and the source / drain contact MD13″ can serve as the source / drain region S / D11″, the source / drain region S / D12″, and the source / drain region S / D13″, and the portions of the active region OD11″, the active region OD12″, and the active region OD13″ not covered by the source / drain contact MD11″, the source / drain contact MD12″, and the source / drain contact MD13″ can serve as the channel region 312 a, the channel region 312 b, and the channel region 312 c, as shown in FIG. Figure 1M As shown. In some embodiments, the source / drain contact MD11", the source / drain contact MD12", and the source / drain contact MD13" may include aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), ruthenium (Ru), tungsten (W), platinum (Pt), tungsten nitride (WN), iridium (Ru), etc., or a combination thereof. In some embodiments, the source / drain contact MD11", the source / drain contact MD12", and the source / drain contact MD13" may be interchangeably referred to as a source / drain film, a source / drain layer, or a source / drain pattern. In some embodiments, an interlayer dielectric layer 318 on the source / drain contact MD11″, the source / drain contact MD12″, and the source / drain contact MD13″ can be formed by depositing an insulating material on the substrate 310. In some embodiments, the interlayer dielectric layer 318 may include silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass (BPSG), undoped silicate glass, a low dielectric constant insulating material such as fluorosilicate glass, silicon carbon oxide, carbon-doped oxide, a flowable oxide, or a porous oxide (e.g., aerogel / aerogel), or the like, or a combination thereof.

[0294] Subsequently, source / drain vias 322 may be formed on the source / drain contacts MD11″, the source / drain contacts MD12″, and the source / drain contacts MD13″. The source / drain vias 322 may include a metal content material, such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, copper, etc., or a combination thereof, a multilayer structure, etc. Subsequently, a fuse resistor (not shown) may be connected in series to the access transistor T11″. The structures and functions of these elements and their relationship between the transistor T11″ and the fuse resistor are similar to those in FIG. Figures 1D to 1G The transistor T11 and the fuse resistor 104 shown in FIG. 1 are substantially the same, and their detailed descriptions may refer to the previous paragraphs and are not described again here.

[0295] Reference Figures 1N to 1R . Figure 1N 、 Figure 1P and Figure 1R A cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown. Figure 1O and Figure 1Q Some embodiments of the present disclosure are shown. Figure 1N and Figure 1P The local magnified view of the semiconductor structure corresponding to the regions C7 and C8 in FIG. Figures 1N to 1R Draws a picture with Figures 1H to 1M Detailed Description of the Invention The present disclosure includes various cross-sectional view configurations of semiconductor structures in various embodiments. Furthermore, this disclosure may reuse reference numbers and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various discussed embodiments and / or configurations.

[0296] Specifically, if Figure 1A The memory array region 101 shown can be formed at different heights so that the peripheral circuit region 102 can be distributed in the same device area as the memory array region 101, and the transistors in the peripheral circuit region 102 (e.g., Figures 1G to 1I The transistors T12' / T13' shown in FIG. 1 can be connected to the transistors in the memory array region 101 (eg, Figures 1K to 1M The transistor T11 shown is overlapped. Figures 1N to 1R As shown, the height position of the memory array region 101 may be higher than the height position of the peripheral circuit region 102. In some embodiments, the height position of the memory array region 101 may be lower than the height position of the peripheral circuit region 102. In addition, the transistors in the peripheral circuit region 102 may be different types of elements from the transistors in the memory array region 101. For example, the transistors in the peripheral circuit region 102 (e.g., Figures 1G to 1I The transistors T12' / T13' shown in the figure can be gate-around devices, and the transistors in the memory array region 101 (eg, Figures 1K to 1M The transistor T11″ shown may be a thin film transistor element.

[0297] like Figure 1NAs shown, after forming transistor T12' / transistor T13', a back-end-of-line (BEOL) routing structure 330 may be formed on transistor T12' / transistor T13', and is shown schematically without detailing the interconnection method. In some embodiments, transistor T12' may be a sense amplifier, and transistor T13' may be a power supply connector. In some embodiments, an improved read window may be achieved by lowering the threshold voltage of transistor T12'. Therefore, transistor T12' may be a p-type metal oxide semiconductor transistor, whose gate contact (e.g., Figure 1L and Figure 1M The gate contact VG12' shown overlaps with the active region OD12' of the transistor T12'. In some embodiments, by maintaining the threshold voltage of the transistor T13' stable, efficient power utilization can be achieved. Therefore, the transistor T13' can be an n-type metal oxide semiconductor transistor or a p-type metal oxide semiconductor transistor, and its gate contact (such as Figure 1L and Figure 1M The gate contact VG13 ″) is shown not overlapping the active region OD13 ′ of the transistor T13 ′.

[0298] In some embodiments, back-end-of-line (BOL) wiring structure 330 can be formed using a back-end-of-line (BOL) process. Back-end-of-line (BOL) processes involve forming metal wiring between component structures on substrate 210 to connect them to each other, including forming contacts, interconnect wires, via structures, and dielectric structures. Subsequently, dielectric layers 331 and 332 can be formed on back-end-of-line (BOL) wiring structure 330. In some embodiments, dielectric layers 331 and 332 can include silicon oxide (SiO2), silicon carbon nitride (SiCN), or any other suitable material.

[0299] Subsequently, a transistor T11" (e.g., an electronic fuse memory cell) of a memory cell may be formed above the transistor T12' / transistor T13' and laterally surrounded by the dielectric layer 318. The transistor T11" may be configured as a single crystal and a single resistor array, and include a channel region 312a, source / drain regions S / D11" located on both sides of the channel region 312a and connected to the channel region 312a, and a gate structure G11" formed on the channel region 312a. In some embodiments, the leakage current of the memory system may be reduced by increasing the threshold voltage of the transistor T11". Therefore, the transistor T11" may be an n-type metal oxide semiconductor transistor with a gate contact (see Figure 1L and Figure 1MThe gate contact VG11″ shown in FIG1 overlaps with the active region OD11″ of the transistor T11″. This configuration can increase the threshold voltage, thereby reducing leakage current. In some embodiments, the stacked transistor T11″ (e.g., a three-dimensional indium gallium zinc oxide (IGZO) element) can achieve efficient and precise control of threshold voltage (Vt) variations, thereby allowing clear separation of different Vt variations to optimize the balance between higher battery current and lower battery leakage current. Higher battery current promotes improved performance, while lower leakage current achieves higher power efficiency. In addition, the stacked three-dimensional transistor T11" (for example, a stacked three-dimensional indium gallium zinc oxide element) can achieve a smaller unit area, which contributes to a more compact and efficient layout; conversely, the bit cell current can be significantly improved to achieve a bit cell current, for example, at least about three times that of other designs. The source / drain contact MD11" can be conformally formed on the active region OD11". The source / drain through hole 322 can be formed on the source / drain contact MD11", the source / drain contact MD12", and the source / drain contact MD13".

[0300] Subsequently, a fuse resistor 104 may be formed on the transistor T11″ and connected in series to the access transistor T11″. The fuse resistor 104 may include a bottom electrode layer 104a, a top electrode layer 104c, and a fuse layer 104b between the bottom electrode layer 104a and the top electrode layer 104c. The fuse layer 104b may be a metal-containing layered structure, but is not limited to TiO. x 、NiO x , HfO x 、NbO x 、CoO x 、FeO x , CuO x , VO x 、TaO x , WO x CrO xand combinations thereof. For example, the fuse layer 104b may include materials such as tantalum nitride (TaN), an alloy of Ti and TiN, an alloy of Ta and TaN, or a combination thereof. In some embodiments, the bottom electrode layer 104a and the top electrode layer 104c may include aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), ruthenium (Ru), tungsten (W), platinum (Pt), tungsten nitride (WN), iridium (Ru), etc., or combinations thereof. Metal wiring 334 and metal wiring 335 may be formed to clamp the fuse resistor 104 so as to interconnect the fuse resistor 104 with the component structure (not shown) on the substrate 210. In some embodiments, the fuse resistor 104 and the metal wiring 334 and metal wiring 335 may be formed in the dielectric layer 336.

[0301] Reference Figure 1O The structure and function of the transistor T21 ″ including the channel region 412 a, the source / drain region S / D21 ″ and the gate structure G21 ″ located on the channel region 412 a are similar to those of the transistor T21 ″. Figure 1N The structure and function of the transistor T11 ″ including the channel region 312 a, the source / drain region S / D11 ″ and the gate structure G11 ″ located on the channel region 312 a are substantially the same. For detailed descriptions thereof, reference may be made to the aforementioned paragraphs and will not be described again here. It is worth noting that this embodiment is different from Figure 1N The difference between the embodiments is that the vertical dimension of the transistor T21″ can be larger than that of the transistor T11″. Figure 1O As shown, the transistor T21″ may include an active region OD21″ having an inverted U-shaped cross-sectional profile. The structure of the transistor T21″ may allow its vertical dimension to be greater than its lateral dimension, so that the vertical dimension R1 of the active region OD21″ may be increased without affecting the 2D area, thereby maintaining a compact footprint of the component. In some embodiments, the vertical dimension R1 of the active region OD21″ is greater than the lateral dimension W1 of the active region OD21″. Increasing the vertical dimension R1 of the active region OD21″ may increase the contact area between the active region OD21″ and the corresponding metal contact MD21″. The larger contact area between the active region OD21″ and the metal contact MD21″ may reduce the contact resistance, thereby facilitating the flow of current. Specifically, lower contact resistance means that the transistor T21″ can conduct a higher current when the same voltage is applied. Therefore, by increasing the vertical dimension R1 of the active region OD21″, the current driving capability of the transistor may be increased, thereby improving the overall performance of the transistor T21″ without the need for an additional two-dimensional (2D) area.

[0302] Reference Figure 1P The structure and function of the transistor T31 ″ including the source / drain contact MD31 ″ and the channel region 512 a (located in the active region OD31 ″), the source / drain region S / D31 ″ (located in the active region OD31 ″) and the gate structure G31 ″ formed on the channel region 512 a are substantially the same as those of the transistor T31 ″. Figure 1N The structure and function of the source / drain contact MD11″ and the transistor T11″ including the channel region 312a, the source / drain region S / D11″ and the gate structure G11″ are the same. The relevant detailed description can be referred to above and will not be described again here. It is worth noting that this embodiment is different from Figure 1N The difference between the embodiments in is that the source / drain contact MD31" can be two layers landing on the dielectric layer 331. The active region OD31" can be conformally formed on the source / drain contact MD31", and extend laterally continuously from one source / drain contact MD31" to another source / drain contact MD31" along the top surface of the dielectric layer 332. The gate structure G31" can include a gate electrode layer 517 and a gate dielectric layer 516. The gate dielectric layer 516 is conformally formed on the active region OD31", and the gate electrode layer 517 can be formed on the gate dielectric layer 516 and laterally located between the source / drain contacts MD31". In some embodiments, the source / drain through-hole 322 can be formed through the active region OD31" and the gate dielectric layer 516, and land on the source / drain contact MD31". Therefore, the source / drain contact configuration can increase the contact area between the source / drain regions S / D31″ of the active region OD31″ and the corresponding metal contacts MD31″. A larger contact area can reduce contact resistance, thereby facilitating the flow of current. Specifically, lower contact resistance means that the transistor T31″ can conduct a higher current when the same voltage is applied. Therefore, the current driving capability of the transistor can be improved, thereby improving the overall performance of the transistor T31″.

[0303] Reference Figure 1Q The structure and function of the transistor T41″ including the channel region 612a (located in the active region OD41″), the source / drain region S / D41″ (located in the active region OD41″) and the gate structure G41″ formed on the channel region 412a are basically the same as those of the transistor T41″. Figure 1P The structure and function of the transistor T31 ″ including the channel region 512 a, the source / drain region S / D31 ″ and the gate structure G31 ″ are the same, and the relevant detailed description can be referred to above and will not be described again here. It is worth noting that this embodiment is different from Figure 1P The difference between the embodiments in FIG. 1 and FIG. 2 is that the transistor T41 ″ may have a larger vertical dimension than the transistor T31 ″. Figure 1QIn the embodiment, the vertical dimensions R3 and R4 of the source / drain contact MD41″ and the gate electrode layer 617 of the gate structure G41″ can be increased without affecting the two-dimensional area, thereby maintaining a compact footprint of the component. In some embodiments, the vertical dimension R3 of the source / drain contact MD41″ can be greater than Figure 1P The vertical dimension R5 of the source / drain contact MD31" shown in FIG. 1 and the vertical dimension R4 of the gate electrode layer 617 of the gate structure G41" may be greater than Figure 1P The gate electrode layer 517 of the gate structure G31″ shown has a vertical dimension R6.

[0304] In some embodiments, increasing the vertical dimension R3 of the active region OD41″ can increase the contact area between the source / drain regions S / D41″ of the active region OD41″ and the corresponding metal contacts MD41″. A larger contact area can reduce contact resistance, thereby facilitating current flow. Specifically, lower contact resistance means that the transistor T41″ can conduct a higher current under the same applied voltage. Therefore, by increasing the vertical dimension R3 of the active region OD41″, the current driving capability of the transistor can be increased, improving the overall performance of the transistor T41″ without requiring additional two-dimensional regions. Furthermore, increasing the vertical dimension R4 of the active region OD41″ can increase the contact area between the source / drain regions S / D41″ of the active region OD41″ and the corresponding metal contacts MD41″, thereby increasing the gate electrode-gate dielectric contact area between the gate electrode layer 617 and the gate dielectric layer 616, thereby improving gate control. In some embodiments, a larger gate electrode-gate dielectric contact area means that the gate voltage can affect a larger volume of the semiconductor, thereby enhancing the gate's control over the operation of the transistor.

[0305] Reference Figure 1R The structure and function of this structure are similar to Figure 1N The structure and function of the structure shown in FIG are basically the same. For the related detailed description, please refer to the previous text and will not be described again here. Figure 1R The implementation method in Figure 1N The difference between the implementations in Figure 1R The transistor T11" shown in FIG. 1 is an anti-fuse memory cell. Therefore, there are two transistors T11" connected to each other via the source / drain region S / D11". The structure and function of the anti-fuse memory cell will be explained in more detail later (see FIG. Figure 8A ).

[0306] Reference Figures 2A to 7B . Figures 2A to 7BA cross-sectional view is shown of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments of the present disclosure. Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A and 7A The figure shows the Figure 1A Cross-sectional views obtained from reference cross section AA', reference cross section BB' and reference cross section CC'. Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B and Figure 7B Draws from Figure 1A The cross-sectional views obtained from the reference cross-section D-D', reference cross-section E-E' and reference cross-section F-F' in FIG. Figures 2A to 7B Other operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for other embodiments of the method. The order of the operations / processes may be interchanged.

[0307] Reference Figure 2A and Figure 2B One or more dielectric isolation structures 111 may be formed in the substrate 110 to define the active region OD11, the active region OD12, and the active region OD13. Forming the dielectric isolation structures 111 includes, for example, but is not limited to, etching the substrate 110 to form one or more trenches defining the active region OD11, the active region OD12, and the active region OD13, depositing one or more dielectric materials (e.g., silicon oxide) to fill the trenches in the substrate 110, and then performing a chemical mechanical polishing process to make the one or more dielectric isolation structures 111 planar with the substrate 110. The dielectric isolation structures 111 may be further recessed (e.g., by an etch back process) to be lower than the top surfaces of the active regions OD11, the active regions OD12, and the active regions OD13, so that the active regions OD11, the active regions OD12, and the active regions OD13 protrude from the top surfaces of the recessed dielectric isolation structures 111 to form a fin-like structure. In some embodiments, the active region OD11 may be formed in the memory array region 101, and the active region OD12 and the active region OD13 may be formed in the peripheral circuit region 102. Subsequently, a transistor T11 (see FIG. 1 ) belonging to a memory element may be formed in the active region OD11. Figure 7A and Figure 7B ), a transistor T12 belonging to a sense amplifier is formed in the active region OD12 and the active region OD13 (see Figure 7A and 7B Figure) and transistor T13 belonging to the power supply connection (see Figure 7Aand Figure 7B ).

[0308] Reference Figure 3A and Figure 3B After forming one or more dielectric isolation structures 111, a sacrificial gate structure 130 is formed on the active region OD11, the active region OD12, and the active region OD13. The sacrificial gate structure 130 may include one or more sacrificial gate structures 130, including one or more sacrificial gate structures 130, such as a sacrificial gate dielectric layer 114, and a sacrificial gate electrode 115 on the sacrificial gate dielectric layer 114. In some embodiments, for example but not limited to, one or more sacrificial gate dielectric materials (such as silicon oxide, silicon nitride, etc.) may be deposited on the substrate 110, and then one or more sacrificial gate materials (such as doped or undoped polysilicon) may be deposited, and then the polysilicon may be planarized by a process such as chemical mechanical polishing, and then the polysilicon material and the sacrificial gate dielectric material may be patterned using appropriate photolithography and etching techniques to form each sacrificial gate structure 130 including a sacrificial gate dielectric material and a sacrificial gate material to serve as its corresponding sacrificial gate dielectric layer 114 and sacrificial gate 115.

[0309] Reference Figure 4A and Figure 4B . Gate spacers 113 are then formed on opposing sidewalls of each sacrificial gate structure 130 . In some embodiments, the gate spacers 113 are formed by, for example, depositing and anisotropically etching a gap dielectric layer after patterning of the sacrificial gate is complete. In some embodiments, the gap dielectric layer can include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, similar materials, or combinations thereof. The anisotropic etching process removes the gap dielectric layer from the top of the sacrificial gate structure 130 while retaining the gate spacers 113 along the sidewalls of the sacrificial gate structure 130 .

[0310] Reference Figure 5A and Figure 5BAfter the gate spacer structure 113 is formed, source / drain regions S / D11, S / D12, and S / D13 are formed in the active regions OD11, OD12, and OD13 and are self-aligned with the gate spacer structure 113. Portions of the active regions OD11, OD12, and OD13 between the corresponding source / drain regions S / D11, S / D12, and S / D13 (i.e., fin structures) may serve as the channel regions 112a, 112b, and 112c. In some embodiments, the source / drain regions S / D11, S / D12, and S / D13 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. During the epitaxial process, the source / drain regions S / D11, S / D12, and S / D13 can be in-situ doped by introducing dopant species (including p-type dopants such as boron or BF2; n-type dopants such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof). If the source / drain regions S / D11, S / D12, and S / D13 are not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain regions S / D11, S / D12, and S / D13. In some exemplary embodiments, the n-type source / drain regions S / D11, S / D12, and S / D13 include Si:P. In some embodiments, the source / drain region S / D11 , the source / drain region S / D12 , and the source / drain region S / D13 may be interchangeably referred to as source / drain regions, source / drain patterns, or source / drain structures.

[0311] Reference Figure 6A and Figure 6B. The sacrificial gate structure 130 is replaced with the gate structure G11, the gate structure G12, and the gate structure G13. The manufacture of the source / drain region S / D11, the source / drain region S / D12, and the source / drain region S / D13 and the gate structure G11, the gate structure G12, and the gate structure G13 of the transistor can be referred to as a front-end-of-line (FEOL) process. Specifically, an interlayer dielectric layer 118 covering the source / drain region S / D11, the source / drain region S / D12, and the source / drain region S / D13 can be formed by depositing an insulating material on the source / drain region S / D11, the source / drain region S / D12, and the source / drain region S / D13 and then planarizing the insulating material (for example, using a chemical mechanical polishing process) to expose the sacrificial gate structure 130. Subsequently, the gate replacement process includes, for example, but not limited to, removing the sacrificial gate structure 130 using one or more etching techniques (e.g., dry etching, wet etching, or a combination thereof) to form gate trenches between the respective gate spacers 113. Next, a gate dielectric layer 116 comprising one or more insulating materials may be deposited, followed by a gate electrode layer 117 comprising one or more metals to completely fill the gate trenches. Excess portions of the gate dielectric layer 116 and gate electrode layer 117 may then be removed from the top surface of the interlayer dielectric layer 118 using, for example, a chemical mechanical polishing process. In some embodiments, according to Figure 6A and Figure 6B As shown, the resulting structure may include remaining portions of the gate dielectric layer 116 and the gate electrode layer 117 embedded between respective gate spacer structures 113 , serving as the gate structure G11 , the gate structure G12 , and the gate structure G13 .

[0312] In some embodiments, the gate dielectric layer 116 includes a stack of an interfacial dielectric material and a high-k dielectric material. In some embodiments, the high-k gate dielectric material includes, but is not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, zirconium oxide, titanium oxide, aluminum oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate metal is formed on the gate dielectric. The gate metal layer 117 is a single-layer structure or a multi-layer structure, including copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum silicon oxynitride (TaSiN), tungsten (W), tungsten nitride (WN), molybdenum nitride (MoN), etc. and / or combinations thereof. In some embodiments, the materials used to form the gate structures G11, G12, and G13 can be deposited by any suitable method, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), electrochemical plating (ECP), electroless chemical deposition, etc. In some embodiments, the interlayer dielectric layer 118 may include silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, a low dielectric constant dielectric material such as fluorosilicate glass, silicon oxide carbide, carbon-doped oxide, a flowable oxide, or a porous oxide (e.g., xerogels / aerogels), etc., or a combination thereof.

[0313] Reference Figure 7A and Figure 7B. An interlayer dielectric layer 128 may be formed over the gate structure G11, the gate structure G12, and the gate structure G13 using a suitable deposition process, and then gate contacts VG11, VG12, and VG13 may be formed on the interlayer dielectric layer 128 and over the gate structures G11, G12, and G13. In some embodiments, the material of the interlayer dielectric layer 128 is the same as that of the interlayer dielectric layer 118. After depositing the interlayer dielectric layer 128, the gate contacts VG11, VG12, and VG13 may be formed using photolithography, etching, and deposition techniques. For example, in some embodiments, a patterned mask may be formed on the interlayer dielectric layer 128 for etching through the interlayer dielectric layer 128 to expose contact openings for the gate structure G11, G12, and G13. Then, one or more metals may be filled into the contact openings in the interlayer dielectric layer 128 using any acceptable deposition technique (e.g., CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, or a combination thereof). Next, a planarization process (e.g., a chemical mechanical polishing process) may be used to remove excess metal from the top surface of the interlayer dielectric layer 128. The resulting conductive plugs fill the contact openings in the interlayer dielectric layer 128 and correspond to gate contacts VG11, VG12, and VG1, which are physically and electrically connected to the gate structures G11, G12, and G13.

[0314] By increasing the threshold voltage of transistor T11 in bit cell 102 of memory system 100, current leakage can be minimized. Therefore, transistor T11 can be an n-type metal oxide semiconductor transistor, where the gate contact VG11 overlaps the active region OD11 of transistor T11. This configuration increases the threshold voltage, thereby reducing current leakage. Furthermore, for the sense amplifier within bit cell 102 in peripheral circuit region 102, an improved read window can be achieved by lowering the threshold voltage of transistor T12, which serves as the sense amplifier. Therefore, transistor T12 can be a p-type metal oxide semiconductor transistor, where the gate contact VG12 overlaps the active region OD12 of transistor T12. This configuration lowers the threshold voltage, thereby expanding the read window and improving the performance of the sense amplifier. Furthermore, for the power supply terminal in peripheral circuit region 102, efficient power utilization can be achieved by stabilizing the threshold voltage of transistor T13 in the power supply terminal. Therefore, transistor T13 can be an n-type metal oxide semiconductor transistor or a p-type metal oxide semiconductor transistor, wherein the gate contact VG13 does not overlap with the active region OD13 of transistor T13. This configuration can keep the threshold voltage of transistor T13 stable and prevent threshold voltage drift, thereby facilitating efficient power utilization within memory system 100.

[0315] In some embodiments, gate contact VG11, gate contact VG12, and gate contact VG13 may include a metal-containing material, such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, copper, combinations thereof, multi-layer structures, etc. In some embodiments, interlayer dielectric layer 128 may include silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, a low-k insulating material (such as fluorosilicate glass, silicon oxycarbide, carbon-doped oxide, flowable oxide, porous oxide (such as xerogels / aerogels), etc., or a combination thereof.

[0316] refer to Figures 8A to 10 . Figure 8A A circuit diagram of an antifuse memory cell according to some embodiments of the present disclosure is shown. Figures 8B to 10 The bit cell 103a in some embodiments of the present disclosure is shown (see Figures 8B to 8E ), bit unit 103b (see Figures 9A to 9E ), bit unit 103c (see Figure 10 ) and bit cell 103d (see Figure 1B ). In some embodiments, Figure 1A The bit cell 103 shown in FIG. 1 may be replaced by the bit cell 103a, the bit cell 103b, the bit cell 103c and / or the bit cell 103d. In some embodiments, Figures 8B to 10 The bit cells 103a, 103b and 103b shown in FIG may include, but are not limited to, antifuse memory cells. Figures 8B to 10 Implementations of bit cells 103a, 103b, and 103c with different gate contact locations are shown. Figures 1A to 7B The bit cell 103 shown in FIG.

[0317] like Figure 8A As shown, the circuit of the antifuse memory cell is coupled to the programming word line WLP, the reading word line WLR, the source line SL, and the bit line BL. The antifuse memory cell may include a programming transistor TP and a reading transistor TR. Examples of the programming transistor TP and / or the reading transistor TR may include, but are not limited to, FinFET devices, nanoFET devices, and / or thin film transistor devices. In some embodiments, the programming transistor TP and the reading transistor TR have the same configuration. For example, the programming transistor TP and the reading transistor TR have the same size and are manufactured using the same process.

[0318] The programming transistor TP may include a gate terminal 710 coupled to the programming word line WLP, a first terminal 711 coupled to the source line SL, and a second terminal 712 coupled to the second terminal 712 of the programming transistor TP. The read transistor TR may include a gate terminal 720 coupled to the read word line WLR, a first terminal 721 coupled to the bit line BL, and a second terminal 722 coupled to the second terminal 712 of the programming transistor TP. In other words, the programming transistor TP and the read transistor TR are coupled together in series. In some embodiments, the first terminal 711 may be the source / drain region of the programming transistor TP, and the second terminal 712 may be another source / drain region of the programming transistor TP. The first terminal 721 may be the source / drain region of the read transistor TR, and the second terminal 722 may be another source / drain region of the read transistor TR. In some embodiments, the second terminal 712 of the programming transistor TP and the second terminal 722 of the read transistor TR are the same, that is, the programming transistor TP and the read transistor TR share a common source / drain region.

[0319] In some embodiments, the operation of the antifuse memory cell is controlled by a controller. The controller is coupled to the antifuse memory cell through the programming word line WLP, the read word line WLR, the source line SL, and the bit line BL. When the antifuse memory cell is selected in a programming operation, the controller is configured to apply a higher voltage to the first terminal 711 of the programming transistor TP through the source line SL, and to apply a lower voltage to the gate terminal 710 of the programming transistor TP through the programming word line WLP. The controller is configured to turn off the read transistor TR during the programming operation. The voltage difference between the higher voltage on the first terminal 711 and the lower voltage on the gate terminal 710 is equal to or higher than a predetermined breakdown voltage sufficient to break down the gate dielectric layer of the programming transistor TP. Therefore, the gate dielectric layer of the programming transistor TP is broken down, and the programming current I prog The antifuse memory cell is programmed by flowing from the source line SL through the programming transistor TP to the programming word line WLP. In some embodiments, the voltage applied to the programming word line WLP is ground, while the voltage applied to the source line SL is a higher programming voltage.

[0320] When the antifuse memory cell is selected in a read operation, the controller is configured to apply a turn-on voltage to the gate terminal 720 of the read transistor through the read word line WLR to turn on the read transistor TR. The controller is further configured to apply a read voltage to the first terminal 711 and the gate terminal 710 of the programming transistor TP through the source line SL and the programming word line WLP respectively to detect the data stored in the antifuse memory cell when the read transistor TR is turned on. For example, the controller is configured to sense a read current head flowing from the programming transistor TP through the turned-on read transistor TR to the bit line BL by using a sense amplifier or the like. When the antifuse memory cell has been programmed to store logic "0", the current value of the read current head is different from the current value of the read current when the antifuse memory cell has not been programmed and still stores logic "1". By sensing the current value of the read current, the controller is configured to detect the data stored in the antifuse memory cell.

[0321] refer to Figures 8B to 9E . Figure 8B and Figure 9A A top view of a semiconductor structure according to some embodiments of the present disclosure is shown. Figures 8C to 8E According to some embodiments of the present disclosure, Figure 8B Cross-sectional views of the semiconductor structure obtained from the reference cross-section C1 - C1 ′, the reference cross-section D1 - D1 ′, and the reference cross-section E1 - E1 ′. Figures 9B to 9E According to some embodiments of the present disclosure, Figure 9A Cross-sectional views of the semiconductor structure obtained from the reference cross-section B2-B2', the reference cross-section C2-C2', the reference cross-section D2-D2' and the reference cross-section E2-E2'. Figures 8A to 9E Embodiments of semiconductor structures with different bit cell configurations are shown. Figures 1A to 1Q The semiconductor structures used are different. Furthermore, this disclosure may repeat reference numbers and / or letters throughout various examples. This repetition is for simplicity and clarity and does not in itself dictate the relationship between the various embodiments and / or configurations discussed. The semiconductor structures are non-limiting examples for the purpose of illustrating the present disclosure.

[0322] like Figures 8B to 9EAs shown, the gate structure G11 connected to the programming word line WLP can be interchangeably referred to as a programming transistor, and the gate structure G11 connected to the read word line WLR can be interchangeably referred to as a read transistor. In some embodiments, in order to reduce leakage current in the memory system, it can be achieved by enhancing the threshold voltage of the transistor T11 connected to the programming word line WLP. Therefore, the transistor T11 connected to the programming word line WLP can be an n-type metal oxide semiconductor transistor, and its gate contact VG11 overlaps with the active region OD11 of the transistor T11 connected to the programming word line WLP. This configuration can increase the threshold voltage, thereby reducing current leakage. In addition, the transistor T11 connected to the read word line WLR can also be an n-type metal oxide semiconductor transistor, and its gate contact VG11 (see Figures 8B to 8E ) overlaps with the active region OD11 of the transistor T11 connected to the read word line WLR. In some embodiments, the transistor T11 connected to the read word line WLR may also be an n-type metal oxide semiconductor transistor, whose gate contacts VG11 (see Figures 9A to 9E ) does not overlap with the active region OD11 of the transistor T11 connected to the read word line WLR.

[0323] refer to Figure 10 . Figure 10 A top view of a semiconductor structure according to some embodiments of the present disclosure is shown. Figure 10 It depicts a different Figures 8B to 9E Detailed descriptions of embodiments and configurations of semiconductor structures in the present disclosure are provided. It should be noted that reference numbers and / or letters may be repeated throughout this disclosure. This repetition is for simplicity and clarity and does not inherently dictate the relationship between the various embodiments and / or configurations discussed. The semiconductor structures are provided as non-limiting examples for purposes of illustrating the present disclosure.

[0324] like Figure 10As shown, the gate structure G11 can extend across multiple active regions OD11. In some embodiments, by increasing the threshold voltage of the transistor T11 connected to the programming word line WLP (i.e., the programming transistor), current leakage can be reduced in the memory system. Therefore, the transistor T11 connected to the programming word line WLP can be an n-type metal oxide semiconductor transistor, whose gate contact VG11 overlaps with the active region OD11 of the transistor T11 connected to the programming word line WLP. This configuration can increase the threshold voltage and thus reduce current leakage. In some embodiments, the gate contact VG11 on the programming transistor can be separated from the edge B11 of the active region OD11 by at least a lateral distance D5. For example, the distance D5 may be approximately greater than 5 nanometers, such as approximately 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15 nanometers. Furthermore, the transistor T11 connected to the read word line WLR (i.e., the read transistor) may also be an n-type metal oxide semiconductor transistor, with its gate contact VG11 not overlapping the active region OD11 of the transistor T11 connected to the read word line WLR, such that the gate contact VG11 can be located between two adjacent read transistors. In some embodiments, the gate contact VG11 on the read transistor can be separated from the edge B11 of the active region OD11 by at least a lateral distance D5'. For example, the distance D5' may be greater than approximately 15 nanometers, such as approximately 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, or 25 nanometers. In some embodiments, the distance D5' can be greater than the distance D5.

[0325] refer to Figures 11A to 14 . Figures 11A to 14 Various views of a semiconductor structure including transistors (e.g., sense amplifier transistors and power tap transistors) in a peripheral region of a memory system are shown, according to some embodiments of the present disclosure. Examples of transistors in the peripheral region may include, but are not limited to, FinFET devices, nanoFET devices, and / or thin-film transistor devices. Figure 11A and Figures 12 to 14 A top view of a semiconductor structure according to some embodiments of the present disclosure is shown. Figures 11B to 11E Some embodiments of the present disclosure are shown. Figure 11A Cross-sectional views of the semiconductor structure obtained from the reference cross-section B3-B3', the reference cross-section C3-C3', the reference cross-section D3-D3' and the reference cross-section E3-E3'. Figures 11A to 14 Draws the Figure 1ADetailed descriptions of semiconductor structures with different gate contact configurations are provided herein. It should be noted that reference numbers and / or letters may be repeated throughout this disclosure. This repetition is for simplicity and clarity and does not inherently dictate the relationship between the various embodiments and / or configurations discussed. The semiconductor structures are provided as non-limiting examples for purposes of illustrating this disclosure.

[0326] In some embodiments, as Figure 1A The semiconductor structure in the peripheral circuit region 102 may be Figures 11A to 14 In some embodiments, the semiconductor structure including the transistor T13 can be used as a power supply terminal. Figures 11A to 11E As shown, the interaction between the gate contact VG13 and the active region OD13 exhibits an intermittent pattern configuration. Some gate contacts VG13 periodically overlap or cover the active region OD13, while others are intermittently located outside the active region OD13. In some embodiments, when the gate contact VG13 of transistor T13 is located overlapping the active region OD13, the resulting threshold voltage (Vt) may be approximately -10 millivolts. When the gate contact VG13 is located not overlapping the active region OD13, the resulting threshold voltage (Vt) is approximately 0 millivolts. Considering these two conditions, it can be shown that the overall threshold voltage Vt stabilizes at the average of the two individual conditions. In other words, the overall threshold voltage Vt may be approximately -5 millivolts. Therefore, this dynamic process provides additional embodiments for device operating conditions and can affect the placement of the gate contact VG13 relative to the active region OD13.

[0327] Figure 12 illustrates the changes in this design, with Figures 11A to 11E The main difference lies in the arrangement of the gate contacts VG13. There are at least two adjacent gate contacts VG13 covering the active region OD13, followed by a sequence of at least two adjacent gate contacts VG13 outside the active region OD13. Figure 13 A variation is shown in which all gate contacts VG13 can be located outside the active region OD13. These gate contacts VG13 can be dynamically positioned as they gradually approach or move away from the edge B13 of the active region OD13. In some embodiments, the maximum distance between the gate contacts VG13 and the edge of the active region OD13 can be limited to no more than 50 nanometers, while the minimum distance can be no less than 19 nanometers. Figure 14A variation is illustrated in which all gate contacts VG13 can be located on the active region OD13. These gate contacts VG13 can exhibit dynamic positioning as they gradually approach or move away from the edge B13 of the active region OD13. In some embodiments, the maximum distance from the edge can be limited to no more than 11 nanometers. Overall, these different configurations of gate contacts relative to the active region OD13 can illustrate the versatility of design and optimization possibilities in the peripheral circuit region 102, providing room for adjusting the performance characteristics of transistors (e.g., power tap transistors) to meet specific requirements.

[0328] Figure 15 FIG1 is a diagram of an electronic design automation (EDA) system 1600, according to some embodiments. The methods described herein for generating a design layout, such as the layout of the memory system 100 discussed above, according to one or more embodiments, can be implemented using the EDA system 1600, according to some embodiments. The memory system 100 is manufactured using a layout design similar to that of a corresponding integrated circuit. For simplicity, Figures 1A to 14 are described as corresponding integrated circuits, but in some embodiments, Figures 1A to 14It also corresponds to a layout design having a corresponding pattern configuration similar to the corresponding structure, and includes alignment of the length and width of the layout design, as well as pattern configuration relationships, similar to the structural relationships, configurations, and hierarchies of the corresponding integrated circuit. A similar detailed description will not be provided for the sake of brevity. In some embodiments, electronic design automation system 1600 is a computing element capable of performing one or more automatic placement and routing (APR) operations. Electronic design automation system 1600 includes a hardware process 1602 and a non-volatile computer-readable storage medium 1604. Computer-readable storage medium 1604, among other things, is encoded with, i.e., stores, a set of executable instructions 1606, design layouts 1607, a design rule check (DRC) platform 1609, or any intermediate data for executing the instruction set. Each design layout 1607 may include a graphical representation of an integrated circuit, such as a GSII file. Each design rule check platform 1609 may include a list of design rules applicable to selecting a semiconductor process for manufacturing design layout 1607. The hardware process device 1602 executes the instructions 1606, the design layout 1607, and the design rule checking platform 1609, indicating that the hardware process device 1602 represents an electronic design automation tool that (at least partially) implements some or all of the above-described method. In one or more embodiments, the process device 1602 is a central processing unit (CPU), a multi-processor, a distributed process system, an application specific integrated circuit (ASIC), and / or an appropriate process unit.

[0329] Processor 1602 is electrically connected to computer-readable storage medium 1604 via bus 1608. Processor 1602 is also electrically connected to input / output interface 1610 via bus 1608. Network interface 1612 is also electrically connected to processor 1602 via bus 1608. Network interface 1612 is connected to network 1614, enabling processor 1602 and computer-readable storage medium 1604 to connect to external elements via network 1614. Processor 1602 is configured to execute instructions 1606 encoded on computer-readable storage medium 1604 to enable electronic design automation system 1600 to perform some or all of the methods described above. In one or more embodiments, processor 1602 is a central processing unit, a multi-processor, a distributed processing system, an application-specific integrated circuit, and / or a suitable processing unit.

[0330] In one or more embodiments, the computer-readable storage medium 1604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or element). For example, the computer-readable storage medium 1604 includes semiconductor or solid-state memory, magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1604 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disc (DVD).

[0331] In one or more embodiments, computer-readable storage medium 1604 stores instructions 1606, a design layout 1607 (e.g., the layout of memory system 100 discussed above), and a design rule checking platform 1609 configured to enable electronic design automation system 1600 (where such execution is at least partially representative of an electronic design automation tool) to perform some or all of the above-described methods. In one or more embodiments, storage medium 1604 also stores information that facilitates the performance of some or all of the above-described methods.

[0332] Electronic design automation system 1600 includes an input / output interface 1610. The input / output interface 1610 interfaces with external circuitry. In one or more embodiments, the input / output interface 1610 includes a keyboard, a keyboard, a mouse, a trackball, a touchpad, a touch screen, and / or cursor keys for transmitting information and commands to the process device 1602.

[0333] Electronic design automation system 1600 also includes a network interface 1612 connected to process device 1602. Network interface 1612 allows electronic design automation system 1600 to communicate with a network 1614, to which one or more other computer systems are connected. Network interface 1612 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface such as Ethernet, USB, or IEEE-1388. In one or more embodiments, part or all of one or more of the above methods are implemented in two or more electronic design automation systems 1600.

[0334] Electronic design automation system 1600 is configured to receive information via input / output interface 1610. The information received via input / output interface 1610 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters of a process executed by process controller 1602. The information is transmitted to process controller 1602 via bus 1608. Electronic design automation system 1600 is configured to receive information related to user interface (UI) 1616 via input / output interface 1610. The information is stored in computer-readable medium 1604 as user interface 1616.

[0335] Figure 15 Also shown are fabrication tools associated with electronic design automation system 1600. For example, a mask factory 1630 receives a design layout from electronic design automation system 1600, for example, via network 1614. Mask factory 1630 includes a mask fabrication tool 1632 (e.g., a mask fabricator) for fabricating one or more photomasks (e.g., photomasks for fabricating memory system 100, as discussed above, including resistor circuits) based on the design layout generated by electronic design automation system 1600. An integrated circuit fabricator ("Fab") 1620 can be connected to mask factory 1630 and electronic design automation system 1600 via network 1614. IC fabricator 1620 includes an IC fabrication tool 1622 for fabricating integrated circuit wafers using the photomasks fabricated by mask factory 1630 (e.g., the layout of memory system 100, as discussed above, including resistor circuits, fabricated using the photomasks fabricated by mask factory 1630). For example, the integrated circuit fabrication tool 1622 includes one or more cluster tools for fabricating integrated circuit wafers. The cluster tool can be a multi-chamber complex comprising a polyhedral transfer chamber into which a robot for processing wafers is inserted, a plurality of process chambers (e.g., chemical vapor deposition chambers, PVD chambers, etch chambers, annealing chambers, or the like) located on each wall of the polyhedral transfer chamber, and a load lock chamber mounted on a different wall of the transfer chamber.

[0336] Figure 16 FIG1 is a block diagram of an integrated circuit fabrication system 1700 and an associated integrated circuit fabrication process, according to some embodiments. In some embodiments, fabrication system 1700 is used to fabricate one or more photomasks and one or more integrated circuits based on one or more design layouts, such as the layout of memory system 100 discussed above.

[0337] exist Figure 16In the embodiment, integrated circuit manufacturing system 1700 includes entities, such as a design site 1720, a mask factory 1730, and an integrated circuit manufacturing site 1750. These entities interact with each other and participate in the design, development, and manufacturing cycles associated with manufacturing integrated circuits 1760 and / or provide manufacturing-related services. The entities in integrated circuit manufacturing system 1700 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design site 1720, mask factory 1730, and integrated circuit manufacturing site 1750 are owned by a single, larger company. In some embodiments, two or more of the design site 1720, mask factory 1730, and integrated circuit manufacturing site 1750 are co-located in a common facility and utilize common resources.

[0338] The design end (or design company / team) 1720 generates a design layout 1722 (e.g., the layout of the memory system 100 discussed above). The design layout 1722 includes various geometric patterns designed for the integrated circuit 1760 (e.g., the memory system 100 discussed above). These geometric patterns correspond to the patterns of the various metal, oxide, or semiconductor layers that make up the integrated circuit 1760 to be manufactured. The various layers combine to form various component features. For example, a portion of the design layout 1722 includes various circuit features, such as active regions, passive regions, functional gate structures, resistive structures, gate contacts, resistive contacts, source / drain contacts, and / or metal lines, which will be formed on the semiconductor wafer. The design end 1720 implements an appropriate design program to generate the design layout 1722. The design program includes one or more of logical design, physical design, or placement and routing. The design layout 1722 is presented in the form of one or more data files containing geometric pattern information and a netlist of various nets. For example, the design layout 1722 can be represented in a GDSII file format or a DFII file format.

[0339] The mask factory 1730 includes data preparation 1732 and mask manufacturing 1744. The mask factory 1730 uses the design layout 1722 (e.g., the layout of the memory system 100 discussed above) to manufacture one or more photomasks 1745 for manufacturing layers of an integrated circuit 1760 based on the design layout 1722. The mask factory 1730 performs mask data preparation 1732, in which the design layout 1722 is converted into a representative data file (RDF). The mask data preparation 1732 provides the representative data file to the mask manufacturing 1744. The mask manufacturing 1744 includes a mask maker. The mask maker converts the representative data file into an image on a photomask (or reticle) 1745 based on the design layout 1722. The design layout 1722 is manipulated by the mask data preparation 1732 to conform to the specific characteristics of the mask maker and / or the rules of the integrated circuit manufacturing end 1750. In Figure 16 , mask data preparation 1732 and mask fabrication 1744 are depicted as separate elements. In some implementations, mask data preparation 1732 and mask fabrication 1744 can be collectively referred to as mask data preparation.

[0340] In some embodiments, mask data preparation 1732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, and other process effects. Optical proximity correction adjusts the design layout 1722. In some embodiments, mask data preparation 1732 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, treating optical proximity correction as an inverse imaging problem.

[0341] In some embodiments, mask data preparation 1732 includes a mask rule checker (MRC) that checks a design layout 1722 that has been subjected to an optical proximity correction process using a set of mask formation rules that include geometric and / or connectivity constraints to ensure sufficient margins to account for factors such as variability in semiconductor manufacturing processes. In some embodiments, the mask rule checker modifies the representation of the design layout 1722 to compensate for the constraints imposed during mask creation 1744, which may undo some of the modifications performed by the optical proximity correction process to satisfy the mask formation rules.

[0342] In some embodiments, mask data preparation 1732 includes lithography process checking (LPC), which simulates the processing to be performed by integrated circuit fabrication 1750 to fabricate integrated circuit 1760. The lithography process checking simulates this processing based on design layout 1722 to form a simulated fabricated integrated circuit, such as integrated circuit 1760. The lithography process checking simulation considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), and other appropriate factors. In some embodiments, after the lithography process checking simulation, if the simulated device shape does not meet the design rules, optical proximity correction and / or mask rule checker are repeatedly executed to further refine the design layout 1722.

[0343] After mask data preparation 1732 and during mask fabrication 1744, one or a set of photomasks 1745 are fabricated based on design layout 1722. In some embodiments, mask fabrication 1744 includes performing one or more photolithography exposure processes based on design layout 1722. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to form a pattern on photomask 1745 based on design layout 1722. Photomask 1745 can be fabricated using various techniques. In some embodiments, photomask 1745 is fabricated using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose a layer of radiation-sensitive material (e.g., photoresist) already coated on a wafer is transmitted through the transparent regions and blocked by the opaque regions. In one example, a binary mask version of photomask 1745 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, the light mask 1745 is manufactured using a phase shift technique. In a phase shift mask (PSM) version, various features in the pattern are set to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift light mask can be an attenuated phase shift mask or an alternating phase shift mask. The light mask (or a set of light masks) generated by mask manufacturing 1744 is used in various processes. For example, such masks (or masks) are used in ion implantation processes to form various doped regions in the semiconductor wafer 1753, in etching processes to form various etched regions in the semiconductor wafer 1753, and / or in other appropriate processes.

[0344] Integrated circuit fabrication site 1750 may include wafers 1752. Integrated circuit fabrication site 1750 is an integrated circuit manufacturing business that includes fabrication facilities used to manufacture a variety of different integrated circuit products. In some embodiments, integrated circuit fabrication site 1750 is a semiconductor wafer fab. For example, there may be one fabrication facility that provides front-end fabrication for multiple integrated circuit products (front-end fabrication), a second fabrication facility that provides back-end fabrication for interconnection and packaging of the integrated circuit products (back-end fabrication), and a third fabrication facility that provides other services for the wafer fab business.

[0345] Integrated circuit fabrication 1750 uses a photomask 1745 produced by mask factory 1730 to fabricate integrated circuit 1760. Thus, integrated circuit fabrication 1750 at least indirectly uses design layout 1722 (e.g., the layout of memory system 100 discussed above) to fabricate integrated circuit 1760. In some embodiments, wafer 1753 is processed by integrated circuit fabrication 1750 through photomask 1745 to form integrated circuit 1760. In some embodiments, device fabrication includes one or more photolithographic exposures performed at least indirectly based on design layout 1722.

[0346] Therefore, based on the above discussion, it can be seen that the present disclosure provides advantages. However, it is understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed in all embodiments, nor are specific advantages necessarily provided for all embodiments. In various embodiments, the present disclosure provides flexibility in the location of gate contacts within memory bit cells and some peripheral components. For example, in an n-type metal oxide semiconductor (NMOS) memory cell, the gate contact can be located within the active area when viewed from above. Furthermore, the present disclosure can enable the implementation of 3D stacking of InGaZnO thin-film transistor (TFT) components. This configuration can provide increased threshold voltage shift, thereby increasing battery current or reducing battery leakage. Furthermore, for peripheral sense amplifiers (e.g., including PMOS transistors), the gate contact can be located within the active area when viewed from above. This configuration can provide reduced threshold voltage shift, thereby expanding the read window and improving the performance of the sense amplifier. Furthermore, for power connectors (e.g., including PMOS / NMOS transistors), the gate contact can be located outside the active area when viewed from above. This configuration can provide threshold voltage stability, thereby contributing to efficient power utilization within the memory system.

[0347] In some embodiments, a method for fabricating a semiconductor structure includes forming a first gate structure across a first active region, the first active region being located on a substrate within a memory region, wherein the first gate structure belongs to a first transistor, the first transistor being of a first conductivity type; forming a second gate structure across a second active region, the second active region being located on the substrate within a peripheral region, wherein the second gate structure belongs to a second transistor, the second transistor being of a second conductivity type opposite to the first conductivity type; forming a first gate contact over the first gate structure, the first gate contact overlapping the first active region; and forming a second gate contact over the second gate structure, the second gate contact not overlapping the second active region. In some embodiments, the first transistor is an n-type metal oxide semiconductor transistor.

[0348] In some embodiments, the first gate contact is laterally spaced at least approximately 10 nanometers from an edge of the first active region, as viewed from above. In some embodiments, the method further includes forming a third gate structure spanning the first active region within the memory region, wherein the third gate structure is a third transistor, the third transistor and the first transistor forming an antifuse memory cell, the third gate structure being electrically connected to a read word line, and the first gate structure being electrically connected to a program word line; and forming a third gate contact above the third gate structure, the third gate contact not overlapping the first active region. In some embodiments, the first transistor is a thin-film transistor comprising a gate layer, a high-k dielectric layer above the gate layer, an indium gallium zinc oxide layer above the high-k dielectric layer, and a plurality of titanium nitride layers on opposite sides of the indium gallium zinc oxide layer. In some embodiments, the second transistor is a p-type metal oxide semiconductor transistor. In some embodiments, the second gate contact is laterally spaced at least approximately 15 nanometers from an edge of the second active region, as viewed from above. In some embodiments, the memory region is located higher than the surrounding region. In some embodiments, the method further includes forming a third gate structure across a third active region, the third active region being located in a peripheral region of the substrate, wherein the third gate structure comprises a third transistor of the second conductivity type; and forming a third gate contact over the third gate structure, wherein the third gate contact does not overlap the first active region. In some embodiments, the first transistor is a thin film transistor comprising a gate layer, a high-k dielectric layer over the gate layer, an indium gallium zinc oxide layer over the high-k dielectric layer, and a plurality of titanium nitride layers overlying the indium gallium zinc oxide layer.

[0349] In some embodiments, a method for fabricating a semiconductor structure includes forming a plurality of fin structures extending upward from a semiconductor substrate within a memory bit cell; forming a first gate stripe structure extending across the plurality of fin structures and a second gate stripe structure extending across the plurality of fin structures; growing a plurality of source / drain structures on the plurality of fin structures; forming a first gate contact above the first gate stripe structure, wherein the first gate contact is located within a region defined, when viewed from above, by a first outer edge of a first outermost one of the plurality of fin structures and a second outer edge of a second outermost one of the plurality of fin structures, the second outermost one being located on an opposite side of the first outermost one; and forming a second gate contact above the second gate stripe structure, wherein the second gate contact is located outside the region defined, when viewed from above, by the first and second outer edges of the first and second outermost ones of the plurality of fin structures. In some embodiments, the first gate stripe structure is electrically connected to a read word line via the first gate contact, and the second gate stripe structure is electrically connected to a program word line via the second gate contact. In some embodiments, the first gate strip structure is a first n-type metal oxide semiconductor (NMOS) device, and the second gate strip structure is a second NMOS device. In some embodiments, a non-zero distance exists between the second gate contact and the region when viewed from above. In some embodiments, the method further includes: forming a third gate strip structure extending across the plurality of fin structures and positioned between the first gate strip structure and the second gate strip structure; forming a third gate contact over the third gate strip structure, wherein, when viewed from above, the second gate contact is positioned outside the region defined by the first outermost edge and the second outermost edge of the first outermost edge of the second outermost edge of the plurality of fin structures. In some embodiments, the method further includes: forming a third gate strip structure extending across the plurality of fin structures, wherein the second gate strip structure is positioned between the first gate strip structure and the third gate strip structure; forming a third gate contact over the third gate strip structure, wherein, when viewed from above, the second gate contact is positioned within the region defined by the first outermost edge and the second outermost edge of the first outermost edge of the second outermost edge of the plurality of fin structures.

[0350] In some embodiments, a semiconductor structure includes a substrate, a first transistor, a second transistor, and a first gate contact. The first transistor is located above the substrate and is a sense amplifier or power supply terminal of a memory device. The first transistor includes a channel region, a gate structure surrounding the channel region, and a plurality of source / drain regions located on opposite sides of the gate structure. The second transistor is located above the first transistor and is a memory cell. The second transistor includes a gate electrode, a gate dielectric layer located above the gate electrode, an indium gallium zinc oxide layer located above the gate dielectric layer, a first titanium nitride source / drain electrode formed on a first side of the indium gallium zinc oxide layer, and a second titanium nitride source / drain electrode formed on a second side of the indium gallium zinc oxide layer. The first gate contact is located above the gate electrode. From a top view, the indium gallium zinc oxide layer surrounds the first gate contact. In some embodiments, the first transistor is a sense amplifier, and the semiconductor structure further includes a second gate contact. The second gate contact is located above the gate structure of the first transistor and overlaps the channel region of the first transistor. In some embodiments, the first transistor is a power supply terminal, and the semiconductor structure further includes a second gate contact. The second gate contact is located above the gate structure of the first transistor and does not overlap the channel region of the first transistor. In some embodiments, the first transistor is a p-type metal oxide semiconductor device.

[0351] In some embodiments, a semiconductor structure includes a substrate, a first active region, a second active region, a first gate structure, a second gate structure, a first gate contact, and a second gate contact. The first active region is located within a memory region of the substrate. The second active region is located within a peripheral region of the substrate. The first gate structure spans the first active region, wherein the first gate structure belongs to a first transistor, which is of a first conductivity type. The second gate structure spans the second active region, wherein the second gate structure belongs to a second transistor, which is of a second conductivity type opposite to the first conductivity type. The first gate contact is located above the first gate structure, wherein the first gate contact overlaps the first active region. The second gate contact is located above the second gate structure, wherein the second gate contact does not overlap the second active region. In some embodiments, the semiconductor structure further includes a third gate structure, a read word line, a programming word line, and a third gate contact. The third gate structure spans the first active region within the memory region, wherein the third gate structure belongs to a third transistor, and the third transistor and the first transistor form an anti-fuse memory cell. The read word line is electrically connected to the third gate structure. The programming word line is electrically connected to the first gate structure. A third gate contact is located above the third gate structure, wherein the third gate contact does not overlap the first active region. In some embodiments, the semiconductor structure further includes a third active region, a third gate structure, and a third gate contact. The third active region is located within a peripheral region of the substrate. The third gate structure spans the third active region, wherein the third gate structure belongs to a third transistor, and the third transistor is of the second conductivity type. A third gate contact is located on the third gate structure, wherein the third gate contact overlaps the third active region.

[0352] In some embodiments, a semiconductor structure includes a semiconductor substrate, a plurality of fin structures, a first gate strip structure, a second gate strip structure, a plurality of source / drain structures, a first gate contact, and a second gate contact. The plurality of fin structures extend upward from the semiconductor substrate within a memory bit cell. The first gate strip structure extends across the plurality of fin structures. The second gate strip structure extends across the plurality of fin structures. The plurality of source / drain structures are located on the plurality of fin structures. The first gate contact is located above the first gate strip structure, wherein, from a top view, the first gate contact is located within a region defined by a first outer edge of a first outermost one of the plurality of fin structures and a second outer edge of a second outermost one of the plurality of fin structures, the second outermost one being located on an opposite side of the first outermost one. The second gate contact is located above the second gate strip structure, wherein, from a top view, the second gate contact is located outside the region defined by the first and second outer edges of the first and second outermost ones of the plurality of fin structures. In some embodiments, the semiconductor structure further includes a third gate strip structure and a third gate contact. The third gate strip structure extends across multiple fin structures and is located between the first gate strip structure and the second gate strip structure. The third gate contact is located above the third gate strip structure, wherein from the top view, the third gate contact is located outside the aforementioned area, and the aforementioned area is defined by the first outermost edge and the second outermost edge of the first outermost of the multiple fin structures. In some embodiments, the semiconductor structure further includes a third gate strip structure and a third gate contact. The third gate strip structure extends across multiple fin structures, wherein the second gate strip structure is located between the first gate strip structure and the third gate strip structure. The third gate contact is located above the third gate strip structure, wherein from the top view, the third gate contact is located within the aforementioned area, and the aforementioned area is defined by the first outermost edge and the second outermost edge of the first outermost of the multiple fin structures.

[0353] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and replacements may be made herein for such equivalent constructions without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: a substrate; a first transistor disposed over the substrate, the first transistor being a sense amplifier or a power connector of a memory device, the first transistor comprising a channel region, a gate structure surrounding the channel region, and a plurality of source / drain regions located on opposite sides of the gate structure; a second transistor located above the first transistor, the second transistor belonging to a memory cell and comprising: a gate electrode; a gate dielectric layer located above the gate electrode; an indium gallium zinc oxide layer located above the gate dielectric layer; a first titanium nitride source / drain electrode formed on a first side of the indium gallium zinc oxide layer; and a second titanium nitride source / drain electrode formed on a second side of the indium gallium zinc oxide layer; and A first gate contact is located above the gate electrode, wherein the indium gallium zinc oxide layer surrounds the first gate contact when viewed from a top view.

2. The semiconductor structure according to claim 1, wherein The first transistor is a sensing amplifier, and the semiconductor structure further includes: A second gate contact is located above the gate structure of the first transistor, and the second gate contact overlaps the channel region of the first transistor.

3. The semiconductor structure according to claim 1, wherein: The first transistor is a power supply terminal, and the semiconductor structure further includes: A second gate contact is located above the gate structure of the first transistor, and the second gate contact does not overlap the channel region of the first transistor.

4. The semiconductor structure according to claim 1, wherein: The first transistor is a p-type metal oxide semiconductor element.

5. A semiconductor structure, characterized in that include: a substrate; a first active region located in a memory region of a substrate; a second active region located in a peripheral region of the substrate; a first gate structure spanning the first active region, wherein the first gate structure belongs to a first transistor, and the first transistor is of a first conductivity type; a second gate structure spanning the second active region, wherein the second gate structure belongs to a second transistor, and the second transistor is of a second conductivity type opposite to the first conductivity type; a first gate contact located above the first gate structure, wherein the first gate contact overlaps the first active region; and A second gate contact is located above the second gate structure, wherein the second gate contact does not overlap the second active region.

6. The semiconductor structure according to claim 5, wherein: Further including: a third gate structure spanning the first active region in the memory region, wherein the third gate structure belongs to a third transistor, and the third transistor and the first transistor form an anti-fuse memory cell; a read word line electrically connected to the third gate structure; a programming word line electrically connected to the first gate structure; and A third gate contact is located above the third gate structure, wherein the third gate contact does not overlap the first active region.

7. The semiconductor structure according to claim 5, wherein: Further including: a third active region located in the peripheral area of ​​the substrate; a third gate structure spanning the third active region, wherein the third gate structure belongs to a third transistor, and the third transistor is of the second conductivity type; and A third gate contact is located on the third gate structure, wherein the third gate contact overlaps the third active region.

8. A semiconductor structure, characterized in that include: a semiconductor substrate; a plurality of fin structures extending upward from the semiconductor substrate within a memory bit cell; a first gate strip structure extending across the plurality of fin structures; a second gate strip structure extending across the plurality of fin structures; a plurality of source / drain structures located on the plurality of fin structures; a first gate contact located above the first gate strip structure, wherein, from a top view, the first gate contact is located within a region defined by a first outer edge of a first outermost one of the plurality of fin structures and a second outer edge of a second outermost one of the plurality of fin structures, the second outermost one being located on an opposite side of the first outermost one; and A second gate contact is located above the second gate strip structure, wherein from the top view, the second gate contact is located outside the area defined by the first outermost, the first outer edge, and the second outer edge of the second outermost of the multiple fin structures.

9. The semiconductor structure according to claim 8, wherein: Further including: a third gate strip structure extending across the plurality of fin structures and located between the first gate strip structure and the second gate strip structure; and A third gate contact is located above the third gate strip structure, wherein from the top view, the third gate contact is located outside the area defined by the first outermost, the first outer edge, and the second outer edge of the second outermost of the multiple fin structures.

10. The semiconductor structure according to claim 8, wherein Further including: a third gate strip structure extending across the plurality of fin structures, wherein the second gate strip structure is located between the first gate strip structure and the third gate strip structure; and A third gate contact is located above the third gate strip structure, wherein from the top view, the third gate contact is located in the area defined by the first outermost, the first outer edge, and the second outer edge of the second outermost of the multiple fin structures.

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