Low-power-consumption bleeder circuit, switching power supply circuit and chip

Abstract

The utility model relates to a low power consumption bleeder circuit, switch power supply circuit and chip, low power consumption bleeder circuit includes peak detection circuit, bleeder current source and fourth capacitor, wherein peak detection circuit includes: diode and third capacitor, the cathode of diode is connected with the anode of input voltage, and the cathode of diode is connected with the anode of input voltage. The anode of the diode is connected with the first end of the third capacitor to form a sampling end of peak voltage Vhold, and the second end of the third capacitor is connected with the common ground; the input end of the bleeder current source is connected between the input voltage VIN and the peak voltage Vhold, the output end of the bleeder current source is connected with the fourth capacitor in parallel, and the bleeder current source does not generate current when the input voltage VIN is in the rising stage and can provide arcsine current for the fourth capacitor to discharge the voltage in the fourth capacitor when the input voltage VIN is in the falling stage. Therefore, the parasitic capacitance of the circuit can be fully discharged under the condition of low power consumption.

Description

Technical Field

[0001] The utility model relates to the technical field of chips, and in particular to a low-power dissipation circuit, a switching power supply circuit and a chip. Background Art

[0002] In modern power electronics and circuit design, the input voltage is typically an AC sinusoidal wave, such as the mains. Accurate sampling of the input voltage is crucial for circuit judgment and calculation during circuit operation. However, in practical applications, parasitic capacitance often exists at the power input. This parasitic capacitance can originate from wiring, component layout, or design flaws in the circuit board. When parasitic capacitance is present, the input sinusoidal waveform becomes distorted, leading to errors in the sampled voltage. This sine wave distortion not only affects the voltage sampling accuracy but can also affect the proper judgment and operation of the entire circuit, resulting in reduced circuit performance or even failure.

[0003] The usual solution is to connect a bleeder resistor in parallel across the two ends of the parasitic capacitor to release the voltage on the capacitor through the bleeder resistor. Although this bleeder circuit can solve the problem to a certain extent, it has two major disadvantages. First, if a larger resistor is used, the bleeder current is small, and the voltage on the capacitor cannot be fully discharged, which will still cause interference to the circuit; second, if a smaller resistor is used, although the voltage can be discharged quickly, the excessive bleeder current will lead to increased power consumption and serious heating of the circuit components. More importantly, the bleeder current of the bleeder resistor will continue to exist throughout the entire voltage cycle, which not only consumes a lot of power, but also affects the energy efficiency and reliability of the system. Therefore, how to effectively suppress the voltage distortion caused by parasitic capacitance without significantly increasing power consumption is an important challenge in the current technical field. Utility Model Content

[0004] In response to the above problems, the present invention provides a low-power discharge circuit used to discharge parasitic capacitance in a main circuit, including: a discharge current source I1 and a first capacitor C1 connected in parallel therewith, the first capacitor C1 being connected in parallel to the input voltage ends of the main circuit, the discharge current source I1 being an inverse sine current source whose current waveform follows the law of the inverse sine function.

[0005] Optionally, the bleeder current source I1 includes: a first resistor R1, a first MOS transistor NM1, a second MOS transistor NM2, a third MOS transistor NM3, and a first current source I2; a first end of the first resistor R1 is configured to be connected to an input voltage VIN, a second end of the first resistor R1 is connected to a drain of the first MOS transistor NM1, a gate of the first MOS transistor NM1 is connected to a gate of the second MOS transistor NM2, a drain of the second MOS transistor NM2 is connected to the first current source I2, drains of the third MOS transistor NM3 and the second MOS transistor NM2 are connected to the gate of the third MOS transistor NM3, sources of the first MOS transistor NM1, the second MOS transistor NM2, and the third MOS transistor NM3 are connected to a common ground, and the drain and source of the third MOS transistor NM3 form an output end of the bleeder current source and are connected in parallel to both ends of the first capacitor C1.

[0006] In order to solve the above technical problems, the utility model provides a low-power discharging circuit, which is used to discharge the parasitic capacitance in the main circuit, including a peak detection circuit 01, a comparison circuit 02, a switch circuit 03, a discharging current source I1 and a second capacitor C2, wherein the peak detection circuit 01 is connected to the input voltage VIN, and is used to sample the electrical signal representing the input voltage, and determine the peak value Vholdmax of the input voltage based on the electrical signal; the two input ends of the comparison circuit 02 are respectively connected to the peak detection circuit 01 and the main circuit to respectively access the peak voltage Vhold and the input The output end of the comparison circuit 02 is connected to the control end of the switch circuit 03, and can determine whether the input voltage VIN is in the rising stage / falling stage based on the comparison result of the input voltage VIN and Vhold, and then control the switch circuit 03 to be closed when the input voltage VIN is in the rising process, and to be closed when the input voltage VIN is in the falling process; the series body formed by the switch circuit 03 and the discharge current source I1 in series is connected in parallel to the two ends of the second capacitor C2, which can discharge the voltage on the second capacitor C2 through the arcsine current generated by the discharge current source I1.

[0007] Optionally, the peak detection circuit 01 includes: a diode VG1 and a third capacitor C3, the anode of the diode VG1 is connected to the positive electrode of the input voltage VIN, the cathode of the diode VG1 is connected to the first end of the third capacitor C3, forming a sampling end of the peak voltage Vhold, and the second end of the third capacitor C3 is connected to the common ground.

[0008] In order to solve the above technical problems, the present invention provides a low-power dissipation circuit for discharging parasitic capacitance in a main circuit, including a peak detection circuit 01, a discharging current source and a fourth capacitor C4, wherein the peak detection circuit 01 includes: a diode VG1 and a third capacitor C3, the anode of the diode VG1 is connected to the positive electrode of the input voltage VIN, the cathode of the diode VG1 is connected to the first end of the third capacitor C3, forming a sampling end of the peak voltage Vhold, and the second end of the third capacitor C3 is connected to a common ground; the input end of the discharging current source is connected between the input voltage VIN and the peak voltage Vhold, and the output end thereof is connected in parallel with the fourth capacitor C4. The discharging current source does not generate current when the input voltage VIN is in a rising stage, and can provide an inverse sine current to the fourth capacitor C4 when the input voltage VIN is in a falling stage to discharge the voltage in the fourth capacitor C4.

[0009] Optionally, the bleeder current source includes a differential pair consisting of a fourth MOS transistor NM4, a fifth MOS transistor NM5, a second current source I3, and a third current source I4; a second resistor R2 connected between the sources of the fourth MOS transistor NM4 and the fifth MOS transistor NM5; and a current sampling circuit O4 having an input end connected in parallel to both ends of the second resistor R2 and an output end connected in parallel to both ends of the fourth capacitor C4; no current flows through the second resistor R2 when the input voltage VIN is in a rising phase, and an arcsine current is generated when the input voltage VIN is in a falling phase. The current sampling circuit O4 can sample the current of the second resistor R2 and output it to both ends of the fourth capacitor C4.

[0010] Optionally, the current sampling circuit 04 includes: a first current mirror 05, a second current mirror 06 and an arcsine current output circuit 07, the first current mirror 05 can obtain the current I11 at the first end of the second resistor R2, the second current mirror 06 can obtain the current I12 at the second end of the second resistor R2, the arcsine current output circuit 07 is connected to the output ends of the first current mirror 05 and the second current mirror 06, and can output the difference between the currents I12 and I11 to the two ends of the fourth capacitor C4.

[0011] In order to solve the above technical problems, the utility model provides a switching power supply circuit, which applies the low-power dissipation circuit described above.

[0012] In order to solve the above technical problems, the present invention provides a chip integrating the low-power dissipation circuit described above.

[0013] In order to solve the above technical problems, the present invention provides a chip integrating the switching power supply circuit described above.

[0014] In summary, the low-power discharge circuit provided by the present invention can discharge the parasitic capacitance with low power consumption by introducing the inverse sine current source. Furthermore, by the coordinated design of the peak detection circuit and the inverse sine current source, the inverse sine current source provides the circuit with an inverse sine current only when the input voltage drops, thereby further reducing the power consumption of the discharge circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is the sampling voltage distortion caused by parasitic capacitance in existing electronic circuits.

[0016] Figure 2 Schematic diagram of the circuit structure of the low-power dissipation circuit provided in the embodiment of the present utility model.

[0017] Figure 3 yes Figure 2 A circuit structure diagram of a discharge current source in a low-power discharge circuit is provided in FIG.

[0018] Figure 4 A schematic diagram of current waveforms of arcsine current and sinusoidal current is shown.

[0019] Figure 5 A schematic diagram of the power waveforms of inverse sine current and sine current under the same conditions is shown.

[0020] Figure 6 A schematic diagram of the circuit structure of a low-power dissipation circuit provided by an embodiment of the present utility model is shown.

[0021] Figure 7 Shown Figure 6 Schematic diagram of the circuit structure of the peak detection circuit in the low and medium power dissipation circuit.

[0022] Figure 8 The figure shows a circuit structure diagram of a low-power dissipation circuit provided by an embodiment of the present utility model.

[0023] Figure 9 Shown Figure 8 Schematic diagram of the circuit structure of the current sampling circuit in the low- and medium-power bleeder circuit. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0025] In many power electronics applications, large-capacity capacitors are used for filtering or energy storage. When the system is turned off or the power is disconnected, these capacitors may still store a large amount of charge, which may cause the following problems if not released quickly: Safety hazards: Charged capacitors may cause electric shock hazards during maintenance or debugging. System response delay: When the system restarts, the residual charge in the capacitor may interfere with the new operation and affect the stability or response speed of the system. Component damage: In some cases, capacitors that are not discharged in time may cause reverse current or voltage shock to components in the circuit (such as MOSFET, IGBT, etc.), causing damage. Inaccurate sampling voltage: Usually, the input voltage used by the circuit is a sine wave. When the input voltage needs to be sampled, if there is parasitic capacitance on the power supply voltage, it will cause the sine wave to be deformed, such as Figure 1 As shown, the sampling voltage is inaccurate, which in turn affects the judgment and calculation of the circuit.

[0026] In order to solve the above technical problems, Figure 2 As shown, this embodiment provides a low-power discharge circuit for discharging parasitic capacitance in a main circuit, including: a discharge current source I1 and a first capacitor C1 connected in parallel with the discharge current source I1, the first capacitor C1 being connected in parallel to the input voltage of the main circuit, wherein the discharge current source I1 is an inverse sine current source.

[0027] The main circuit mentioned in this embodiment may be a switching power supply circuit, or other electronic circuits that are prone to generating parasitic capacitance due to a large number of switches or other reasons.

[0028] Specifically, the inverse sine current source is a current source that generates a current waveform that follows the law of the inverse sine function. Assuming that an input signal changes with time, the inverse sine current source will transform the input signal through the inverse sine function and convert it into a current output. Its specific implementation method can be realized by digital circuits, analog circuits or analog-digital hybrid circuits. As an example, Figure 3The embodiment shows an implementation of a bleeder current source, which includes: a first resistor R1, a first MOS transistor NM1, a second MOS transistor NM2, a third MOS transistor NM3 and a first current source I2. The first end of the first resistor R1 is configured to be connected to the input voltage VIN, the second end of the first resistor R1 is connected to the drain of the first MOS transistor NM1, the gate of the first MOS transistor NM1 is connected to the gate of the second MOS transistor NM2, the drain of the second MOS transistor NM2 is connected to the first current source I2, and the third MOS transistor NM3 and the second MOS transistor NM2 are connected to the first current source I2. The drain of the transistor NM2 is connected to the gate of the third MOS transistor NM3. The sources of the first to third MOS transistors are connected to a common ground. The drain and source of the third MOS transistor NM3 form the output end of the discharge current source I1, which is connected in parallel to the two ends of the first capacitor C1. The current I=VIN / R in the first MOS transistor NM1 is equal to the current in the second MOS transistor NM2. Then, the current I3 in the third MOS transistor NM3 is I2-I=I2-VIN / R, where I2 and the first resistor R1 are adjustable. At this time, the current in the drain of the third MOS transistor NM3 is an inverse sine current.

[0029] like Figure 4 and Figure 5 As shown, the waveforms of the inverse sine current and the sinusoidal current and the corresponding power waveforms are shown respectively. The power calculation formulas of the inverse sine current and the sinusoidal current under the same conditions are as follows. Assuming that the input voltage expression is U = αsinx, the current generated by the parallel resistor is I = αsinx / R, and the power P = α2sin2x / R. Under the same conditions, the inverse sine current formula is I = α / R-αsinx / R, and the power P = αsinx / R-α2sin2x / R, where x represents time and R represents the resistance value of the resistor connected in parallel to the capacitor.

[0030] based on Figure 5 From the above calculations, it can be seen that the power of the arcsine current is less than the power generated by the sinusoidal current. Therefore, the low-power discharge circuit provided in this embodiment can solve the problem in the prior art that the discharge circuit composed of a resistor and a capacitor in parallel has excessive power consumption or cannot completely discharge the parasitic capacitance.

[0031] In order to further reduce the power consumption of the discharge circuit, this embodiment also provides a low-power discharge circuit, such as Figure 6As shown, a peak detection circuit 01, a comparison circuit 02, a switch circuit 03, a discharge current source I1 and a second capacitor C2 are connected, wherein the peak detection circuit 01 is connected to the input voltage, and is used to sample an electrical signal representing the input voltage, and determine the peak value Vhold of the input voltage VIN based on the electrical signal; the two input ends of the comparison circuit 02 are respectively connected to the peak detection circuit 01 and the main circuit to respectively receive the peak voltage Vhold and the input voltage VIN; the output end of the comparison circuit 02 is connected to the control end of the switch circuit 03, and can determine whether the input voltage VIN is in the rising stage / falling stage based on the magnitude relationship between the input voltage VIN and Vhold, and control the switch circuit 03 to be closed when the input voltage VIN is in the rising process, and to be closed when the input voltage VIN is in the falling process; the series body formed by the switch circuit 03 and the discharge current source I1 in series is connected in parallel to the two ends of the second capacitor C2, which can discharge the voltage on the second capacitor C2 through the arcsine current generated by the discharge current source I1.

[0032] Figure 6 The low power bleeder circuit shown in Figure 7 As shown, voltage discharge is performed only when the input voltage is in the process of decreasing, which further reduces the power consumption of the discharge circuit.

[0033] in, Figure 6 The bleeder current source in the low power bleeder circuit shown in FIG can be obtained by Figure 3 The bleeder current source I1 shown in FIG is implemented to generate an arc-sinusoidal current.

[0034] Among them, such as Figure 7 As shown, the peak detection circuit 01 can be implemented as follows: it includes a diode VG1 and a third capacitor C3. The anode of the diode VG1 is connected to the positive electrode of the input voltage VIN, and the cathode of the diode VG1 is connected to the first end of the third capacitor C3, forming a sampling terminal for the peak voltage Vhold. The second end of the third capacitor C3 is connected to the common ground. The operating principle of this circuit is: when the input voltage VIN is in the rising phase, the diode VG1 is turned on and charges the third capacitor C3, Vhold = VIN - VG1. When VIN decreases, VIN < Vhold + VG1, the diode VG1 is turned off, and Vhold is maintained at the maximum voltage, Vholdmax = VINmax. In this way, the peak voltage Vholdmax can be obtained.

[0035] In order to further simplify the circuit structure, this embodiment also provides a low power dissipation circuit, such as Figure 8 As shown, it includes a peak detection circuit 01, a discharge current source and a fourth capacitor C4, wherein the structure of the peak detection circuit 01 is as shown Figure 7As shown, the peak voltage Vhold can be obtained. The input end of the discharge current source I2 is connected between the input voltage VIN and the peak voltage Vhold, or in other words, is connected in parallel with the diode VG1 in the peak detection circuit 01. The output end of the discharge current source I2 is connected in parallel with the fourth capacitor C4. It does not generate current when the input voltage VIN is in the rising stage, and can provide an arcsine current to the fourth capacitor C4 when the input voltage VIN is in the falling stage to discharge the voltage in the fourth capacitor C4.

[0036] Specifically, the bleeder current source includes a differential pair consisting of a fourth MOS transistor NM4, a fifth MOS transistor NM5, a second current source I3, and a third current source I4; a second resistor R2 connected between the sources of the fourth MOS transistor NM4 and the fifth MOS transistor NM5; and a current sampling circuit O4 having an input terminal connected in parallel with both ends of the second resistor R2 and an output terminal connected in parallel with both ends of the fourth capacitor C4. When the input voltage VIN is in a rising phase, Vhold = VIN - VG1, ignoring the diode voltage drop Vhold ≈ VIN, and no current flows through the second resistor R2. When the input voltage VIN is in a falling phase, Vhold > VIN, and current flows through the second resistor R2, with the current being I = (Vholdmax - VIN) / R2, where Vholdmax is a constant (peak voltage). The resistance of the second resistor R2 is adjustable. At this time, the current in the second resistor R2 is an inverse sine current, which is generated only when the input voltage VIN is falling. The current sampling circuit can sample this inverse sine current and output it to both ends of the fourth capacitor C4 to achieve voltage bleeder.

[0037] In this embodiment, the structure and characteristics of the peak detection circuit 01 are utilized. Figure 6 The low-power discharge circuit shown in FIG does not require a switch circuit and a comparison circuit. In other words, the switch circuit and the comparison circuit reuse some electronic components with the peak detection circuit 01 to achieve voltage discharge, which not only saves the circuit cost but also further reduces the power consumption of the discharge circuit.

[0038] Specifically, the circuit connection relationship of the differential pair is as follows: the gate of the fourth MOS transistor NM4 is connected to the input voltage VIN, the gate of the fifth MOS transistor NM5 is connected to Vhold, the drains of the fourth MOS transistor NM4 and the fifth MOS transistor M5 are connected to the voltage VCC, the source of the fourth MOS transistor M4 is connected to the first end of the second resistor R2 and the first end of the second current source I3, the source of the fifth MOS transistor NM5 is connected to the second end of the second resistor R2 and the first end of the third current source I4, and the second end of the second current source I3 and the second end of the third current source I4 are connected to a common ground.

[0039] The current sampling circuit can be implemented in many ways, as an example, Figure 9As shown, it may include a first current mirror 05, a second current mirror 06 and an arcsine current output circuit 07. The first current mirror 05 can obtain the current I11 at the first end of the second resistor R2, and the second current mirror 06 can obtain the current I12 at the second end of the second resistor R2. The arcsine current output circuit 07 is connected to the output ends of the first current mirror 05 and the second current mirror 06, and can output the difference between the currents I12 and I11 to both ends of the fourth capacitor C4.

[0040] Specifically, the first current mirror 05 includes an eighth MOS transistor NM8 and a ninth MOS transistor NM9, the second current mirror 06 includes a sixth MOS transistor NM6 and a seventh MOS transistor NM7, and the arcsine current output circuit 07 includes a tenth MOS transistor NM10, an eleventh MOS transistor NM11, a twelfth MOS transistor NM12, and a thirteenth MOS transistor NM13. Since the principles and structures of current mirrors and current difference circuits are well known to those skilled in the art, they will not be described in detail in this embodiment.

[0041] Among them, the first to the thirteenth MOS transistors are NMOS transistors.

[0042] Optionally, this embodiment provides a switching power supply circuit (not shown), which includes Figure 2 、 Figure 6 and Figure 8 Any of the low power bleeder circuits shown.

[0043] Optionally, this embodiment provides a chip that integrates Figure 2 、 Figure 6 and Figure 8 Any of the low power bleeder circuits shown.

[0044] Optionally, this embodiment provides a chip that integrates the switching power supply circuit provided in this embodiment.

[0045] Thus far, the technical solution of the present invention has been described in conjunction with the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is clearly not limited to the specific embodiments described above. Without departing from the principles of the present invention, those skilled in the art may make equivalent modifications or substitutions to the relevant technical features, and the technical solutions after such modifications or substitutions will fall within the scope of protection of the present invention.

Claims

1. A low-power dissipation circuit, used for dissipating parasitic capacitance in a main circuit, characterized in that: include: A discharge current source I1 and a first capacitor C1 connected in parallel therewith, wherein the first capacitor C1 is connected in parallel to the input voltage of the main circuit, and the discharge current source I1 is an inverse sine current source generating a current waveform following an inverse sine function.

2. The low-power dissipation circuit according to claim 1, characterized in that: The bleeder current source I1 includes: a first resistor R1, a first MOS transistor NM1, a second MOS transistor NM2, a third MOS transistor NM3, and a first current source I2. The first end of the first resistor R1 is configured to be connected to the input voltage VIN, the second end of the first resistor R1 is connected to the drain of the first MOS transistor NM1, the gate of the first MOS transistor NM1 is connected to the gate of the second MOS transistor NM2, the drain of the second MOS transistor NM2 is connected to the first current source I2, the drains of the third MOS transistor NM3 and the second MOS transistor NM2 are connected to the gate of the third MOS transistor NM3, the sources of the first MOS transistor NM1, the second MOS transistor NM2, and the third MOS transistor NM3 are connected to a common ground, and the drain and source of the third MOS transistor NM3 form the output end of the bleeder current source and are connected in parallel to the two ends of the first capacitor C1.

3. A low-power dissipation circuit, used to discharge parasitic capacitance in a main circuit, characterized in that: The system comprises a peak detection circuit 01, a comparison circuit 02, a switch circuit 03, a discharge current source I1 and a second capacitor C2, wherein the peak detection circuit 01 is connected to the input voltage VIN, and is used to sample an electrical signal representing the input voltage, and determine the peak value Vholdmax of the input voltage based on the electrical signal; the two input ends of the comparison circuit 02 are respectively connected to the peak detection circuit 01 and the main circuit to respectively receive the peak voltage Vhold and the input voltage VIN; the output end of the comparison circuit 02 is connected to the control end of the switch circuit 03, and can determine whether the input voltage VIN is in the rising stage / falling stage based on the comparison result of the input voltage VIN and Vhold, and then control the switch circuit 03 to be closed when the input voltage VIN is in the rising process and closed when the input voltage VIN is in the falling process; the series body formed by the switch circuit 03 and the discharge current source I1 in series is connected in parallel to the two ends of the second capacitor C2, which can discharge the voltage on the second capacitor C2 through the inverse sine current generated by the discharge current source I1.

4. The low-power dissipation circuit according to claim 3, characterized in that: The peak detection circuit 01 includes: a diode VG1 and a third capacitor C3, the anode of the diode VG1 is connected to the positive electrode of the input voltage VIN, the cathode of the diode VG1 is connected to the first end of the third capacitor C3, forming a sampling end of the peak voltage Vhold, and the second end of the third capacitor C3 is connected to the common ground.

5. A low power dissipation circuit, characterized in that: The peak detection circuit 01 includes a peak detection circuit 01, a discharge current source and a fourth capacitor C4, wherein the peak detection circuit 01 includes: a diode VG1 and a third capacitor C3, the anode of the diode VG1 is connected to the positive electrode of the input voltage VIN, the cathode of the diode VG1 is connected to the first end of the third capacitor C3, forming a sampling end of the peak voltage Vhold, and the second end of the third capacitor C3 is connected to the common ground; the input end of the discharge current source is connected between the input voltage VIN and the peak voltage Vhold, and the output end thereof is connected in parallel with the fourth capacitor C4. The discharge current source does not generate current when the input voltage VIN is in a rising stage, and can provide an inverse sine current to the fourth capacitor C4 when the input voltage VIN is in a falling stage to discharge the voltage in the fourth capacitor C4.

6. The low-power dissipation circuit according to claim 5, characterized in that: The bleeder current source includes a differential pair consisting of a fourth MOS transistor NM4, a fifth MOS transistor NM5, a second current source I3, and a third current source I4; a second resistor R2 connected between the sources of the fourth MOS transistor NM4 and the fifth MOS transistor NM5; and a current sampling circuit O4 having an input end connected in parallel to both ends of the second resistor R2 and an output end connected in parallel to both ends of the fourth capacitor C4. No current flows through the second resistor R2 when the input voltage VIN is in a rising phase, and an arcsine current is generated when the input voltage VIN is in a falling phase. The current sampling circuit O4 can sample the current of the second resistor R2 and output it to both ends of the fourth capacitor C4.

7. The low-power dissipation circuit according to claim 6, characterized in that: The current sampling circuit 04 includes: a first current mirror 05, a second current mirror 06, and an arcsine current output circuit 07. The first current mirror 05 can obtain the current I11 at the first end of the second resistor R2, and the second current mirror 06 can obtain the current I12 at the second end of the second resistor R2. The arcsine current output circuit 07 is connected to the output ends of the first current mirror 05 and the second current mirror 06, and can output the difference between the currents I12 and I11 to the two ends of the fourth capacitor C4.

8. A switching power supply circuit, characterized in that: A low-power dissipation circuit according to any one of claims 1 to 7 is used.

9. A chip, characterized in that: The low-power dissipation circuit according to any one of claims 1 to 7 is integrated.

10. A chip, characterized in that: The switching power supply circuit according to claim 8 is integrated.

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