Server mainboard

Abstract

According to the server mainboard provided by the embodiment of the invention, a plurality of PCB laminations which are stacked layer by layer transmit different signals, and the signals among the different PCB laminations are interconnected through mechanical blind holes; the plurality of memory particles comprise first memory particles configured on a TOP surface of the PCB mainboard and second memory particles configured on a BOTTOM surface of the PCB mainboard, the first memory particles and the second memory particles are configured on a memory channel of the CPU in a one-to-one correspondence manner, and the plurality of PCB laminations stacked layer by layer comprise first laminations for transmitting signals of the first memory particles. The second lamination is used for transmitting signals of the second memory particles, the third lamination is used for bearing a power supply, and the first lamination and the second lamination have structural symmetry based on the third lamination. The memory chips are arranged on the main board in an oppositely-attached mode, the layout space is saved, the first lamination layer and the second lamination layer of the main board are symmetrical based on the third lamination layer structure, the warping degree of the main board is reduced, different lamination layers are interconnected through mechanical blind holes, blind holes do not need to be configured through precise equipment, and the cost is saved.

Description

Technical Field

[0001] The present application relates to the field of PCB motherboards, and in particular to a server motherboard. Background Art

[0002] As an important part of computer components, memory plays an increasingly important role in improving computer performance.

[0003] With the growing demand for data transmission, the multi-channel memory architecture on the printed circuit board (PCB) motherboard can provide more parallel data transmission paths. Each channel can transmit data simultaneously, thereby improving memory bandwidth and system performance. In other words, more channels can be set on a single side of the central processing unit (CPU) memory group. Correspondingly, more channels can be configured with more memory chips.

[0004] The current layout of single-sided memory chips on the PCB motherboard is limited by the board area and has insufficient layout space. Utility Model Content

[0005] The main purpose of the embodiments of the present application is to provide a server motherboard for increasing the layout space of single-sided memory chips.

[0006] To achieve the above objectives, a first aspect of an embodiment of the present application provides a server motherboard, characterized in that: it includes a multi-layer printed circuit board (PCB), a central processing unit (CPU), multiple memory chips, and a power supply. The multi-layer PCB includes multiple PCB layers stacked one on top of the other, each PCB layer transmitting a different signal, and the signals between different PCB layers are interconnected via mechanical blind vias.

[0007] The multiple memory particles include a first memory particle configured on the top TOP surface of the PCB mainboard and a second memory particle configured on the bottom BOTTOM surface of the PCB mainboard. The first memory particle and the second memory particle include multiple memory particles. The first memory particle and the second memory particle are configured on the memory channel of the CPU in a one-to-one manner. The multiple layered PCB stacks include a first stack for transmitting the signal of the first memory particle, a second stack for transmitting the signal of the second memory particle, and a third stack for carrying the power supply. The first stack and the second stack have structural symmetry based on the third stack.

[0008] Optionally, the CPU has 4-channel memory on one side, with 2 channels of first memory particles configured on the TOP surface, and 2 channels of second memory particles configured on the BOTTOM surface in positions symmetrical to the first memory particles.

[0009] Optionally, the number of PCB stacks is 24, the first stack includes 5 first ground layers, 4 first wiring layers and a TOP surface layer, the first ground layer and the first wiring layer are stacked alternately, the second stack includes 5 second ground layers, 4 second wiring layers and a BOTTOM surface layer, the second ground layer and the second wiring layer are stacked alternately, the third stack includes 4 power supply layers, the first wiring layer is used to transmit the signal of the first memory particle, and the second wiring layer is used to transmit the signal of the second memory particle.

[0010] Optionally, the first ground layer, the second ground layer, and the power layer are routed using through holes.

[0011] Optionally, the power layer has a centrally symmetrical structure.

[0012] Optionally, the power supply layer includes two CPU power supply layers, and the two CPU power supply layers are symmetrical based on the center of the power supply layer.

[0013] Optionally, signals between the CPU and the multi-layer PCB mainboard are transmitted using through-holes.

[0014] Optionally, the through hole includes a first through hole and a second through hole, the CPU is connected to the first wiring layer through the first through hole, and performs signal transmission with the first memory chip through the first wiring layer;

[0015] The CPU is connected to the second wiring layer through the second through hole and performs signal transmission with the second memory particle through the second wiring layer.

[0016] Optionally, the PCB stack is a double-sided PCB board.

[0017] Optionally, the multi-layer PCB main board is generated by stacking and pressing double-sided PCB boards.

[0018] The present application uses a multi-layer PCB motherboard including multiple PCB stacks stacked layer by layer, each PCB stack transmits different signals, and the signals between different PCB stacks are interconnected through mechanical blind vias;

[0019] The multiple memory particles include a first memory particle configured on the top TOP surface of the PCB mainboard and a second memory particle configured on the bottom BOTTOM surface of the PCB mainboard. The first memory particle and the second memory particle include multiple memory particles. The first memory particle and the second memory particle are configured on the memory channel of the CPU in a one-to-one manner. The multiple layered PCB stacks include a first stack for transmitting the signal of the first memory particle, a second stack for transmitting the signal of the second memory particle, and a third stack for carrying the power supply. The first stack and the second stack have structural symmetry based on the third stack.

[0020] The server motherboard has memory chips placed on the motherboard, which can save layout space. The first and second layers of the motherboard are symmetrical based on the third layer structure, which can reduce the warping of the motherboard. Different layers are interconnected through mechanical blind holes, which does not require sophisticated equipment to configure blind holes and saves costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the conventional layout and wiring planning of memory chips provided in an embodiment of the present application;

[0022] Figure 2 This is a schematic diagram of the layout of the PCB motherboard provided in an embodiment of the present application;

[0023] Figure 3 This is a structural diagram of a server motherboard provided in an embodiment of the present application;

[0024] Figure 4 This is a schematic diagram of the 4-channel memory distribution provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] An embodiment of the present application provides a server motherboard for increasing the layout space of memory chips on a single side.

[0026] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0027] It should be noted that although the functional modules are divided in the device schematic, in some cases, the module division may be different from that in the device. The terms "first," "second," etc. in the specification, claims, and drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0028] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0029] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program that has a predetermined function and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories) or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.

[0030] In addition, numerous specific details are provided in the detailed description below to better illustrate the present application. Those skilled in the art will appreciate that the present application can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present application.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0032] With the growing demand for data transmission, the multi-channel memory architecture on the printed circuit board (PCB) motherboard can provide more parallel data transmission paths. Each channel can transmit data simultaneously, thereby improving memory bandwidth and system performance. In other words, more channels can be set on a single side of the central processing unit (CPU) memory group. Correspondingly, more channels can be configured with more memory chips.

[0033] When the CPU memory group is four channels, there are two channels in the same area on one side. The conventional layout and wiring planning diagram of the double data rate (DDR) memory particles in the PCB motherboard is as follows: Figure 1 shown. Figure 1 Each channel uses five x16 DDR memory chips, with a total of 64 bits of DDR data plus 8 bits of error-correcting code (ECC). Each memory chip consists of a data group and an address group. The data group of each memory chip is connected to the CPU's data group via wiring, and the address group of each memory chip is connected to the CPU's address group via wiring. The address group is typically used to transmit memory address information, represented by a dotted line in the figure, while the data group is used to transmit actual data, represented by a solid line. Typically, two wiring layers are required for data signal routing, and two wiring layers are required for address group signals, for a total of two to four wiring layers per channel to implement DDR routing. Dual-channel DDR routing typically requires four to eight wiring layers. When address and data signal routing do not interfere with each other, the minimum number of wiring layers is four. When interference is severe, at least eight wiring layers are required.

[0034] When the number of channels on one side of the CPU memory group is 4, the layout of the PCB motherboard can refer to Figure 2 As shown in the figure, 4 channels of memory particles are arranged on one side of the CPU, and each channel is configured with 5 memory particles. In this case, the memory particles require a large layout space, but due to the area limitation of the PCB motherboard, sufficient space cannot be provided.

[0035] Based on the above problems, an embodiment of the present application provides a server motherboard, and the relevant description of the server motherboard can be referred to as follows.

[0036] See also Figure 3 ,like Figure 3 FIG. 1 is a schematic structural diagram of a server motherboard according to an embodiment of the present application. The server motherboard includes a multi-layer PCB motherboard, a CPU, multiple memory chips, and a power supply. The multi-layer PCB motherboard includes multiple PCB layers stacked one on top of the other. Each PCB layer transmits a different signal, and the signals between different PCB layers are interconnected via mechanical blind vias.

[0037] The multiple memory particles include a first memory particle configured on the top (TOP) surface of the PCB mainboard and a second memory particle configured on the bottom (BOTTOM) surface of the PCB mainboard. The first memory particle and the second memory particle include multiple memory particles. The first memory particle and the second memory particle are configured on the memory channel of the CPU in a one-to-one manner. The multiple layered PCB stacks include a first stack for transmitting signals of the first memory particle, a second stack for transmitting signals of the second memory particle, and a third stack for carrying power. The first stack and the second stack have structural symmetry based on the third stack.

[0038] In this embodiment, the server motherboard is constructed from multiple stacked PCB layers, each responsible for transmitting different signals. Signals between different PCB layers can be interconnected via blind vias. These blind vias do not penetrate the entire PCB, but instead connect signals between layers, thereby achieving electrical connections between different layers. This allows for more wiring layers to be arranged within the limited PCB space, thereby increasing wiring density. The blind vias in this embodiment can be mechanical vias, which are typically formed using a mechanical drilling process and do not require sophisticated equipment or high technical requirements.

[0039] A plurality of memory particles are configured on the PCB motherboard based on the channels of the CPU, including a first memory particle located on the TOP surface of the motherboard and a second memory particle located on the BOTTOM surface. These memory particles are configured on the memory channels of the CPU in a pasting manner, which improves the density and access speed of the memory. Among them, the first memory particle and the second memory particle include a plurality of memory particles, and the pasting manner is that any memory particle on the TOP surface of the first memory particle has a symmetrically distributed memory particle with the second memory particle on the BOTTOM surface. The multiple PCB stacks stacked layer by layer can be based on a centrally symmetrical structure, which can be used to reduce the warping rate of the PCB and help maintain the stability and reliability of the wiring in a tighter space. Among them, the center of the multiple PCB stacks stacked layer by layer can be a third stack that carries the power supply. The first stack and the second stack are symmetrical based on the third stack structure, which can reduce interference between signals. The power supply layer in the center can increase the efficiency of the power distribution and reduce the impedance between the power supply layer and the ground layer, thereby improving the current flow capacity of the copper foil.

[0040] The embodiment of the present application saves layout space by placing memory chips on the motherboard, and the first and second stacks of the motherboard are symmetrical based on the third stack structure, which can reduce the warping of the motherboard. Different stacks are interconnected through mechanical blind holes, and there is no need for sophisticated equipment to configure blind holes, thus saving costs.

[0041] based on Figure 3 In a feasible implementation of the server motherboard shown, one side of the CPU has 4-channel memory, 2 channels of first memory particles are configured on the TOP surface, and 2 channels of second memory particles are configured on the BOTTOM surface in a symmetrical position with the first memory particles.

[0042] In this implementation, when the CPU supports 4-channel memory on one side, based on the memory particle alignment method, 2 channels can be allocated on the TOP surface and 2 channels can be allocated on the BOTTOM surface. The channels on the TOP and BOTTOM surfaces are symmetrically distributed, that is, for any memory particle in the channel on the TOP surface, there is a symmetrically distributed memory particle in the channel on the BOTTOM surface.

[0043] For example, see Figure 4 The diagram below shows a 4-channel memory layout. For example, each channel has 5 memory chips. The channels on the top side can be called channels 1 and 3, and the channels on the bottom side can be called channels 2 and 4. The memory chips on channel 1 align with those on channel 2, and the memory chips on channel 3 align with those on channel 4. The CPU communicates with the memory chips on all four channels.

[0044] based on Figure 3In the server motherboard shown, in a feasible implementation manner, the number of PCB stacks is 24, the first stack includes 5 first ground layers, 4 first wiring layers and a TOP surface layer, the first ground layers and the first wiring layers are stacked alternately, the second stack includes 5 second ground layers, 4 second wiring layers and a BOTTOM surface layer, the second ground layers and the second wiring layers are stacked alternately, the third stack includes 4 power supply layers, the first wiring layer is used to transmit signals of the first memory particles, and the second wiring layer is used to transmit signals of the second memory particles.

[0045] In this embodiment, the first stack may include 5 first ground layers and 4 first wiring layers, as well as a TOP surface layer, and the second stack may include 5 second ground layers and 4 second wiring layers, as well as a BOTTOM surface layer. The spaced stacking design of the ground layers and wiring layers can provide good signal shielding and power distribution, which is crucial for maintaining the integrity of memory signals and reducing interference. The third stack includes 4 power layers, which is very important for providing stable and clean power to the memory particles, because the stable operation of the memory requires a stable power supply. The first wiring layer can connect to the pins of the first memory particle and transmit signals with the first memory particle, and the second wiring layer can connect to the pins of the second memory particle and transmit signals with the second memory particle. The memory signal is transmitted through a dedicated wiring layer, which helps to reduce signal interference and improve the reliability of data transmission.

[0046] For example, an example of a 24-layer PCB motherboard can be shown in Table 1, which includes 24 layers from L1 to L24. Layer L1 is the top surface of the device. The copper thickness of the top surface of the device can be 2mil, which can be used for the fan-out of the device. Layers L2 to L10 are the distribution of the ground layer and the wiring layer in sequence. The copper thickness can be 0.6mil. Among them, L3 and L5 can transmit the data and address signals of memory chip 1, and L7 and L9 can transmit the data and address signals of memory chip 2. L11 to L14 are power supply layers. L12 and L13 can carry the CPU core voltage power supply. The copper thickness can be 2mil. L12 can also serve as the ground layer. L11 and L14 can carry other power supplies. The copper thickness can be 1.2mil. L15 to L23 are the distribution of the ground layer and the wiring layer in sequence. The copper thickness can be 0.6mil. Among them, L16 and L18 can transmit the data and address signals of memory chip 3, and L20 and L22 can transmit the data and address signals of memory chip 4. The L24 layer is the bottom surface of the device. The copper thickness laid on the bottom surface of the device can be 2mil, which can be used for the fan-out of the device.

[0047] Table 1

[0048] Cascade Name definition Copper thickness Wiring Instructions L1 Device top surface 2mil Device Fanout L2 Ground Plane-1 0.6mil L3 Wiring layer-1 0.6mil DDR 1 channel data, address L4 Ground Plane-2 0.6mil L5 Wiring layer-2 0.6mil DDR 1 channel data, address L6 Ground Plane-3 0.6mil L7 Wiring layer-3 0.6mil DDR 2 channel data, address L8 Ground Plane -4 0.6mil L9 Wiring layer-4 0.6mil DDR 2 channel data, address L10 Ground level -5 0.6mil L11 Power layer-1 1.2mil Other power supplies L12 Power Layer-2 2mil CPU core voltage power supply / ground plane L13 Power Layer-3 2mil CPU core voltage power supply L14 Power Layer-3 1.2mil Other power supplies L15 Ground level -7 0.6mil L16 Wiring layer-5 0.6mil DDR 3 channel data, address L17 Ground level -8 0.6mil L18 Wiring layer-6 0.6mil DDR 3 channel data, address L19 Ground level -9 0.6mil L20 Wiring layer-7 0.6mil DDR 4-channel data, address L21 Ground level -10 0.6mil L22 Wiring layer-8 0.6mil DDR 4-channel data, address L23 Ground level -11 0.6mil L24 Device bottom 2mil Device Fanout

[0049] based on Figure 3In a feasible implementation of the server motherboard shown, the first ground layer, the second ground layer, and the power layer are routed using through holes.

[0050] In this implementation, the ground and power planes are connected via vias, ensuring stable power supply and good signal grounding. Furthermore, since server motherboards generate significant heat during operation, vias serve as heat dissipation channels, helping to conduct heat away from components and out of the PCB, thereby improving the thermal efficiency of the entire system.

[0051] based on Figure 3 In a feasible implementation of the server motherboard shown, the power supply layer has a centrally symmetrical structure.

[0052] In this embodiment, the centrally symmetrical power plane can provide good electromagnetic compatibility (EMC) because this layout helps reduce electromagnetic interference (EMI). In addition, the symmetrical design can also provide more uniform current distribution, thereby improving the efficiency and thermal management performance of the power supply.

[0053] based on Figure 3 In a feasible implementation of the server motherboard shown, the power supply layer includes two CPU power supply layers, and the two CPU power supply layers are symmetrical about the center of the power supply layer.

[0054] In this embodiment, the CPU power supply layer can also be called the CPU core voltage power supply. The symmetrically distributed power supply layer can reduce the impedance of the power supply path because the current can be more evenly distributed on different CPU power supply layers. This can reduce the voltage drop caused by current congestion, thereby improving voltage stability. The symmetrical power supply design can improve the power conversion efficiency because the current is distributed more evenly, reducing the additional power consumption caused by unbalanced load.

[0055] based on Figure 3 In a feasible implementation of the server motherboard shown, signals between the CPU and the multi-layer PCB motherboard are transmitted using through-holes.

[0056] In this implementation, the CPU area typically generates a lot of heat. Using through-holes can provide a better heat conduction path, helping to transfer heat from the heat source to other parts of the PCB or heat dissipation structures. Through-holes can increase the copper area, thereby improving heat conduction efficiency. In one example, the CPU area and the corresponding DDR signals on the top side can also be fanouted using mechanical blind vias, and the DDR signals on the bottom side can be fanouted using through-holes.

[0057] based on Figure 3In one feasible embodiment of the server motherboard shown, the through hole includes a first through hole and a second through hole, the CPU is connected to the first wiring layer through the first through hole, and transmits signals with the first memory chip through the first wiring layer;

[0058] The CPU is connected to the second wiring layer through the second through hole and performs signal transmission with the second memory particle through the second wiring layer.

[0059] In this embodiment, the CPU is connected to the first wiring layer via the first through-hole. That is, the CPU signal passes through the PCB through the first through-hole and is connected to the first wiring layer. When the CPU signal reaches the first wiring layer, data can be exchanged with the first memory chip through the wiring on the first wiring layer.

[0060] The CPU signal penetrates the PCB through the second through-hole and is connected to the second wiring layer. Through the wiring of the second wiring layer, the CPU signal can be transmitted to the second memory particle to realize data communication with the second memory particle.

[0061] based on Figure 3 In a feasible implementation of the server motherboard shown, the PCB stack is a double-sided PCB board.

[0062] In this embodiment, each layer of a multilayer PCB is a complete double-sided PCB. This double-sided PCB design allows for routing on both sides of the PCB, which is particularly useful in space-constrained applications such as portable electronic devices or high-density servers. Double-sided routing also reduces signal transmission distance, helping to improve signal integrity and reduce signal attenuation and interference.

[0063] based on Figure 3 In a feasible implementation of the server motherboard shown, the multi-layer PCB motherboard is generated by stacking and pressing double-sided PCB boards.

[0064] In this implementation, multiple inner-layer circuit boards (including double-sided PCBs) and prepreg sheets (for interlayer insulation and bonding) are alternately stacked. These layers are pressed together using a laminator under high temperature and pressure to form a single, integrated multi-layer PCB. The laminated PCBs are then drilled with the necessary through-holes and blind vias for component pin insertion and interlayer circuit connections. The vias are then electroplated to form a conductive copper coating, ensuring interlayer circuit connectivity.

[0065] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the illustrative use of the above terms does not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0066] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and purpose of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A server motherboard, characterized in that: The system comprises a multi-layer printed circuit board (PCB), a central processing unit (CPU), multiple memory chips, and a power supply. The multi-layer PCB comprises multiple PCB layers stacked one on top of the other. Each PCB layer transmits a different signal, and the signals between different PCB layers are interconnected via mechanical blind vias. The multiple memory particles include a first memory particle configured on the top TOP surface of the PCB mainboard and a second memory particle configured on the bottom BOTTOM surface of the PCB mainboard. The first memory particle and the second memory particle include multiple memory particles. The first memory particle and the second memory particle are configured on the memory channel of the CPU in a one-to-one manner. The multiple PCB stacks stacked layer by layer include a first stack for transmitting the signal of the first memory particle, a second stack for transmitting the signal of the second memory particle, and a third stack for carrying the power supply. The first stack and the second stack have structural symmetry based on the third stack.

2. A server motherboard according to claim 1, characterized in that: The CPU has a 4-channel memory on one side, with the first memory particles of 2 channels configured on the TOP surface, and the second memory particles of another 2 channels configured on the BOTTOM surface in positions symmetrical to the first memory particles.

3. The server motherboard according to claim 1, wherein: The number of PCB stacks is 24, the first stack includes 5 first ground layers, 4 first wiring layers and a TOP surface layer, the first ground layer and the first wiring layer are stacked alternately, the second stack includes 5 second ground layers, 4 second wiring layers and a BOTTOM surface layer, the second ground layer and the second wiring layer are stacked alternately, the third stack includes 4 power supply layers, the first wiring layer is used to transmit the signal of the first memory particle, and the second wiring layer is used to transmit the signal of the second memory particle.

4. A server motherboard according to claim 3, characterized in that: The first ground layer, the second ground layer and the power layer are routed using through holes.

5. The server motherboard according to claim 3, wherein: The power supply layer has a central symmetrical structure.

6. The server motherboard according to claim 3, wherein: The power supply layer includes two CPU power supply layers, and the two CPU power supply layers are symmetrical based on the center of the power supply layer.

7. The server motherboard according to claim 3, wherein: The signals between the CPU and the multi-layer PCB mainboard are transmitted using through holes.

8. The server motherboard according to claim 7, wherein: The through hole includes a first through hole and a second through hole, the CPU is connected to the first wiring layer through the first through hole, and performs signal transmission with the first memory chip through the first wiring layer; The CPU is connected to the second wiring layer through the second through-hole, and performs signal transmission with the second memory chip through the second wiring layer.

9. The server motherboard according to claim 1, wherein: The PCB stack is a double-sided PCB board.

10. The server motherboard according to claim 9, wherein: The multi-layer PCB main board is generated by stacking and pressing the double-sided PCB boards.

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